1 //===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAG class, which is used as the common
11 // base class for instruction schedulers.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULEDAG_H
16 #define LLVM_CODEGEN_SCHEDULEDAG_H
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/GraphTraits.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/PointerIntPair.h"
29 class MachineConstantPool;
30 class MachineFunction;
31 class MachineRegisterInfo;
33 class TargetRegisterInfo;
36 class TargetInstrInfo;
37 class TargetInstrDesc;
39 class TargetRegisterClass;
40 template<class Graph> class GraphWriter;
42 /// SDep - Scheduling dependency. This represents one direction of an
43 /// edge in the scheduling DAG.
46 /// Kind - These are the different kinds of scheduling dependencies.
48 Data, ///< Regular data dependence (aka true-dependence).
49 Anti, ///< A register anti-dependedence (aka WAR).
50 Output, ///< A register output-dependence (aka WAW).
51 Order ///< Any other ordering dependency.
55 /// Dep - A pointer to the depending/depended-on SUnit, and an enum
56 /// indicating the kind of the dependency.
57 PointerIntPair<SUnit *, 2, Kind> Dep;
59 /// Contents - A union discriminated by the dependence kind.
61 /// Reg - For Data, Anti, and Output dependencies, the associated
62 /// register. For Data dependencies that don't currently have a register
63 /// assigned, this is set to zero.
66 /// Order - Additional information about Order dependencies.
68 /// isNormalMemory - True if both sides of the dependence
69 /// access memory in non-volatile and fully modeled ways.
70 bool isNormalMemory : 1;
72 /// isMustAlias - True if both sides of the dependence are known to
73 /// access the same memory.
76 /// isArtificial - True if this is an artificial dependency, meaning
77 /// it is not necessary for program correctness, and may be safely
78 /// deleted if necessary.
79 bool isArtificial : 1;
83 /// Latency - The time associated with this edge. Often this is just
84 /// the value of the Latency field of the predecessor, however advanced
85 /// models may provide additional information about specific edges.
89 /// SDep - Construct a null SDep. This is only for use by container
90 /// classes which require default constructors. SUnits may not
91 /// have null SDep edges.
92 SDep() : Dep(0, Data) {}
94 /// SDep - Construct an SDep with the specified values.
95 SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0,
96 bool isNormalMemory = false, bool isMustAlias = false,
97 bool isArtificial = false)
98 : Dep(S, kind), Contents(), Latency(latency) {
103 "SDep::Anti and SDep::Output must use a non-zero Reg!");
106 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!");
107 assert(!isArtificial && "isArtificial only applies with SDep::Order!");
111 assert(Reg == 0 && "Reg given for non-register dependence!");
112 Contents.Order.isNormalMemory = isNormalMemory;
113 Contents.Order.isMustAlias = isMustAlias;
114 Contents.Order.isArtificial = isArtificial;
119 bool operator==(const SDep &Other) const {
120 if (Dep != Other.Dep || Latency != Other.Latency) return false;
121 switch (Dep.getInt()) {
125 return Contents.Reg == Other.Contents.Reg;
127 return Contents.Order.isNormalMemory ==
128 Other.Contents.Order.isNormalMemory &&
129 Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias &&
130 Contents.Order.isArtificial == Other.Contents.Order.isArtificial;
132 assert(0 && "Invalid dependency kind!");
136 bool operator!=(const SDep &Other) const {
137 return !operator==(Other);
140 /// getLatency - Return the latency value for this edge, which roughly
141 /// means the minimum number of cycles that must elapse between the
142 /// predecessor and the successor, given that they have this edge
144 unsigned getLatency() const {
148 /// setLatency - Set the latency for this edge.
149 void setLatency(unsigned Lat) {
153 //// getSUnit - Return the SUnit to which this edge points.
154 SUnit *getSUnit() const {
155 return Dep.getPointer();
158 //// setSUnit - Assign the SUnit to which this edge points.
159 void setSUnit(SUnit *SU) {
163 /// getKind - Return an enum value representing the kind of the dependence.
164 Kind getKind() const {
168 /// isCtrl - Shorthand for getKind() != SDep::Data.
169 bool isCtrl() const {
170 return getKind() != Data;
173 /// isNormalMemory - Test if this is an Order dependence between two
174 /// memory accesses where both sides of the dependence access memory
175 /// in non-volatile and fully modeled ways.
176 bool isNormalMemory() const {
177 return getKind() == Order && Contents.Order.isNormalMemory;
180 /// isMustAlias - Test if this is an Order dependence that is marked
181 /// as "must alias", meaning that the SUnits at either end of the edge
182 /// have a memory dependence on a known memory location.
183 bool isMustAlias() const {
184 return getKind() == Order && Contents.Order.isMustAlias;
187 /// isArtificial - Test if this is an Order dependence that is marked
188 /// as "artificial", meaning it isn't necessary for correctness.
189 bool isArtificial() const {
190 return getKind() == Order && Contents.Order.isArtificial;
193 /// isAssignedRegDep - Test if this is a Data dependence that is
194 /// associated with a register.
195 bool isAssignedRegDep() const {
196 return getKind() == Data && Contents.Reg != 0;
199 /// getReg - Return the register associated with this edge. This is
200 /// only valid on Data, Anti, and Output edges. On Data edges, this
201 /// value may be zero, meaning there is no associated register.
202 unsigned getReg() const {
203 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
204 "getReg called on non-register dependence edge!");
208 /// setReg - Assign the associated register for this edge. This is
209 /// only valid on Data, Anti, and Output edges. On Anti and Output
210 /// edges, this value must not be zero. On Data edges, the value may
211 /// be zero, which would mean that no specific register is associated
213 void setReg(unsigned Reg) {
214 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
215 "setReg called on non-register dependence edge!");
216 assert((getKind() != Anti || Reg != 0) &&
217 "SDep::Anti edge cannot use the zero register!");
218 assert((getKind() != Output || Reg != 0) &&
219 "SDep::Output edge cannot use the zero register!");
225 struct isPodLike<SDep> { static const bool value = true; };
227 /// SUnit - Scheduling unit. This is a node in the scheduling DAG.
230 SDNode *Node; // Representative node.
231 MachineInstr *Instr; // Alternatively, a MachineInstr.
233 SUnit *OrigNode; // If not this, the node from which
234 // this node was cloned.
236 // Preds/Succs - The SUnits before/after us in the graph. The boolean value
237 // is true if the edge is a token chain edge, false if it is a value edge.
238 SmallVector<SDep, 4> Preds; // All sunit predecessors.
239 SmallVector<SDep, 4> Succs; // All sunit successors.
241 typedef SmallVector<SDep, 4>::iterator pred_iterator;
242 typedef SmallVector<SDep, 4>::iterator succ_iterator;
243 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;
244 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;
246 unsigned NodeNum; // Entry # of node in the node vector.
247 unsigned NodeQueueId; // Queue id of node.
248 unsigned NumPreds; // # of SDep::Data preds.
249 unsigned NumSuccs; // # of SDep::Data sucss.
250 unsigned NumPredsLeft; // # of preds not scheduled.
251 unsigned NumSuccsLeft; // # of succs not scheduled.
252 unsigned short Latency; // Node latency.
253 bool isCall : 1; // Is a function call.
254 bool isTwoAddress : 1; // Is a two-address instruction.
255 bool isCommutable : 1; // Is a commutable instruction.
256 bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
257 bool hasPhysRegClobbers : 1; // Has any physreg defs, used or not.
258 bool isPending : 1; // True once pending.
259 bool isAvailable : 1; // True once available.
260 bool isScheduled : 1; // True once scheduled.
261 bool isScheduleHigh : 1; // True if preferable to schedule high.
262 bool isCloned : 1; // True if this node has been cloned.
263 Sched::Preference SchedulingPref; // Scheduling preference.
265 SmallVector<MachineInstr*, 4> DbgInstrList; // dbg_values referencing this.
267 bool isDepthCurrent : 1; // True if Depth is current.
268 bool isHeightCurrent : 1; // True if Height is current.
269 unsigned Depth; // Node depth.
270 unsigned Height; // Node height.
272 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
273 const TargetRegisterClass *CopySrcRC;
275 /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent
276 /// an SDNode and any nodes flagged to it.
277 SUnit(SDNode *node, unsigned nodenum)
278 : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum),
279 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
280 NumSuccsLeft(0), Latency(0),
281 isCall(false), isTwoAddress(false), isCommutable(false),
282 hasPhysRegDefs(false), hasPhysRegClobbers(false),
283 isPending(false), isAvailable(false), isScheduled(false),
284 isScheduleHigh(false), isCloned(false),
285 SchedulingPref(Sched::None),
286 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
287 CopyDstRC(NULL), CopySrcRC(NULL) {}
289 /// SUnit - Construct an SUnit for post-regalloc scheduling to represent
291 SUnit(MachineInstr *instr, unsigned nodenum)
292 : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum),
293 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
294 NumSuccsLeft(0), Latency(0),
295 isCall(false), isTwoAddress(false), isCommutable(false),
296 hasPhysRegDefs(false), hasPhysRegClobbers(false),
297 isPending(false), isAvailable(false), isScheduled(false),
298 isScheduleHigh(false), isCloned(false),
299 SchedulingPref(Sched::None),
300 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
301 CopyDstRC(NULL), CopySrcRC(NULL) {}
303 /// SUnit - Construct a placeholder SUnit.
305 : Node(0), Instr(0), OrigNode(0), NodeNum(~0u),
306 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
307 NumSuccsLeft(0), Latency(0),
308 isCall(false), isTwoAddress(false), isCommutable(false),
309 hasPhysRegDefs(false), hasPhysRegClobbers(false),
310 isPending(false), isAvailable(false), isScheduled(false),
311 isScheduleHigh(false), isCloned(false),
312 SchedulingPref(Sched::None),
313 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
314 CopyDstRC(NULL), CopySrcRC(NULL) {}
316 /// setNode - Assign the representative SDNode for this SUnit.
317 /// This may be used during pre-regalloc scheduling.
318 void setNode(SDNode *N) {
319 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
323 /// getNode - Return the representative SDNode for this SUnit.
324 /// This may be used during pre-regalloc scheduling.
325 SDNode *getNode() const {
326 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
330 /// setInstr - Assign the instruction for the SUnit.
331 /// This may be used during post-regalloc scheduling.
332 void setInstr(MachineInstr *MI) {
333 assert(!Node && "Setting MachineInstr of SUnit with SDNode!");
337 /// getInstr - Return the representative MachineInstr for this SUnit.
338 /// This may be used during post-regalloc scheduling.
339 MachineInstr *getInstr() const {
340 assert(!Node && "Reading MachineInstr of SUnit with SDNode!");
344 /// addPred - This adds the specified edge as a pred of the current node if
345 /// not already. It also adds the current node as a successor of the
347 void addPred(const SDep &D);
349 /// removePred - This removes the specified edge as a pred of the current
350 /// node if it exists. It also removes the current node as a successor of
351 /// the specified node.
352 void removePred(const SDep &D);
354 /// getDepth - Return the depth of this node, which is the length of the
355 /// maximum path up to any node with has no predecessors.
356 unsigned getDepth() const {
358 const_cast<SUnit *>(this)->ComputeDepth();
362 /// getHeight - Return the height of this node, which is the length of the
363 /// maximum path down to any node with has no successors.
364 unsigned getHeight() const {
365 if (!isHeightCurrent)
366 const_cast<SUnit *>(this)->ComputeHeight();
370 /// setDepthToAtLeast - If NewDepth is greater than this node's
371 /// depth value, set it to be the new depth value. This also
372 /// recursively marks successor nodes dirty.
373 void setDepthToAtLeast(unsigned NewDepth);
375 /// setDepthToAtLeast - If NewDepth is greater than this node's
376 /// depth value, set it to be the new height value. This also
377 /// recursively marks predecessor nodes dirty.
378 void setHeightToAtLeast(unsigned NewHeight);
380 /// setDepthDirty - Set a flag in this node to indicate that its
381 /// stored Depth value will require recomputation the next time
382 /// getDepth() is called.
383 void setDepthDirty();
385 /// setHeightDirty - Set a flag in this node to indicate that its
386 /// stored Height value will require recomputation the next time
387 /// getHeight() is called.
388 void setHeightDirty();
390 /// isPred - Test if node N is a predecessor of this node.
391 bool isPred(SUnit *N) {
392 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
393 if (Preds[i].getSUnit() == N)
398 /// isSucc - Test if node N is a successor of this node.
399 bool isSucc(SUnit *N) {
400 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)
401 if (Succs[i].getSUnit() == N)
406 void dump(const ScheduleDAG *G) const;
407 void dumpAll(const ScheduleDAG *G) const;
408 void print(raw_ostream &O, const ScheduleDAG *G) const;
412 void ComputeHeight();
415 //===--------------------------------------------------------------------===//
416 /// SchedulingPriorityQueue - This interface is used to plug different
417 /// priorities computation algorithms into the list scheduler. It implements
418 /// the interface of a standard priority queue, where nodes are inserted in
419 /// arbitrary order and returned in priority order. The computation of the
420 /// priority and the representation of the queue are totally up to the
421 /// implementation to decide.
423 class SchedulingPriorityQueue {
426 SchedulingPriorityQueue() : CurCycle(0) {}
427 virtual ~SchedulingPriorityQueue() {}
429 virtual void initNodes(std::vector<SUnit> &SUnits) = 0;
430 virtual void addNode(const SUnit *SU) = 0;
431 virtual void updateNode(const SUnit *SU) = 0;
432 virtual void releaseState() = 0;
434 virtual bool empty() const = 0;
435 virtual void push(SUnit *U) = 0;
437 void push_all(const std::vector<SUnit *> &Nodes) {
438 for (std::vector<SUnit *>::const_iterator I = Nodes.begin(),
439 E = Nodes.end(); I != E; ++I)
443 virtual SUnit *pop() = 0;
445 virtual void remove(SUnit *SU) = 0;
447 /// ScheduledNode - As each node is scheduled, this method is invoked. This
448 /// allows the priority function to adjust the priority of related
449 /// unscheduled nodes, for example.
451 virtual void ScheduledNode(SUnit *) {}
453 virtual void UnscheduledNode(SUnit *) {}
455 void setCurCycle(unsigned Cycle) {
459 unsigned getCurCycle() const {
466 MachineBasicBlock *BB; // The block in which to insert instructions
467 MachineBasicBlock::iterator InsertPos;// The position to insert instructions
468 const TargetMachine &TM; // Target processor
469 const TargetInstrInfo *TII; // Target instruction information
470 const TargetRegisterInfo *TRI; // Target processor register info
471 MachineFunction &MF; // Machine function
472 MachineRegisterInfo &MRI; // Virtual/real register map
473 std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s
474 // represent noop instructions.
475 std::vector<SUnit> SUnits; // The scheduling units.
476 SUnit EntrySU; // Special node for the region entry.
477 SUnit ExitSU; // Special node for the region exit.
479 explicit ScheduleDAG(MachineFunction &mf);
481 virtual ~ScheduleDAG();
483 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered
488 /// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock
489 /// according to the order specified in Sequence.
491 virtual MachineBasicBlock *EmitSchedule() = 0;
493 void dumpSchedule() const;
495 virtual void dumpNode(const SUnit *SU) const = 0;
497 /// getGraphNodeLabel - Return a label for an SUnit node in a visualization
498 /// of the ScheduleDAG.
499 virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0;
501 /// addCustomGraphFeatures - Add custom features for a visualization of
503 virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {}
506 /// VerifySchedule - Verify that all SUnits were scheduled and that
507 /// their state is consistent.
508 void VerifySchedule(bool isBottomUp);
512 /// Run - perform scheduling.
514 void Run(MachineBasicBlock *bb, MachineBasicBlock::iterator insertPos);
516 /// BuildSchedGraph - Build SUnits and set up their Preds and Succs
517 /// to form the scheduling dependency graph.
519 virtual void BuildSchedGraph(AliasAnalysis *AA) = 0;
521 /// ComputeLatency - Compute node latency.
523 virtual void ComputeLatency(SUnit *SU) = 0;
525 /// ComputeOperandLatency - Override dependence edge latency using
526 /// operand use/def information
528 virtual void ComputeOperandLatency(SUnit *, SUnit *,
531 /// Schedule - Order nodes according to selected style, filling
532 /// in the Sequence member.
534 virtual void Schedule() = 0;
536 /// ForceUnitLatencies - Return true if all scheduling edges should be given
537 /// a latency value of one. The default is to return false; schedulers may
538 /// override this as needed.
539 virtual bool ForceUnitLatencies() const { return false; }
541 /// EmitNoop - Emit a noop instruction.
545 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap);
548 class SUnitIterator : public std::iterator<std::forward_iterator_tag,
553 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
555 bool operator==(const SUnitIterator& x) const {
556 return Operand == x.Operand;
558 bool operator!=(const SUnitIterator& x) const { return !operator==(x); }
560 const SUnitIterator &operator=(const SUnitIterator &I) {
561 assert(I.Node==Node && "Cannot assign iterators to two different nodes!");
566 pointer operator*() const {
567 return Node->Preds[Operand].getSUnit();
569 pointer operator->() const { return operator*(); }
571 SUnitIterator& operator++() { // Preincrement
575 SUnitIterator operator++(int) { // Postincrement
576 SUnitIterator tmp = *this; ++*this; return tmp;
579 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
580 static SUnitIterator end (SUnit *N) {
581 return SUnitIterator(N, (unsigned)N->Preds.size());
584 unsigned getOperand() const { return Operand; }
585 const SUnit *getNode() const { return Node; }
586 /// isCtrlDep - Test if this is not an SDep::Data dependence.
587 bool isCtrlDep() const {
588 return getSDep().isCtrl();
590 bool isArtificialDep() const {
591 return getSDep().isArtificial();
593 const SDep &getSDep() const {
594 return Node->Preds[Operand];
598 template <> struct GraphTraits<SUnit*> {
599 typedef SUnit NodeType;
600 typedef SUnitIterator ChildIteratorType;
601 static inline NodeType *getEntryNode(SUnit *N) { return N; }
602 static inline ChildIteratorType child_begin(NodeType *N) {
603 return SUnitIterator::begin(N);
605 static inline ChildIteratorType child_end(NodeType *N) {
606 return SUnitIterator::end(N);
610 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> {
611 typedef std::vector<SUnit>::iterator nodes_iterator;
612 static nodes_iterator nodes_begin(ScheduleDAG *G) {
613 return G->SUnits.begin();
615 static nodes_iterator nodes_end(ScheduleDAG *G) {
616 return G->SUnits.end();
620 /// ScheduleDAGTopologicalSort is a class that computes a topological
621 /// ordering for SUnits and provides methods for dynamically updating
622 /// the ordering as new edges are added.
624 /// This allows a very fast implementation of IsReachable, for example.
626 class ScheduleDAGTopologicalSort {
627 /// SUnits - A reference to the ScheduleDAG's SUnits.
628 std::vector<SUnit> &SUnits;
630 /// Index2Node - Maps topological index to the node number.
631 std::vector<int> Index2Node;
632 /// Node2Index - Maps the node number to its topological index.
633 std::vector<int> Node2Index;
634 /// Visited - a set of nodes visited during a DFS traversal.
637 /// DFS - make a DFS traversal and mark all nodes affected by the
638 /// edge insertion. These nodes will later get new topological indexes
639 /// by means of the Shift method.
640 void DFS(const SUnit *SU, int UpperBound, bool& HasLoop);
642 /// Shift - reassign topological indexes for the nodes in the DAG
643 /// to preserve the topological ordering.
644 void Shift(BitVector& Visited, int LowerBound, int UpperBound);
646 /// Allocate - assign the topological index to the node n.
647 void Allocate(int n, int index);
650 explicit ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits);
652 /// InitDAGTopologicalSorting - create the initial topological
653 /// ordering from the DAG to be scheduled.
654 void InitDAGTopologicalSorting();
656 /// IsReachable - Checks if SU is reachable from TargetSU.
657 bool IsReachable(const SUnit *SU, const SUnit *TargetSU);
659 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU
660 /// will create a cycle.
661 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU);
663 /// AddPred - Updates the topological ordering to accomodate an edge
664 /// to be added from SUnit X to SUnit Y.
665 void AddPred(SUnit *Y, SUnit *X);
667 /// RemovePred - Updates the topological ordering to accomodate an
668 /// an edge to be removed from the specified node N from the predecessors
669 /// of the current node M.
670 void RemovePred(SUnit *M, SUnit *N);
672 typedef std::vector<int>::iterator iterator;
673 typedef std::vector<int>::const_iterator const_iterator;
674 iterator begin() { return Index2Node.begin(); }
675 const_iterator begin() const { return Index2Node.begin(); }
676 iterator end() { return Index2Node.end(); }
677 const_iterator end() const { return Index2Node.end(); }
679 typedef std::vector<int>::reverse_iterator reverse_iterator;
680 typedef std::vector<int>::const_reverse_iterator const_reverse_iterator;
681 reverse_iterator rbegin() { return Index2Node.rbegin(); }
682 const_reverse_iterator rbegin() const { return Index2Node.rbegin(); }
683 reverse_iterator rend() { return Index2Node.rend(); }
684 const_reverse_iterator rend() const { return Index2Node.rend(); }