1 //===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAG class, which is used as the common
11 // base class for instruction schedulers.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_SCHEDULEDAG_H
16 #define LLVM_CODEGEN_SCHEDULEDAG_H
18 #include "llvm/CodeGen/MachineBasicBlock.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/ADT/DenseMap.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/GraphTraits.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/PointerIntPair.h"
29 class MachineConstantPool;
30 class MachineFunction;
31 class MachineRegisterInfo;
33 class TargetRegisterInfo;
36 class TargetInstrInfo;
37 class TargetInstrDesc;
39 class TargetRegisterClass;
40 template<class Graph> class GraphWriter;
42 /// SDep - Scheduling dependency. This represents one direction of an
43 /// edge in the scheduling DAG.
46 /// Kind - These are the different kinds of scheduling dependencies.
48 Data, ///< Regular data dependence (aka true-dependence).
49 Anti, ///< A register anti-dependedence (aka WAR).
50 Output, ///< A register output-dependence (aka WAW).
51 Order ///< Any other ordering dependency.
55 /// Dep - A pointer to the depending/depended-on SUnit, and an enum
56 /// indicating the kind of the dependency.
57 PointerIntPair<SUnit *, 2, Kind> Dep;
59 /// Contents - A union discriminated by the dependence kind.
61 /// Reg - For Data, Anti, and Output dependencies, the associated
62 /// register. For Data dependencies that don't currently have a register
63 /// assigned, this is set to zero.
66 /// Order - Additional information about Order dependencies.
68 /// isNormalMemory - True if both sides of the dependence
69 /// access memory in non-volatile and fully modeled ways.
70 bool isNormalMemory : 1;
72 /// isMustAlias - True if both sides of the dependence are known to
73 /// access the same memory.
76 /// isArtificial - True if this is an artificial dependency, meaning
77 /// it is not necessary for program correctness, and may be safely
78 /// deleted if necessary.
79 bool isArtificial : 1;
83 /// Latency - The time associated with this edge. Often this is just
84 /// the value of the Latency field of the predecessor, however advanced
85 /// models may provide additional information about specific edges.
89 /// SDep - Construct a null SDep. This is only for use by container
90 /// classes which require default constructors. SUnits may not
91 /// have null SDep edges.
92 SDep() : Dep(0, Data) {}
94 /// SDep - Construct an SDep with the specified values.
95 SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0,
96 bool isNormalMemory = false, bool isMustAlias = false,
97 bool isArtificial = false)
98 : Dep(S, kind), Contents(), Latency(latency) {
103 "SDep::Anti and SDep::Output must use a non-zero Reg!");
106 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!");
107 assert(!isArtificial && "isArtificial only applies with SDep::Order!");
111 assert(Reg == 0 && "Reg given for non-register dependence!");
112 Contents.Order.isNormalMemory = isNormalMemory;
113 Contents.Order.isMustAlias = isMustAlias;
114 Contents.Order.isArtificial = isArtificial;
119 bool operator==(const SDep &Other) const {
120 if (Dep != Other.Dep || Latency != Other.Latency) return false;
121 switch (Dep.getInt()) {
125 return Contents.Reg == Other.Contents.Reg;
127 return Contents.Order.isNormalMemory ==
128 Other.Contents.Order.isNormalMemory &&
129 Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias &&
130 Contents.Order.isArtificial == Other.Contents.Order.isArtificial;
132 assert(0 && "Invalid dependency kind!");
136 bool operator!=(const SDep &Other) const {
137 return !operator==(Other);
140 /// getLatency - Return the latency value for this edge, which roughly
141 /// means the minimum number of cycles that must elapse between the
142 /// predecessor and the successor, given that they have this edge
144 unsigned getLatency() const {
148 /// setLatency - Set the latency for this edge.
149 void setLatency(unsigned Lat) {
153 //// getSUnit - Return the SUnit to which this edge points.
154 SUnit *getSUnit() const {
155 return Dep.getPointer();
158 //// setSUnit - Assign the SUnit to which this edge points.
159 void setSUnit(SUnit *SU) {
163 /// getKind - Return an enum value representing the kind of the dependence.
164 Kind getKind() const {
168 /// isCtrl - Shorthand for getKind() != SDep::Data.
169 bool isCtrl() const {
170 return getKind() != Data;
173 /// isNormalMemory - Test if this is an Order dependence between two
174 /// memory accesses where both sides of the dependence access memory
175 /// in non-volatile and fully modeled ways.
176 bool isNormalMemory() const {
177 return getKind() == Order && Contents.Order.isNormalMemory;
180 /// isMustAlias - Test if this is an Order dependence that is marked
181 /// as "must alias", meaning that the SUnits at either end of the edge
182 /// have a memory dependence on a known memory location.
183 bool isMustAlias() const {
184 return getKind() == Order && Contents.Order.isMustAlias;
187 /// isArtificial - Test if this is an Order dependence that is marked
188 /// as "artificial", meaning it isn't necessary for correctness.
189 bool isArtificial() const {
190 return getKind() == Order && Contents.Order.isArtificial;
193 /// isAssignedRegDep - Test if this is a Data dependence that is
194 /// associated with a register.
195 bool isAssignedRegDep() const {
196 return getKind() == Data && Contents.Reg != 0;
199 /// getReg - Return the register associated with this edge. This is
200 /// only valid on Data, Anti, and Output edges. On Data edges, this
201 /// value may be zero, meaning there is no associated register.
202 unsigned getReg() const {
203 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
204 "getReg called on non-register dependence edge!");
208 /// setReg - Assign the associated register for this edge. This is
209 /// only valid on Data, Anti, and Output edges. On Anti and Output
210 /// edges, this value must not be zero. On Data edges, the value may
211 /// be zero, which would mean that no specific register is associated
213 void setReg(unsigned Reg) {
214 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
215 "setReg called on non-register dependence edge!");
216 assert((getKind() != Anti || Reg != 0) &&
217 "SDep::Anti edge cannot use the zero register!");
218 assert((getKind() != Output || Reg != 0) &&
219 "SDep::Output edge cannot use the zero register!");
224 /// SUnit - Scheduling unit. This is a node in the scheduling DAG.
227 SDNode *Node; // Representative node.
228 MachineInstr *Instr; // Alternatively, a MachineInstr.
230 SUnit *OrigNode; // If not this, the node from which
231 // this node was cloned.
233 // Preds/Succs - The SUnits before/after us in the graph. The boolean value
234 // is true if the edge is a token chain edge, false if it is a value edge.
235 SmallVector<SDep, 4> Preds; // All sunit predecessors.
236 SmallVector<SDep, 4> Succs; // All sunit successors.
238 typedef SmallVector<SDep, 4>::iterator pred_iterator;
239 typedef SmallVector<SDep, 4>::iterator succ_iterator;
240 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;
241 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;
243 unsigned NodeNum; // Entry # of node in the node vector.
244 unsigned NodeQueueId; // Queue id of node.
245 unsigned short Latency; // Node latency.
246 unsigned NumPreds; // # of SDep::Data preds.
247 unsigned NumSuccs; // # of SDep::Data sucss.
248 unsigned NumPredsLeft; // # of preds not scheduled.
249 unsigned NumSuccsLeft; // # of succs not scheduled.
250 bool isCall : 1; // Is a function call.
251 bool isTwoAddress : 1; // Is a two-address instruction.
252 bool isCommutable : 1; // Is a commutable instruction.
253 bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
254 bool hasPhysRegClobbers : 1; // Has any physreg defs, used or not.
255 bool isPending : 1; // True once pending.
256 bool isAvailable : 1; // True once available.
257 bool isScheduled : 1; // True once scheduled.
258 bool isScheduleHigh : 1; // True if preferable to schedule high.
259 bool isCloned : 1; // True if this node has been cloned.
260 Sched::Preference SchedulingPref; // Scheduling preference.
262 SmallVector<MachineInstr*, 4> DbgInstrList; // dbg_values referencing this.
264 bool isDepthCurrent : 1; // True if Depth is current.
265 bool isHeightCurrent : 1; // True if Height is current.
266 unsigned Depth; // Node depth.
267 unsigned Height; // Node height.
269 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
270 const TargetRegisterClass *CopySrcRC;
272 /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent
273 /// an SDNode and any nodes flagged to it.
274 SUnit(SDNode *node, unsigned nodenum)
275 : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum),
276 NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
278 isCall(false), isTwoAddress(false), isCommutable(false),
279 hasPhysRegDefs(false), hasPhysRegClobbers(false),
280 isPending(false), isAvailable(false), isScheduled(false),
281 isScheduleHigh(false), isCloned(false),
282 SchedulingPref(Sched::None),
283 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
284 CopyDstRC(NULL), CopySrcRC(NULL) {}
286 /// SUnit - Construct an SUnit for post-regalloc scheduling to represent
288 SUnit(MachineInstr *instr, unsigned nodenum)
289 : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum),
290 NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
292 isCall(false), isTwoAddress(false), isCommutable(false),
293 hasPhysRegDefs(false), hasPhysRegClobbers(false),
294 isPending(false), isAvailable(false), isScheduled(false),
295 isScheduleHigh(false), isCloned(false),
296 SchedulingPref(Sched::None),
297 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
298 CopyDstRC(NULL), CopySrcRC(NULL) {}
300 /// SUnit - Construct a placeholder SUnit.
302 : Node(0), Instr(0), OrigNode(0), NodeNum(~0u),
303 NodeQueueId(0), Latency(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
305 isCall(false), isTwoAddress(false), isCommutable(false),
306 hasPhysRegDefs(false), hasPhysRegClobbers(false),
307 isPending(false), isAvailable(false), isScheduled(false),
308 isScheduleHigh(false), isCloned(false),
309 SchedulingPref(Sched::None),
310 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
311 CopyDstRC(NULL), CopySrcRC(NULL) {}
313 /// setNode - Assign the representative SDNode for this SUnit.
314 /// This may be used during pre-regalloc scheduling.
315 void setNode(SDNode *N) {
316 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
320 /// getNode - Return the representative SDNode for this SUnit.
321 /// This may be used during pre-regalloc scheduling.
322 SDNode *getNode() const {
323 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
327 /// setInstr - Assign the instruction for the SUnit.
328 /// This may be used during post-regalloc scheduling.
329 void setInstr(MachineInstr *MI) {
330 assert(!Node && "Setting MachineInstr of SUnit with SDNode!");
334 /// getInstr - Return the representative MachineInstr for this SUnit.
335 /// This may be used during post-regalloc scheduling.
336 MachineInstr *getInstr() const {
337 assert(!Node && "Reading MachineInstr of SUnit with SDNode!");
341 /// addPred - This adds the specified edge as a pred of the current node if
342 /// not already. It also adds the current node as a successor of the
344 void addPred(const SDep &D);
346 /// removePred - This removes the specified edge as a pred of the current
347 /// node if it exists. It also removes the current node as a successor of
348 /// the specified node.
349 void removePred(const SDep &D);
351 /// getDepth - Return the depth of this node, which is the length of the
352 /// maximum path up to any node with has no predecessors.
353 unsigned getDepth() const {
355 const_cast<SUnit *>(this)->ComputeDepth();
359 /// getHeight - Return the height of this node, which is the length of the
360 /// maximum path down to any node with has no successors.
361 unsigned getHeight() const {
362 if (!isHeightCurrent)
363 const_cast<SUnit *>(this)->ComputeHeight();
367 /// setDepthToAtLeast - If NewDepth is greater than this node's
368 /// depth value, set it to be the new depth value. This also
369 /// recursively marks successor nodes dirty.
370 void setDepthToAtLeast(unsigned NewDepth);
372 /// setDepthToAtLeast - If NewDepth is greater than this node's
373 /// depth value, set it to be the new height value. This also
374 /// recursively marks predecessor nodes dirty.
375 void setHeightToAtLeast(unsigned NewHeight);
377 /// setDepthDirty - Set a flag in this node to indicate that its
378 /// stored Depth value will require recomputation the next time
379 /// getDepth() is called.
380 void setDepthDirty();
382 /// setHeightDirty - Set a flag in this node to indicate that its
383 /// stored Height value will require recomputation the next time
384 /// getHeight() is called.
385 void setHeightDirty();
387 /// isPred - Test if node N is a predecessor of this node.
388 bool isPred(SUnit *N) {
389 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
390 if (Preds[i].getSUnit() == N)
395 /// isSucc - Test if node N is a successor of this node.
396 bool isSucc(SUnit *N) {
397 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)
398 if (Succs[i].getSUnit() == N)
403 void dump(const ScheduleDAG *G) const;
404 void dumpAll(const ScheduleDAG *G) const;
405 void print(raw_ostream &O, const ScheduleDAG *G) const;
409 void ComputeHeight();
412 //===--------------------------------------------------------------------===//
413 /// SchedulingPriorityQueue - This interface is used to plug different
414 /// priorities computation algorithms into the list scheduler. It implements
415 /// the interface of a standard priority queue, where nodes are inserted in
416 /// arbitrary order and returned in priority order. The computation of the
417 /// priority and the representation of the queue are totally up to the
418 /// implementation to decide.
420 class SchedulingPriorityQueue {
423 SchedulingPriorityQueue() : CurCycle(0) {}
424 virtual ~SchedulingPriorityQueue() {}
426 virtual void initNodes(std::vector<SUnit> &SUnits) = 0;
427 virtual void addNode(const SUnit *SU) = 0;
428 virtual void updateNode(const SUnit *SU) = 0;
429 virtual void releaseState() = 0;
431 virtual bool empty() const = 0;
432 virtual void push(SUnit *U) = 0;
434 void push_all(const std::vector<SUnit *> &Nodes) {
435 for (std::vector<SUnit *>::const_iterator I = Nodes.begin(),
436 E = Nodes.end(); I != E; ++I)
440 virtual SUnit *pop() = 0;
442 virtual void remove(SUnit *SU) = 0;
444 /// ScheduledNode - As each node is scheduled, this method is invoked. This
445 /// allows the priority function to adjust the priority of related
446 /// unscheduled nodes, for example.
448 virtual void ScheduledNode(SUnit *) {}
450 virtual void UnscheduledNode(SUnit *) {}
452 void setCurCycle(unsigned Cycle) {
456 unsigned getCurCycle() const {
463 MachineBasicBlock *BB; // The block in which to insert instructions
464 MachineBasicBlock::iterator InsertPos;// The position to insert instructions
465 const TargetMachine &TM; // Target processor
466 const TargetInstrInfo *TII; // Target instruction information
467 const TargetRegisterInfo *TRI; // Target processor register info
468 MachineFunction &MF; // Machine function
469 MachineRegisterInfo &MRI; // Virtual/real register map
470 std::vector<SUnit*> Sequence; // The schedule. Null SUnit*'s
471 // represent noop instructions.
472 std::vector<SUnit> SUnits; // The scheduling units.
473 SUnit EntrySU; // Special node for the region entry.
474 SUnit ExitSU; // Special node for the region exit.
476 explicit ScheduleDAG(MachineFunction &mf);
478 virtual ~ScheduleDAG();
480 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered
485 /// EmitSchedule - Insert MachineInstrs into the MachineBasicBlock
486 /// according to the order specified in Sequence.
488 virtual MachineBasicBlock *EmitSchedule() = 0;
490 void dumpSchedule() const;
492 virtual void dumpNode(const SUnit *SU) const = 0;
494 /// getGraphNodeLabel - Return a label for an SUnit node in a visualization
495 /// of the ScheduleDAG.
496 virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0;
498 /// addCustomGraphFeatures - Add custom features for a visualization of
500 virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {}
503 /// VerifySchedule - Verify that all SUnits were scheduled and that
504 /// their state is consistent.
505 void VerifySchedule(bool isBottomUp);
509 /// Run - perform scheduling.
511 void Run(MachineBasicBlock *bb, MachineBasicBlock::iterator insertPos);
513 /// BuildSchedGraph - Build SUnits and set up their Preds and Succs
514 /// to form the scheduling dependency graph.
516 virtual void BuildSchedGraph(AliasAnalysis *AA) = 0;
518 /// ComputeLatency - Compute node latency.
520 virtual void ComputeLatency(SUnit *SU) = 0;
522 /// ComputeOperandLatency - Override dependence edge latency using
523 /// operand use/def information
525 virtual void ComputeOperandLatency(SUnit *, SUnit *,
528 /// Schedule - Order nodes according to selected style, filling
529 /// in the Sequence member.
531 virtual void Schedule() = 0;
533 /// ForceUnitLatencies - Return true if all scheduling edges should be given
534 /// a latency value of one. The default is to return false; schedulers may
535 /// override this as needed.
536 virtual bool ForceUnitLatencies() const { return false; }
538 /// EmitNoop - Emit a noop instruction.
542 void EmitPhysRegCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseMap);
545 class SUnitIterator : public std::iterator<std::forward_iterator_tag,
550 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
552 bool operator==(const SUnitIterator& x) const {
553 return Operand == x.Operand;
555 bool operator!=(const SUnitIterator& x) const { return !operator==(x); }
557 const SUnitIterator &operator=(const SUnitIterator &I) {
558 assert(I.Node==Node && "Cannot assign iterators to two different nodes!");
563 pointer operator*() const {
564 return Node->Preds[Operand].getSUnit();
566 pointer operator->() const { return operator*(); }
568 SUnitIterator& operator++() { // Preincrement
572 SUnitIterator operator++(int) { // Postincrement
573 SUnitIterator tmp = *this; ++*this; return tmp;
576 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
577 static SUnitIterator end (SUnit *N) {
578 return SUnitIterator(N, (unsigned)N->Preds.size());
581 unsigned getOperand() const { return Operand; }
582 const SUnit *getNode() const { return Node; }
583 /// isCtrlDep - Test if this is not an SDep::Data dependence.
584 bool isCtrlDep() const {
585 return getSDep().isCtrl();
587 bool isArtificialDep() const {
588 return getSDep().isArtificial();
590 const SDep &getSDep() const {
591 return Node->Preds[Operand];
595 template <> struct GraphTraits<SUnit*> {
596 typedef SUnit NodeType;
597 typedef SUnitIterator ChildIteratorType;
598 static inline NodeType *getEntryNode(SUnit *N) { return N; }
599 static inline ChildIteratorType child_begin(NodeType *N) {
600 return SUnitIterator::begin(N);
602 static inline ChildIteratorType child_end(NodeType *N) {
603 return SUnitIterator::end(N);
607 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> {
608 typedef std::vector<SUnit>::iterator nodes_iterator;
609 static nodes_iterator nodes_begin(ScheduleDAG *G) {
610 return G->SUnits.begin();
612 static nodes_iterator nodes_end(ScheduleDAG *G) {
613 return G->SUnits.end();
617 /// ScheduleDAGTopologicalSort is a class that computes a topological
618 /// ordering for SUnits and provides methods for dynamically updating
619 /// the ordering as new edges are added.
621 /// This allows a very fast implementation of IsReachable, for example.
623 class ScheduleDAGTopologicalSort {
624 /// SUnits - A reference to the ScheduleDAG's SUnits.
625 std::vector<SUnit> &SUnits;
627 /// Index2Node - Maps topological index to the node number.
628 std::vector<int> Index2Node;
629 /// Node2Index - Maps the node number to its topological index.
630 std::vector<int> Node2Index;
631 /// Visited - a set of nodes visited during a DFS traversal.
634 /// DFS - make a DFS traversal and mark all nodes affected by the
635 /// edge insertion. These nodes will later get new topological indexes
636 /// by means of the Shift method.
637 void DFS(const SUnit *SU, int UpperBound, bool& HasLoop);
639 /// Shift - reassign topological indexes for the nodes in the DAG
640 /// to preserve the topological ordering.
641 void Shift(BitVector& Visited, int LowerBound, int UpperBound);
643 /// Allocate - assign the topological index to the node n.
644 void Allocate(int n, int index);
647 explicit ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits);
649 /// InitDAGTopologicalSorting - create the initial topological
650 /// ordering from the DAG to be scheduled.
651 void InitDAGTopologicalSorting();
653 /// IsReachable - Checks if SU is reachable from TargetSU.
654 bool IsReachable(const SUnit *SU, const SUnit *TargetSU);
656 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU
657 /// will create a cycle.
658 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU);
660 /// AddPred - Updates the topological ordering to accomodate an edge
661 /// to be added from SUnit X to SUnit Y.
662 void AddPred(SUnit *Y, SUnit *X);
664 /// RemovePred - Updates the topological ordering to accomodate an
665 /// an edge to be removed from the specified node N from the predecessors
666 /// of the current node M.
667 void RemovePred(SUnit *M, SUnit *N);
669 typedef std::vector<int>::iterator iterator;
670 typedef std::vector<int>::const_iterator const_iterator;
671 iterator begin() { return Index2Node.begin(); }
672 const_iterator begin() const { return Index2Node.begin(); }
673 iterator end() { return Index2Node.end(); }
674 const_iterator end() const { return Index2Node.end(); }
676 typedef std::vector<int>::reverse_iterator reverse_iterator;
677 typedef std::vector<int>::const_reverse_iterator const_reverse_iterator;
678 reverse_iterator rbegin() { return Index2Node.rbegin(); }
679 const_reverse_iterator rbegin() const { return Index2Node.rbegin(); }
680 reverse_iterator rend() { return Index2Node.rend(); }
681 const_reverse_iterator rend() const { return Index2Node.rend(); }