1 //===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ScheduleDAG class, which is used as the common
11 // base class for instruction schedulers. This encapsulates the scheduling DAG,
12 // which is shared between SelectionDAG and MachineInstr scheduling.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_SCHEDULEDAG_H
17 #define LLVM_CODEGEN_SCHEDULEDAG_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/ADT/DenseMap.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/GraphTraits.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/ADT/PointerIntPair.h"
30 class MachineConstantPool;
31 class MachineFunction;
32 class MachineRegisterInfo;
34 class TargetRegisterInfo;
37 class TargetInstrInfo;
40 class TargetRegisterClass;
41 template<class Graph> class GraphWriter;
43 /// SDep - Scheduling dependency. This represents one direction of an
44 /// edge in the scheduling DAG.
47 /// Kind - These are the different kinds of scheduling dependencies.
49 Data, ///< Regular data dependence (aka true-dependence).
50 Anti, ///< A register anti-dependedence (aka WAR).
51 Output, ///< A register output-dependence (aka WAW).
52 Order ///< Any other ordering dependency.
56 /// Dep - A pointer to the depending/depended-on SUnit, and an enum
57 /// indicating the kind of the dependency.
58 PointerIntPair<SUnit *, 2, Kind> Dep;
60 /// Contents - A union discriminated by the dependence kind.
62 /// Reg - For Data, Anti, and Output dependencies, the associated
63 /// register. For Data dependencies that don't currently have a register
64 /// assigned, this is set to zero.
67 /// Order - Additional information about Order dependencies.
69 /// isNormalMemory - True if both sides of the dependence
70 /// access memory in non-volatile and fully modeled ways.
71 bool isNormalMemory : 1;
73 /// isMustAlias - True if both sides of the dependence are known to
74 /// access the same memory.
77 /// isArtificial - True if this is an artificial dependency, meaning
78 /// it is not necessary for program correctness, and may be safely
79 /// deleted if necessary.
80 bool isArtificial : 1;
84 /// Latency - The time associated with this edge. Often this is just
85 /// the value of the Latency field of the predecessor, however advanced
86 /// models may provide additional information about specific edges.
90 /// SDep - Construct a null SDep. This is only for use by container
91 /// classes which require default constructors. SUnits may not
92 /// have null SDep edges.
93 SDep() : Dep(0, Data) {}
95 /// SDep - Construct an SDep with the specified values.
96 SDep(SUnit *S, Kind kind, unsigned latency = 1, unsigned Reg = 0,
97 bool isNormalMemory = false, bool isMustAlias = false,
98 bool isArtificial = false)
99 : Dep(S, kind), Contents(), Latency(latency) {
104 "SDep::Anti and SDep::Output must use a non-zero Reg!");
107 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!");
108 assert(!isArtificial && "isArtificial only applies with SDep::Order!");
112 assert(Reg == 0 && "Reg given for non-register dependence!");
113 Contents.Order.isNormalMemory = isNormalMemory;
114 Contents.Order.isMustAlias = isMustAlias;
115 Contents.Order.isArtificial = isArtificial;
120 bool operator==(const SDep &Other) const {
121 if (Dep != Other.Dep || Latency != Other.Latency) return false;
122 switch (Dep.getInt()) {
126 return Contents.Reg == Other.Contents.Reg;
128 return Contents.Order.isNormalMemory ==
129 Other.Contents.Order.isNormalMemory &&
130 Contents.Order.isMustAlias == Other.Contents.Order.isMustAlias &&
131 Contents.Order.isArtificial == Other.Contents.Order.isArtificial;
133 llvm_unreachable("Invalid dependency kind!");
136 bool operator!=(const SDep &Other) const {
137 return !operator==(Other);
140 /// getLatency - Return the latency value for this edge, which roughly
141 /// means the minimum number of cycles that must elapse between the
142 /// predecessor and the successor, given that they have this edge
144 unsigned getLatency() const {
148 /// setLatency - Set the latency for this edge.
149 void setLatency(unsigned Lat) {
153 //// getSUnit - Return the SUnit to which this edge points.
154 SUnit *getSUnit() const {
155 return Dep.getPointer();
158 //// setSUnit - Assign the SUnit to which this edge points.
159 void setSUnit(SUnit *SU) {
163 /// getKind - Return an enum value representing the kind of the dependence.
164 Kind getKind() const {
168 /// isCtrl - Shorthand for getKind() != SDep::Data.
169 bool isCtrl() const {
170 return getKind() != Data;
173 /// isNormalMemory - Test if this is an Order dependence between two
174 /// memory accesses where both sides of the dependence access memory
175 /// in non-volatile and fully modeled ways.
176 bool isNormalMemory() const {
177 return getKind() == Order && Contents.Order.isNormalMemory;
180 /// isMustAlias - Test if this is an Order dependence that is marked
181 /// as "must alias", meaning that the SUnits at either end of the edge
182 /// have a memory dependence on a known memory location.
183 bool isMustAlias() const {
184 return getKind() == Order && Contents.Order.isMustAlias;
187 /// isArtificial - Test if this is an Order dependence that is marked
188 /// as "artificial", meaning it isn't necessary for correctness.
189 bool isArtificial() const {
190 return getKind() == Order && Contents.Order.isArtificial;
193 /// isAssignedRegDep - Test if this is a Data dependence that is
194 /// associated with a register.
195 bool isAssignedRegDep() const {
196 return getKind() == Data && Contents.Reg != 0;
199 /// getReg - Return the register associated with this edge. This is
200 /// only valid on Data, Anti, and Output edges. On Data edges, this
201 /// value may be zero, meaning there is no associated register.
202 unsigned getReg() const {
203 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
204 "getReg called on non-register dependence edge!");
208 /// setReg - Assign the associated register for this edge. This is
209 /// only valid on Data, Anti, and Output edges. On Anti and Output
210 /// edges, this value must not be zero. On Data edges, the value may
211 /// be zero, which would mean that no specific register is associated
213 void setReg(unsigned Reg) {
214 assert((getKind() == Data || getKind() == Anti || getKind() == Output) &&
215 "setReg called on non-register dependence edge!");
216 assert((getKind() != Anti || Reg != 0) &&
217 "SDep::Anti edge cannot use the zero register!");
218 assert((getKind() != Output || Reg != 0) &&
219 "SDep::Output edge cannot use the zero register!");
225 struct isPodLike<SDep> { static const bool value = true; };
227 /// SUnit - Scheduling unit. This is a node in the scheduling DAG.
230 SDNode *Node; // Representative node.
231 MachineInstr *Instr; // Alternatively, a MachineInstr.
233 SUnit *OrigNode; // If not this, the node from which
234 // this node was cloned.
235 // (SD scheduling only)
237 // Preds/Succs - The SUnits before/after us in the graph.
238 SmallVector<SDep, 4> Preds; // All sunit predecessors.
239 SmallVector<SDep, 4> Succs; // All sunit successors.
241 typedef SmallVector<SDep, 4>::iterator pred_iterator;
242 typedef SmallVector<SDep, 4>::iterator succ_iterator;
243 typedef SmallVector<SDep, 4>::const_iterator const_pred_iterator;
244 typedef SmallVector<SDep, 4>::const_iterator const_succ_iterator;
246 unsigned NodeNum; // Entry # of node in the node vector.
247 unsigned NodeQueueId; // Queue id of node.
248 unsigned NumPreds; // # of SDep::Data preds.
249 unsigned NumSuccs; // # of SDep::Data sucss.
250 unsigned NumPredsLeft; // # of preds not scheduled.
251 unsigned NumSuccsLeft; // # of succs not scheduled.
252 unsigned short NumRegDefsLeft; // # of reg defs with no scheduled use.
253 unsigned short Latency; // Node latency.
254 bool isVRegCycle : 1; // May use and def the same vreg.
255 bool isCall : 1; // Is a function call.
256 bool isCallOp : 1; // Is a function call operand.
257 bool isTwoAddress : 1; // Is a two-address instruction.
258 bool isCommutable : 1; // Is a commutable instruction.
259 bool hasPhysRegDefs : 1; // Has physreg defs that are being used.
260 bool hasPhysRegClobbers : 1; // Has any physreg defs, used or not.
261 bool isPending : 1; // True once pending.
262 bool isAvailable : 1; // True once available.
263 bool isScheduled : 1; // True once scheduled.
264 bool isScheduleHigh : 1; // True if preferable to schedule high.
265 bool isScheduleLow : 1; // True if preferable to schedule low.
266 bool isCloned : 1; // True if this node has been cloned.
267 Sched::Preference SchedulingPref; // Scheduling preference.
270 bool isDepthCurrent : 1; // True if Depth is current.
271 bool isHeightCurrent : 1; // True if Height is current.
272 unsigned Depth; // Node depth.
273 unsigned Height; // Node height.
275 unsigned TopReadyCycle; // Cycle relative to start when node is ready.
276 unsigned BotReadyCycle; // Cycle relative to end when node is ready.
278 const TargetRegisterClass *CopyDstRC; // Is a special copy node if not null.
279 const TargetRegisterClass *CopySrcRC;
281 /// SUnit - Construct an SUnit for pre-regalloc scheduling to represent
282 /// an SDNode and any nodes flagged to it.
283 SUnit(SDNode *node, unsigned nodenum)
284 : Node(node), Instr(0), OrigNode(0), NodeNum(nodenum),
285 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
286 NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0),
287 isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(false),
288 isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
289 isPending(false), isAvailable(false), isScheduled(false),
290 isScheduleHigh(false), isScheduleLow(false), isCloned(false),
291 SchedulingPref(Sched::None),
292 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
293 TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
295 /// SUnit - Construct an SUnit for post-regalloc scheduling to represent
297 SUnit(MachineInstr *instr, unsigned nodenum)
298 : Node(0), Instr(instr), OrigNode(0), NodeNum(nodenum),
299 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
300 NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0),
301 isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(false),
302 isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
303 isPending(false), isAvailable(false), isScheduled(false),
304 isScheduleHigh(false), isScheduleLow(false), isCloned(false),
305 SchedulingPref(Sched::None),
306 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
307 TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
309 /// SUnit - Construct a placeholder SUnit.
311 : Node(0), Instr(0), OrigNode(0), NodeNum(~0u),
312 NodeQueueId(0), NumPreds(0), NumSuccs(0), NumPredsLeft(0),
313 NumSuccsLeft(0), NumRegDefsLeft(0), Latency(0),
314 isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(false),
315 isCommutable(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
316 isPending(false), isAvailable(false), isScheduled(false),
317 isScheduleHigh(false), isScheduleLow(false), isCloned(false),
318 SchedulingPref(Sched::None),
319 isDepthCurrent(false), isHeightCurrent(false), Depth(0), Height(0),
320 TopReadyCycle(0), BotReadyCycle(0), CopyDstRC(NULL), CopySrcRC(NULL) {}
322 /// setNode - Assign the representative SDNode for this SUnit.
323 /// This may be used during pre-regalloc scheduling.
324 void setNode(SDNode *N) {
325 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
329 /// getNode - Return the representative SDNode for this SUnit.
330 /// This may be used during pre-regalloc scheduling.
331 SDNode *getNode() const {
332 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
336 /// isInstr - Return true if this SUnit refers to a machine instruction as
337 /// opposed to an SDNode.
338 bool isInstr() const { return Instr; }
340 /// setInstr - Assign the instruction for the SUnit.
341 /// This may be used during post-regalloc scheduling.
342 void setInstr(MachineInstr *MI) {
343 assert(!Node && "Setting MachineInstr of SUnit with SDNode!");
347 /// getInstr - Return the representative MachineInstr for this SUnit.
348 /// This may be used during post-regalloc scheduling.
349 MachineInstr *getInstr() const {
350 assert(!Node && "Reading MachineInstr of SUnit with SDNode!");
354 /// addPred - This adds the specified edge as a pred of the current node if
355 /// not already. It also adds the current node as a successor of the
357 bool addPred(const SDep &D);
359 /// removePred - This removes the specified edge as a pred of the current
360 /// node if it exists. It also removes the current node as a successor of
361 /// the specified node.
362 void removePred(const SDep &D);
364 /// getDepth - Return the depth of this node, which is the length of the
365 /// maximum path up to any node which has no predecessors.
366 unsigned getDepth() const {
368 const_cast<SUnit *>(this)->ComputeDepth();
372 /// getHeight - Return the height of this node, which is the length of the
373 /// maximum path down to any node which has no successors.
374 unsigned getHeight() const {
375 if (!isHeightCurrent)
376 const_cast<SUnit *>(this)->ComputeHeight();
380 /// setDepthToAtLeast - If NewDepth is greater than this node's
381 /// depth value, set it to be the new depth value. This also
382 /// recursively marks successor nodes dirty.
383 void setDepthToAtLeast(unsigned NewDepth);
385 /// setDepthToAtLeast - If NewDepth is greater than this node's
386 /// depth value, set it to be the new height value. This also
387 /// recursively marks predecessor nodes dirty.
388 void setHeightToAtLeast(unsigned NewHeight);
390 /// setDepthDirty - Set a flag in this node to indicate that its
391 /// stored Depth value will require recomputation the next time
392 /// getDepth() is called.
393 void setDepthDirty();
395 /// setHeightDirty - Set a flag in this node to indicate that its
396 /// stored Height value will require recomputation the next time
397 /// getHeight() is called.
398 void setHeightDirty();
400 /// isPred - Test if node N is a predecessor of this node.
401 bool isPred(SUnit *N) {
402 for (unsigned i = 0, e = (unsigned)Preds.size(); i != e; ++i)
403 if (Preds[i].getSUnit() == N)
408 /// isSucc - Test if node N is a successor of this node.
409 bool isSucc(SUnit *N) {
410 for (unsigned i = 0, e = (unsigned)Succs.size(); i != e; ++i)
411 if (Succs[i].getSUnit() == N)
416 bool isTopReady() const {
417 return NumPredsLeft == 0;
419 bool isBottomReady() const {
420 return NumSuccsLeft == 0;
423 void dump(const ScheduleDAG *G) const;
424 void dumpAll(const ScheduleDAG *G) const;
425 void print(raw_ostream &O, const ScheduleDAG *G) const;
429 void ComputeHeight();
432 //===--------------------------------------------------------------------===//
433 /// SchedulingPriorityQueue - This interface is used to plug different
434 /// priorities computation algorithms into the list scheduler. It implements
435 /// the interface of a standard priority queue, where nodes are inserted in
436 /// arbitrary order and returned in priority order. The computation of the
437 /// priority and the representation of the queue are totally up to the
438 /// implementation to decide.
440 class SchedulingPriorityQueue {
441 virtual void anchor();
445 SchedulingPriorityQueue(bool rf = false):
446 CurCycle(0), HasReadyFilter(rf) {}
447 virtual ~SchedulingPriorityQueue() {}
449 virtual bool isBottomUp() const = 0;
451 virtual void initNodes(std::vector<SUnit> &SUnits) = 0;
452 virtual void addNode(const SUnit *SU) = 0;
453 virtual void updateNode(const SUnit *SU) = 0;
454 virtual void releaseState() = 0;
456 virtual bool empty() const = 0;
458 bool hasReadyFilter() const { return HasReadyFilter; }
460 virtual bool tracksRegPressure() const { return false; }
462 virtual bool isReady(SUnit *) const {
463 assert(!HasReadyFilter && "The ready filter must override isReady()");
466 virtual void push(SUnit *U) = 0;
468 void push_all(const std::vector<SUnit *> &Nodes) {
469 for (std::vector<SUnit *>::const_iterator I = Nodes.begin(),
470 E = Nodes.end(); I != E; ++I)
474 virtual SUnit *pop() = 0;
476 virtual void remove(SUnit *SU) = 0;
478 virtual void dump(ScheduleDAG *) const {}
480 /// scheduledNode - As each node is scheduled, this method is invoked. This
481 /// allows the priority function to adjust the priority of related
482 /// unscheduled nodes, for example.
484 virtual void scheduledNode(SUnit *) {}
486 virtual void unscheduledNode(SUnit *) {}
488 void setCurCycle(unsigned Cycle) {
492 unsigned getCurCycle() const {
499 const TargetMachine &TM; // Target processor
500 const TargetInstrInfo *TII; // Target instruction information
501 const TargetRegisterInfo *TRI; // Target processor register info
502 MachineFunction &MF; // Machine function
503 MachineRegisterInfo &MRI; // Virtual/real register map
504 std::vector<SUnit> SUnits; // The scheduling units.
505 SUnit EntrySU; // Special node for the region entry.
506 SUnit ExitSU; // Special node for the region exit.
509 static const bool StressSched = false;
514 explicit ScheduleDAG(MachineFunction &mf);
516 virtual ~ScheduleDAG();
518 /// clearDAG - clear the DAG state (between regions).
521 /// getInstrDesc - Return the MCInstrDesc of this SUnit.
522 /// Return NULL for SDNodes without a machine opcode.
523 const MCInstrDesc *getInstrDesc(const SUnit *SU) const {
524 if (SU->isInstr()) return &SU->getInstr()->getDesc();
525 return getNodeDesc(SU->getNode());
528 /// viewGraph - Pop up a GraphViz/gv window with the ScheduleDAG rendered
531 void viewGraph(const Twine &Name, const Twine &Title);
534 virtual void dumpNode(const SUnit *SU) const = 0;
536 /// getGraphNodeLabel - Return a label for an SUnit node in a visualization
537 /// of the ScheduleDAG.
538 virtual std::string getGraphNodeLabel(const SUnit *SU) const = 0;
540 /// getDAGLabel - Return a label for the region of code covered by the DAG.
541 virtual std::string getDAGName() const = 0;
543 /// addCustomGraphFeatures - Add custom features for a visualization of
545 virtual void addCustomGraphFeatures(GraphWriter<ScheduleDAG*> &) const {}
548 /// VerifyScheduledDAG - Verify that all SUnits were scheduled and that
549 /// their state is consistent. Return the number of scheduled SUnits.
550 unsigned VerifyScheduledDAG(bool isBottomUp);
554 /// ComputeLatency - Compute node latency.
556 virtual void computeLatency(SUnit *SU) = 0;
558 /// ForceUnitLatencies - Return true if all scheduling edges should be given
559 /// a latency value of one. The default is to return false; schedulers may
560 /// override this as needed.
561 virtual bool forceUnitLatencies() const { return false; }
564 // Return the MCInstrDesc of this SDNode or NULL.
565 const MCInstrDesc *getNodeDesc(const SDNode *Node) const;
568 class SUnitIterator : public std::iterator<std::forward_iterator_tag,
573 SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
575 bool operator==(const SUnitIterator& x) const {
576 return Operand == x.Operand;
578 bool operator!=(const SUnitIterator& x) const { return !operator==(x); }
580 const SUnitIterator &operator=(const SUnitIterator &I) {
581 assert(I.Node==Node && "Cannot assign iterators to two different nodes!");
586 pointer operator*() const {
587 return Node->Preds[Operand].getSUnit();
589 pointer operator->() const { return operator*(); }
591 SUnitIterator& operator++() { // Preincrement
595 SUnitIterator operator++(int) { // Postincrement
596 SUnitIterator tmp = *this; ++*this; return tmp;
599 static SUnitIterator begin(SUnit *N) { return SUnitIterator(N, 0); }
600 static SUnitIterator end (SUnit *N) {
601 return SUnitIterator(N, (unsigned)N->Preds.size());
604 unsigned getOperand() const { return Operand; }
605 const SUnit *getNode() const { return Node; }
606 /// isCtrlDep - Test if this is not an SDep::Data dependence.
607 bool isCtrlDep() const {
608 return getSDep().isCtrl();
610 bool isArtificialDep() const {
611 return getSDep().isArtificial();
613 const SDep &getSDep() const {
614 return Node->Preds[Operand];
618 template <> struct GraphTraits<SUnit*> {
619 typedef SUnit NodeType;
620 typedef SUnitIterator ChildIteratorType;
621 static inline NodeType *getEntryNode(SUnit *N) { return N; }
622 static inline ChildIteratorType child_begin(NodeType *N) {
623 return SUnitIterator::begin(N);
625 static inline ChildIteratorType child_end(NodeType *N) {
626 return SUnitIterator::end(N);
630 template <> struct GraphTraits<ScheduleDAG*> : public GraphTraits<SUnit*> {
631 typedef std::vector<SUnit>::iterator nodes_iterator;
632 static nodes_iterator nodes_begin(ScheduleDAG *G) {
633 return G->SUnits.begin();
635 static nodes_iterator nodes_end(ScheduleDAG *G) {
636 return G->SUnits.end();
640 /// ScheduleDAGTopologicalSort is a class that computes a topological
641 /// ordering for SUnits and provides methods for dynamically updating
642 /// the ordering as new edges are added.
644 /// This allows a very fast implementation of IsReachable, for example.
646 class ScheduleDAGTopologicalSort {
647 /// SUnits - A reference to the ScheduleDAG's SUnits.
648 std::vector<SUnit> &SUnits;
650 /// Index2Node - Maps topological index to the node number.
651 std::vector<int> Index2Node;
652 /// Node2Index - Maps the node number to its topological index.
653 std::vector<int> Node2Index;
654 /// Visited - a set of nodes visited during a DFS traversal.
657 /// DFS - make a DFS traversal and mark all nodes affected by the
658 /// edge insertion. These nodes will later get new topological indexes
659 /// by means of the Shift method.
660 void DFS(const SUnit *SU, int UpperBound, bool& HasLoop);
662 /// Shift - reassign topological indexes for the nodes in the DAG
663 /// to preserve the topological ordering.
664 void Shift(BitVector& Visited, int LowerBound, int UpperBound);
666 /// Allocate - assign the topological index to the node n.
667 void Allocate(int n, int index);
670 explicit ScheduleDAGTopologicalSort(std::vector<SUnit> &SUnits);
672 /// InitDAGTopologicalSorting - create the initial topological
673 /// ordering from the DAG to be scheduled.
674 void InitDAGTopologicalSorting();
676 /// IsReachable - Checks if SU is reachable from TargetSU.
677 bool IsReachable(const SUnit *SU, const SUnit *TargetSU);
679 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU
680 /// will create a cycle.
681 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU);
683 /// AddPred - Updates the topological ordering to accommodate an edge
684 /// to be added from SUnit X to SUnit Y.
685 void AddPred(SUnit *Y, SUnit *X);
687 /// RemovePred - Updates the topological ordering to accommodate an
688 /// an edge to be removed from the specified node N from the predecessors
689 /// of the current node M.
690 void RemovePred(SUnit *M, SUnit *N);
692 typedef std::vector<int>::iterator iterator;
693 typedef std::vector<int>::const_iterator const_iterator;
694 iterator begin() { return Index2Node.begin(); }
695 const_iterator begin() const { return Index2Node.begin(); }
696 iterator end() { return Index2Node.end(); }
697 const_iterator end() const { return Index2Node.end(); }
699 typedef std::vector<int>::reverse_iterator reverse_iterator;
700 typedef std::vector<int>::const_reverse_iterator const_reverse_iterator;
701 reverse_iterator rbegin() { return Index2Node.rbegin(); }
702 const_reverse_iterator rbegin() const { return Index2Node.rbegin(); }
703 reverse_iterator rend() { return Index2Node.rend(); }
704 const_reverse_iterator rend() const { return Index2Node.rend(); }