1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
25 class MachineFunctionPass;
28 class ScheduleDAGInstrs;
30 class TargetLoweringBase;
31 class TargetRegisterClass;
33 struct MachineSchedContext;
35 // The old pass manager infrastructure is hidden in a legacy namespace now.
37 class PassManagerBase;
39 using legacy::PassManagerBase;
41 /// Discriminated union of Pass ID types.
43 /// The PassConfig API prefers dealing with IDs because they are safer and more
44 /// efficient. IDs decouple configuration from instantiation. This way, when a
45 /// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
46 /// refer to a Pass pointer after adding it to a pass manager, which deletes
47 /// redundant pass instances.
49 /// However, it is convient to directly instantiate target passes with
50 /// non-default ctors. These often don't have a registered PassInfo. Rather than
51 /// force all target passes to implement the pass registry boilerplate, allow
52 /// the PassConfig API to handle either type.
54 /// AnalysisID is sadly char*, so PointerIntPair won't work.
55 class IdentifyingPassPtr {
62 IdentifyingPassPtr() : P(nullptr), IsInstance(false) {}
63 IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr), IsInstance(false) {}
64 IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
66 bool isValid() const { return P; }
67 bool isInstance() const { return IsInstance; }
69 AnalysisID getID() const {
70 assert(!IsInstance && "Not a Pass ID");
73 Pass *getInstance() const {
74 assert(IsInstance && "Not a Pass Instance");
79 template <> struct isPodLike<IdentifyingPassPtr> {
80 static const bool value = true;
83 /// Target-Independent Code Generator Pass Configuration Options.
85 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
86 /// to the internals of other CodeGen passes.
87 class TargetPassConfig : public ImmutablePass {
89 /// Pseudo Pass IDs. These are defined within TargetPassConfig because they
90 /// are unregistered pass IDs. They are only useful for use with
91 /// TargetPassConfig APIs to identify multiple occurrences of the same pass.
94 /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early
95 /// during codegen, on SSA form.
96 static char EarlyTailDuplicateID;
98 /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine
99 /// optimization after regalloc.
100 static char PostRAMachineLICMID;
104 AnalysisID StartBefore, StartAfter;
105 AnalysisID StopAfter;
108 bool AddingMachinePasses;
112 PassConfigImpl *Impl; // Internal data structures
113 bool Initialized; // Flagged after all passes are configured.
115 // Target Pass Options
116 // Targets provide a default setting, user flags override.
120 /// Default setting for -enable-tail-merge on this target.
121 bool EnableTailMerge;
124 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
125 // Dummy constructor.
128 ~TargetPassConfig() override;
132 /// Get the right type of TargetMachine for this target.
133 template<typename TMC> TMC &getTM() const {
134 return *static_cast<TMC*>(TM);
138 void setInitialized() { Initialized = true; }
140 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
142 /// Set the StartAfter, StartBefore and StopAfter passes to allow running only
143 /// a portion of the normal code-gen pass sequence.
145 /// If the StartAfter and StartBefore pass ID is zero, then compilation will
146 /// begin at the normal point; otherwise, clear the Started flag to indicate
147 /// that passes should not be added until the starting pass is seen. If the
148 /// Stop pass ID is zero, then compilation will continue to the end.
150 /// This function expects that at least one of the StartAfter or the
151 /// StartBefore pass IDs is null.
152 void setStartStopPasses(AnalysisID StartBefore, AnalysisID StartAfter,
153 AnalysisID StopAfter) {
155 assert(!StartBefore && "Start after and start before passes are given");
156 this->StartBefore = StartBefore;
157 this->StartAfter = StartAfter;
158 this->StopAfter = StopAfter;
159 Started = (StartAfter == nullptr) && (StartBefore == nullptr);
162 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
164 bool getEnableTailMerge() const { return EnableTailMerge; }
165 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
167 /// Allow the target to override a specific pass without overriding the pass
168 /// pipeline. When passes are added to the standard pipeline at the
169 /// point where StandardID is expected, add TargetID in its place.
170 void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
172 /// Insert InsertedPassID pass after TargetPassID pass.
173 void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID);
175 /// Allow the target to enable a specific standard pass by default.
176 void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
178 /// Allow the target to disable a specific standard pass by default.
179 void disablePass(AnalysisID PassID) {
180 substitutePass(PassID, IdentifyingPassPtr());
183 /// Return the pass substituted for StandardID by the target.
184 /// If no substitution exists, return StandardID.
185 IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const;
187 /// Return true if the optimized regalloc pipeline is enabled.
188 bool getOptimizeRegAlloc() const;
190 /// Return true if the default global register allocator is in use and
191 /// has not be overriden on the command line with '-regalloc=...'
192 bool usingDefaultRegAlloc() const;
194 /// Add common target configurable passes that perform LLVM IR to IR
195 /// transforms following machine independent optimization.
196 virtual void addIRPasses();
198 /// Add passes to lower exception handling for the code generator.
199 void addPassesToHandleExceptions();
201 /// Add pass to prepare the LLVM IR for code generation. This should be done
202 /// before exception handling preparation passes.
203 virtual void addCodeGenPrepare();
205 /// Add common passes that perform LLVM IR to IR transforms in preparation for
206 /// instruction selection.
207 virtual void addISelPrepare();
209 /// addInstSelector - This method should install an instruction selector pass,
210 /// which converts from LLVM code to machine instructions.
211 virtual bool addInstSelector() {
215 /// Add the complete, standard set of LLVM CodeGen passes.
216 /// Fully developed targets will not generally override this.
217 virtual void addMachinePasses();
219 /// Create an instance of ScheduleDAGInstrs to be run within the standard
220 /// MachineScheduler pass for this function and target at the current
221 /// optimization level.
223 /// This can also be used to plug a new MachineSchedStrategy into an instance
224 /// of the standard ScheduleDAGMI:
225 /// return new ScheduleDAGMI(C, make_unique<MyStrategy>(C), /* IsPostRA= */false)
227 /// Return NULL to select the default (generic) machine scheduler.
228 virtual ScheduleDAGInstrs *
229 createMachineScheduler(MachineSchedContext *C) const {
233 /// Similar to createMachineScheduler but used when postRA machine scheduling
235 virtual ScheduleDAGInstrs *
236 createPostMachineScheduler(MachineSchedContext *C) const {
241 // Helper to verify the analysis is really immutable.
242 void setOpt(bool &Opt, bool Val);
244 /// Methods with trivial inline returns are convenient points in the common
245 /// codegen pass pipeline where targets may insert passes. Methods with
246 /// out-of-line standard implementations are major CodeGen stages called by
247 /// addMachinePasses. Some targets may override major stages when inserting
248 /// passes is insufficient, but maintaining overriden stages is more work.
251 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
252 /// passes (which are run just before instruction selector).
253 virtual bool addPreISel() {
257 /// addMachineSSAOptimization - Add standard passes that optimize machine
258 /// instructions in SSA form.
259 virtual void addMachineSSAOptimization();
261 /// Add passes that optimize instruction level parallelism for out-of-order
262 /// targets. These passes are run while the machine code is still in SSA
263 /// form, so they can use MachineTraceMetrics to control their heuristics.
265 /// All passes added here should preserve the MachineDominatorTree,
266 /// MachineLoopInfo, and MachineTraceMetrics analyses.
267 virtual bool addILPOpts() {
271 /// This method may be implemented by targets that want to run passes
272 /// immediately before register allocation.
273 virtual void addPreRegAlloc() { }
275 /// createTargetRegisterAllocator - Create the register allocator pass for
276 /// this target at the current optimization level.
277 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
279 /// addFastRegAlloc - Add the minimum set of target-independent passes that
280 /// are required for fast register allocation.
281 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
283 /// addOptimizedRegAlloc - Add passes related to register allocation.
284 /// LLVMTargetMachine provides standard regalloc passes for most targets.
285 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
287 /// addPreRewrite - Add passes to the optimized register allocation pipeline
288 /// after register allocation is complete, but before virtual registers are
289 /// rewritten to physical registers.
291 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
292 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
293 /// When these passes run, VirtRegMap contains legal physreg assignments for
294 /// all virtual registers.
295 virtual bool addPreRewrite() {
299 /// This method may be implemented by targets that want to run passes after
300 /// register allocation pass pipeline but before prolog-epilog insertion.
301 virtual void addPostRegAlloc() { }
303 /// Add passes that optimize machine instructions after register allocation.
304 virtual void addMachineLateOptimization();
306 /// This method may be implemented by targets that want to run passes after
307 /// prolog-epilog insertion and before the second instruction scheduling pass.
308 virtual void addPreSched2() { }
310 /// addGCPasses - Add late codegen passes that analyze code for garbage
311 /// collection. This should return true if GC info should be printed after
313 virtual bool addGCPasses();
315 /// Add standard basic block placement passes.
316 virtual void addBlockPlacement();
318 /// This pass may be implemented by targets that want to run passes
319 /// immediately before machine code is emitted.
320 virtual void addPreEmitPass() { }
322 /// Utilities for targets to add passes to the pass manager.
325 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
326 /// Return the pass that was added, or zero if no pass was added.
327 /// @p printAfter if true and adding a machine function pass add an extra
328 /// machine printer pass afterwards
329 /// @p verifyAfter if true and adding a machine function pass add an extra
330 /// machine verification pass afterwards.
331 AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
332 bool printAfter = true);
334 /// Add a pass to the PassManager if that pass is supposed to be run, as
335 /// determined by the StartAfter and StopAfter options. Takes ownership of the
337 /// @p printAfter if true and adding a machine function pass add an extra
338 /// machine printer pass afterwards
339 /// @p verifyAfter if true and adding a machine function pass add an extra
340 /// machine verification pass afterwards.
341 void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
343 /// addMachinePasses helper to create the target-selected or overriden
345 FunctionPass *createRegAllocPass(bool Optimized);
347 /// printAndVerify - Add a pass to dump then verify the machine function, if
348 /// those steps are enabled.
350 void printAndVerify(const std::string &Banner);
352 /// Add a pass to print the machine function if printing is enabled.
353 void addPrintPass(const std::string &Banner);
355 /// Add a pass to perform basic verification of the machine function if
356 /// verification is enabled.
357 void addVerifyPass(const std::string &Banner);
359 /// Create an instance of ShrinkWrap using the runShrinkWrap predicate
361 FunctionPass *createShrinkWrapPass();
363 /// Predicate function passed to a ShrinkWrap object to determine if shrink
364 /// wrapping should be run on a MachineFunction.
365 virtual bool runShrinkWrap(const MachineFunction &Fn) const;
369 /// List of target independent CodeGen pass IDs.
371 FunctionPass *createAtomicExpandPass(const TargetMachine *TM);
373 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
374 /// work well with unreachable basic blocks (what live ranges make sense for a
375 /// block that cannot be reached?). As such, a code generator should either
376 /// not instruction select unreachable blocks, or run this pass as its
377 /// last LLVM modifying pass to clean up blocks that are not reachable from
379 FunctionPass *createUnreachableBlockEliminationPass();
381 /// MachineFunctionPrinter pass - This pass prints out the machine function to
382 /// the given stream as a debugging tool.
383 MachineFunctionPass *
384 createMachineFunctionPrinterPass(raw_ostream &OS,
385 const std::string &Banner ="");
387 /// MIRPrinting pass - this pass prints out the LLVM IR into the given stream
388 /// using the MIR serialization format.
389 MachineFunctionPass *createPrintMIRPass(raw_ostream &OS);
391 /// createCodeGenPreparePass - Transform the code to expose more pattern
392 /// matching during instruction selection.
393 FunctionPass *createCodeGenPreparePass(const TargetMachine *TM = nullptr);
395 /// AtomicExpandID -- Lowers atomic operations in terms of either cmpxchg
396 /// load-linked/store-conditional loops.
397 extern char &AtomicExpandID;
399 /// MachineLoopInfo - This pass is a loop analysis pass.
400 extern char &MachineLoopInfoID;
402 /// MachineDominators - This pass is a machine dominators analysis pass.
403 extern char &MachineDominatorsID;
405 /// MachineDominanaceFrontier - This pass is a machine dominators analysis pass.
406 extern char &MachineDominanceFrontierID;
408 /// EdgeBundles analysis - Bundle machine CFG edges.
409 extern char &EdgeBundlesID;
411 /// LiveVariables pass - This pass computes the set of blocks in which each
412 /// variable is life and sets machine operand kill flags.
413 extern char &LiveVariablesID;
415 /// PHIElimination - This pass eliminates machine instruction PHI nodes
416 /// by inserting copy instructions. This destroys SSA information, but is the
417 /// desired input for some register allocators. This pass is "required" by
418 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
419 extern char &PHIEliminationID;
421 /// LiveIntervals - This analysis keeps track of the live ranges of virtual
422 /// and physical registers.
423 extern char &LiveIntervalsID;
425 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
426 extern char &LiveStacksID;
428 /// TwoAddressInstruction - This pass reduces two-address instructions to
429 /// use two operands. This destroys SSA information but it is desired by
430 /// register allocators.
431 extern char &TwoAddressInstructionPassID;
433 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
434 extern char &ProcessImplicitDefsID;
436 /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
437 extern char &RegisterCoalescerID;
439 /// MachineScheduler - This pass schedules machine instructions.
440 extern char &MachineSchedulerID;
442 /// PostMachineScheduler - This pass schedules machine instructions postRA.
443 extern char &PostMachineSchedulerID;
445 /// SpillPlacement analysis. Suggest optimal placement of spill code between
447 extern char &SpillPlacementID;
449 /// ShrinkWrap pass. Look for the best place to insert save and restore
450 // instruction and update the MachineFunctionInfo with that information.
451 extern char &ShrinkWrapID;
453 /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
454 /// assigned in VirtRegMap.
455 extern char &VirtRegRewriterID;
457 /// UnreachableMachineBlockElimination - This pass removes unreachable
458 /// machine basic blocks.
459 extern char &UnreachableMachineBlockElimID;
461 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
462 extern char &DeadMachineInstructionElimID;
464 /// FastRegisterAllocation Pass - This pass register allocates as fast as
465 /// possible. It is best suited for debug code where live ranges are short.
467 FunctionPass *createFastRegisterAllocator();
469 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
470 /// register allocator using the basic regalloc framework.
472 FunctionPass *createBasicRegisterAllocator();
474 /// Greedy register allocation pass - This pass implements a global register
475 /// allocator for optimized builds.
477 FunctionPass *createGreedyRegisterAllocator();
479 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
480 /// Quadratic Prograaming (PBQP) based register allocator.
482 FunctionPass *createDefaultPBQPRegisterAllocator();
484 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
485 /// and eliminates abstract frame references.
486 extern char &PrologEpilogCodeInserterID;
488 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
489 /// register allocation.
490 extern char &ExpandPostRAPseudosID;
492 /// createPostRAScheduler - This pass performs post register allocation
494 extern char &PostRASchedulerID;
496 /// BranchFolding - This pass performs machine code CFG based
497 /// optimizations to delete branches to branches, eliminate branches to
498 /// successor blocks (creating fall throughs), and eliminating branches over
500 extern char &BranchFolderPassID;
502 /// MachineFunctionPrinterPass - This pass prints out MachineInstr's.
503 extern char &MachineFunctionPrinterPassID;
505 /// MIRPrintingPass - this pass prints out the LLVM IR using the MIR
506 /// serialization format.
507 extern char &MIRPrintingPassID;
509 /// TailDuplicate - Duplicate blocks with unconditional branches
510 /// into tails of their predecessors.
511 extern char &TailDuplicateID;
513 /// MachineTraceMetrics - This pass computes critical path and CPU resource
514 /// usage in an ensemble of traces.
515 extern char &MachineTraceMetricsID;
517 /// EarlyIfConverter - This pass performs if-conversion on SSA form by
518 /// inserting cmov instructions.
519 extern char &EarlyIfConverterID;
521 /// This pass performs instruction combining using trace metrics to estimate
522 /// critical-path and resource depth.
523 extern char &MachineCombinerID;
525 /// StackSlotColoring - This pass performs stack coloring and merging.
526 /// It merges disjoint allocas to reduce the stack size.
527 extern char &StackColoringID;
529 /// IfConverter - This pass performs machine code if conversion.
530 extern char &IfConverterID;
532 FunctionPass *createIfConverter(std::function<bool(const Function &)> Ftor);
534 /// MachineBlockPlacement - This pass places basic blocks based on branch
536 extern char &MachineBlockPlacementID;
538 /// MachineBlockPlacementStats - This pass collects statistics about the
539 /// basic block placement using branch probabilities and block frequency
541 extern char &MachineBlockPlacementStatsID;
543 /// GCLowering Pass - Used by gc.root to perform its default lowering
545 FunctionPass *createGCLoweringPass();
547 /// ShadowStackGCLowering - Implements the custom lowering mechanism
548 /// used by the shadow stack GC. Only runs on functions which opt in to
549 /// the shadow stack collector.
550 FunctionPass *createShadowStackGCLoweringPass();
552 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
553 /// in machine code. Must be added very late during code generation, just
554 /// prior to output, and importantly after all CFG transformations (such as
556 extern char &GCMachineCodeAnalysisID;
558 /// Creates a pass to print GC metadata.
560 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
562 /// MachineCSE - This pass performs global CSE on machine instructions.
563 extern char &MachineCSEID;
565 /// ImplicitNullChecks - This pass folds null pointer checks into nearby
566 /// memory operations.
567 extern char &ImplicitNullChecksID;
569 /// MachineLICM - This pass performs LICM on machine instructions.
570 extern char &MachineLICMID;
572 /// MachineSinking - This pass performs sinking on machine instructions.
573 extern char &MachineSinkingID;
575 /// MachineCopyPropagation - This pass performs copy propagation on
576 /// machine instructions.
577 extern char &MachineCopyPropagationID;
579 /// PeepholeOptimizer - This pass performs peephole optimizations -
580 /// like extension and comparison eliminations.
581 extern char &PeepholeOptimizerID;
583 /// OptimizePHIs - This pass optimizes machine instruction PHIs
584 /// to take advantage of opportunities created during DAG legalization.
585 extern char &OptimizePHIsID;
587 /// StackSlotColoring - This pass performs stack slot coloring.
588 extern char &StackSlotColoringID;
590 /// createStackProtectorPass - This pass adds stack protectors to functions.
592 FunctionPass *createStackProtectorPass(const TargetMachine *TM);
594 /// createMachineVerifierPass - This pass verifies cenerated machine code
595 /// instructions for correctness.
597 FunctionPass *createMachineVerifierPass(const std::string& Banner);
599 /// createDwarfEHPass - This pass mulches exception handling code into a form
600 /// adapted to code generation. Required if using dwarf exception handling.
601 FunctionPass *createDwarfEHPass(const TargetMachine *TM);
603 /// createWinEHPass - Prepares personality functions used by MSVC on Windows,
604 /// in addition to the Itanium LSDA based personalities.
605 FunctionPass *createWinEHPass(const TargetMachine *TM);
607 /// createSjLjEHPreparePass - This pass adapts exception handling code to use
608 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
610 FunctionPass *createSjLjEHPreparePass();
612 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
613 /// slots relative to one another and allocates base registers to access them
614 /// when it is estimated by the target to be out of range of normal frame
615 /// pointer or stack pointer index addressing.
616 extern char &LocalStackSlotAllocationID;
618 /// ExpandISelPseudos - This pass expands pseudo-instructions.
619 extern char &ExpandISelPseudosID;
621 /// createExecutionDependencyFixPass - This pass fixes execution time
622 /// problems with dependent instructions, such as switching execution
623 /// domains to match.
625 /// The pass will examine instructions using and defining registers in RC.
627 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
629 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
630 extern char &UnpackMachineBundlesID;
633 createUnpackMachineBundles(std::function<bool(const Function &)> Ftor);
635 /// FinalizeMachineBundles - This pass finalize machine instruction
636 /// bundles (created earlier, e.g. during pre-RA scheduling).
637 extern char &FinalizeMachineBundlesID;
639 /// StackMapLiveness - This pass analyses the register live-out set of
640 /// stackmap/patchpoint intrinsics and attaches the calculated information to
641 /// the intrinsic for later emission to the StackMap.
642 extern char &StackMapLivenessID;
644 /// createJumpInstrTables - This pass creates jump-instruction tables.
645 ModulePass *createJumpInstrTablesPass();
647 /// createForwardControlFlowIntegrityPass - This pass adds control-flow
649 ModulePass *createForwardControlFlowIntegrityPass();
651 /// InterleavedAccess Pass - This pass identifies and matches interleaved
652 /// memory accesses to target specific intrinsics.
654 FunctionPass *createInterleavedAccessPass(const TargetMachine *TM);
655 } // End llvm namespace
657 /// Target machine pass initializer for passes with dependencies. Use with
658 /// INITIALIZE_TM_PASS_END.
659 #define INITIALIZE_TM_PASS_BEGIN INITIALIZE_PASS_BEGIN
661 /// Target machine pass initializer for passes with dependencies. Use with
662 /// INITIALIZE_TM_PASS_BEGIN.
663 #define INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis) \
664 PassInfo *PI = new PassInfo(name, arg, & passName ::ID, \
665 PassInfo::NormalCtor_t(callDefaultCtor< passName >), cfg, analysis, \
666 PassInfo::TargetMachineCtor_t(callTargetMachineCtor< passName >)); \
667 Registry.registerPass(*PI, true); \
670 void llvm::initialize##passName##Pass(PassRegistry &Registry) { \
671 CALL_ONCE_INITIALIZATION(initialize##passName##PassOnce) \
674 /// This initializer registers TargetMachine constructor, so the pass being
675 /// initialized can use target dependent interfaces. Please do not move this
676 /// macro to be together with INITIALIZE_PASS, which is a complete target
677 /// independent initializer, and we don't want to make libScalarOpts depend
679 #define INITIALIZE_TM_PASS(passName, arg, name, cfg, analysis) \
680 INITIALIZE_TM_PASS_BEGIN(passName, arg, name, cfg, analysis) \
681 INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis)