1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
25 class MachineFunctionPass;
28 class ScheduleDAGInstrs;
30 class TargetLoweringBase;
31 class TargetRegisterClass;
33 struct MachineSchedContext;
35 // The old pass manager infrastructure is hidden in a legacy namespace now.
37 class PassManagerBase;
39 using legacy::PassManagerBase;
41 /// Discriminated union of Pass ID types.
43 /// The PassConfig API prefers dealing with IDs because they are safer and more
44 /// efficient. IDs decouple configuration from instantiation. This way, when a
45 /// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to
46 /// refer to a Pass pointer after adding it to a pass manager, which deletes
47 /// redundant pass instances.
49 /// However, it is convient to directly instantiate target passes with
50 /// non-default ctors. These often don't have a registered PassInfo. Rather than
51 /// force all target passes to implement the pass registry boilerplate, allow
52 /// the PassConfig API to handle either type.
54 /// AnalysisID is sadly char*, so PointerIntPair won't work.
55 class IdentifyingPassPtr {
62 IdentifyingPassPtr() : P(nullptr), IsInstance(false) {}
63 IdentifyingPassPtr(AnalysisID IDPtr) : ID(IDPtr), IsInstance(false) {}
64 IdentifyingPassPtr(Pass *InstancePtr) : P(InstancePtr), IsInstance(true) {}
66 bool isValid() const { return P; }
67 bool isInstance() const { return IsInstance; }
69 AnalysisID getID() const {
70 assert(!IsInstance && "Not a Pass ID");
73 Pass *getInstance() const {
74 assert(IsInstance && "Not a Pass Instance");
79 template <> struct isPodLike<IdentifyingPassPtr> {
80 static const bool value = true;
83 /// Target-Independent Code Generator Pass Configuration Options.
85 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
86 /// to the internals of other CodeGen passes.
87 class TargetPassConfig : public ImmutablePass {
89 /// Pseudo Pass IDs. These are defined within TargetPassConfig because they
90 /// are unregistered pass IDs. They are only useful for use with
91 /// TargetPassConfig APIs to identify multiple occurrences of the same pass.
94 /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early
95 /// during codegen, on SSA form.
96 static char EarlyTailDuplicateID;
98 /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine
99 /// optimization after regalloc.
100 static char PostRAMachineLICMID;
104 AnalysisID StartBefore, StartAfter;
105 AnalysisID StopAfter;
108 bool AddingMachinePasses;
112 PassConfigImpl *Impl; // Internal data structures
113 bool Initialized; // Flagged after all passes are configured.
115 // Target Pass Options
116 // Targets provide a default setting, user flags override.
120 /// Default setting for -enable-tail-merge on this target.
121 bool EnableTailMerge;
123 /// Default setting for -enable-shrink-wrap on this target.
124 bool EnableShrinkWrap;
127 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
128 // Dummy constructor.
131 ~TargetPassConfig() override;
135 /// Get the right type of TargetMachine for this target.
136 template<typename TMC> TMC &getTM() const {
137 return *static_cast<TMC*>(TM);
141 void setInitialized() { Initialized = true; }
143 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
145 /// Set the StartAfter, StartBefore and StopAfter passes to allow running only
146 /// a portion of the normal code-gen pass sequence.
148 /// If the StartAfter and StartBefore pass ID is zero, then compilation will
149 /// begin at the normal point; otherwise, clear the Started flag to indicate
150 /// that passes should not be added until the starting pass is seen. If the
151 /// Stop pass ID is zero, then compilation will continue to the end.
153 /// This function expects that at least one of the StartAfter or the
154 /// StartBefore pass IDs is null.
155 void setStartStopPasses(AnalysisID StartBefore, AnalysisID StartAfter,
156 AnalysisID StopAfter) {
158 assert(!StartBefore && "Start after and start before passes are given");
159 this->StartBefore = StartBefore;
160 this->StartAfter = StartAfter;
161 this->StopAfter = StopAfter;
162 Started = (StartAfter == nullptr) && (StartBefore == nullptr);
165 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
167 bool getEnableTailMerge() const { return EnableTailMerge; }
168 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
170 /// Allow the target to override a specific pass without overriding the pass
171 /// pipeline. When passes are added to the standard pipeline at the
172 /// point where StandardID is expected, add TargetID in its place.
173 void substitutePass(AnalysisID StandardID, IdentifyingPassPtr TargetID);
175 /// Insert InsertedPassID pass after TargetPassID pass.
176 void insertPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID);
178 /// Allow the target to enable a specific standard pass by default.
179 void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
181 /// Allow the target to disable a specific standard pass by default.
182 void disablePass(AnalysisID PassID) {
183 substitutePass(PassID, IdentifyingPassPtr());
186 /// Return the pass substituted for StandardID by the target.
187 /// If no substitution exists, return StandardID.
188 IdentifyingPassPtr getPassSubstitution(AnalysisID StandardID) const;
190 /// Return true if the optimized regalloc pipeline is enabled.
191 bool getOptimizeRegAlloc() const;
193 /// Return true if shrink wrapping is enabled.
194 bool getEnableShrinkWrap() const;
196 /// Return true if the default global register allocator is in use and
197 /// has not be overriden on the command line with '-regalloc=...'
198 bool usingDefaultRegAlloc() const;
200 /// Add common target configurable passes that perform LLVM IR to IR
201 /// transforms following machine independent optimization.
202 virtual void addIRPasses();
204 /// Add passes to lower exception handling for the code generator.
205 void addPassesToHandleExceptions();
207 /// Add pass to prepare the LLVM IR for code generation. This should be done
208 /// before exception handling preparation passes.
209 virtual void addCodeGenPrepare();
211 /// Add common passes that perform LLVM IR to IR transforms in preparation for
212 /// instruction selection.
213 virtual void addISelPrepare();
215 /// addInstSelector - This method should install an instruction selector pass,
216 /// which converts from LLVM code to machine instructions.
217 virtual bool addInstSelector() {
221 /// Add the complete, standard set of LLVM CodeGen passes.
222 /// Fully developed targets will not generally override this.
223 virtual void addMachinePasses();
225 /// Create an instance of ScheduleDAGInstrs to be run within the standard
226 /// MachineScheduler pass for this function and target at the current
227 /// optimization level.
229 /// This can also be used to plug a new MachineSchedStrategy into an instance
230 /// of the standard ScheduleDAGMI:
231 /// return new ScheduleDAGMI(C, make_unique<MyStrategy>(C), /* IsPostRA= */false)
233 /// Return NULL to select the default (generic) machine scheduler.
234 virtual ScheduleDAGInstrs *
235 createMachineScheduler(MachineSchedContext *C) const {
239 /// Similar to createMachineScheduler but used when postRA machine scheduling
241 virtual ScheduleDAGInstrs *
242 createPostMachineScheduler(MachineSchedContext *C) const {
247 // Helper to verify the analysis is really immutable.
248 void setOpt(bool &Opt, bool Val);
250 /// Methods with trivial inline returns are convenient points in the common
251 /// codegen pass pipeline where targets may insert passes. Methods with
252 /// out-of-line standard implementations are major CodeGen stages called by
253 /// addMachinePasses. Some targets may override major stages when inserting
254 /// passes is insufficient, but maintaining overriden stages is more work.
257 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
258 /// passes (which are run just before instruction selector).
259 virtual bool addPreISel() {
263 /// addMachineSSAOptimization - Add standard passes that optimize machine
264 /// instructions in SSA form.
265 virtual void addMachineSSAOptimization();
267 /// Add passes that optimize instruction level parallelism for out-of-order
268 /// targets. These passes are run while the machine code is still in SSA
269 /// form, so they can use MachineTraceMetrics to control their heuristics.
271 /// All passes added here should preserve the MachineDominatorTree,
272 /// MachineLoopInfo, and MachineTraceMetrics analyses.
273 virtual bool addILPOpts() {
277 /// This method may be implemented by targets that want to run passes
278 /// immediately before register allocation.
279 virtual void addPreRegAlloc() { }
281 /// createTargetRegisterAllocator - Create the register allocator pass for
282 /// this target at the current optimization level.
283 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
285 /// addFastRegAlloc - Add the minimum set of target-independent passes that
286 /// are required for fast register allocation.
287 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
289 /// addOptimizedRegAlloc - Add passes related to register allocation.
290 /// LLVMTargetMachine provides standard regalloc passes for most targets.
291 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
293 /// addPreRewrite - Add passes to the optimized register allocation pipeline
294 /// after register allocation is complete, but before virtual registers are
295 /// rewritten to physical registers.
297 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
298 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
299 /// When these passes run, VirtRegMap contains legal physreg assignments for
300 /// all virtual registers.
301 virtual bool addPreRewrite() {
305 /// This method may be implemented by targets that want to run passes after
306 /// register allocation pass pipeline but before prolog-epilog insertion.
307 virtual void addPostRegAlloc() { }
309 /// Add passes that optimize machine instructions after register allocation.
310 virtual void addMachineLateOptimization();
312 /// This method may be implemented by targets that want to run passes after
313 /// prolog-epilog insertion and before the second instruction scheduling pass.
314 virtual void addPreSched2() { }
316 /// addGCPasses - Add late codegen passes that analyze code for garbage
317 /// collection. This should return true if GC info should be printed after
319 virtual bool addGCPasses();
321 /// Add standard basic block placement passes.
322 virtual void addBlockPlacement();
324 /// This pass may be implemented by targets that want to run passes
325 /// immediately before machine code is emitted.
326 virtual void addPreEmitPass() { }
328 /// Utilities for targets to add passes to the pass manager.
331 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
332 /// Return the pass that was added, or zero if no pass was added.
333 /// @p printAfter if true and adding a machine function pass add an extra
334 /// machine printer pass afterwards
335 /// @p verifyAfter if true and adding a machine function pass add an extra
336 /// machine verification pass afterwards.
337 AnalysisID addPass(AnalysisID PassID, bool verifyAfter = true,
338 bool printAfter = true);
340 /// Add a pass to the PassManager if that pass is supposed to be run, as
341 /// determined by the StartAfter and StopAfter options. Takes ownership of the
343 /// @p printAfter if true and adding a machine function pass add an extra
344 /// machine printer pass afterwards
345 /// @p verifyAfter if true and adding a machine function pass add an extra
346 /// machine verification pass afterwards.
347 void addPass(Pass *P, bool verifyAfter = true, bool printAfter = true);
349 /// addMachinePasses helper to create the target-selected or overriden
351 FunctionPass *createRegAllocPass(bool Optimized);
353 /// printAndVerify - Add a pass to dump then verify the machine function, if
354 /// those steps are enabled.
356 void printAndVerify(const std::string &Banner);
358 /// Add a pass to print the machine function if printing is enabled.
359 void addPrintPass(const std::string &Banner);
361 /// Add a pass to perform basic verification of the machine function if
362 /// verification is enabled.
363 void addVerifyPass(const std::string &Banner);
367 /// List of target independent CodeGen pass IDs.
369 FunctionPass *createAtomicExpandPass(const TargetMachine *TM);
371 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
372 /// work well with unreachable basic blocks (what live ranges make sense for a
373 /// block that cannot be reached?). As such, a code generator should either
374 /// not instruction select unreachable blocks, or run this pass as its
375 /// last LLVM modifying pass to clean up blocks that are not reachable from
377 FunctionPass *createUnreachableBlockEliminationPass();
379 /// MachineFunctionPrinter pass - This pass prints out the machine function to
380 /// the given stream as a debugging tool.
381 MachineFunctionPass *
382 createMachineFunctionPrinterPass(raw_ostream &OS,
383 const std::string &Banner ="");
385 /// MIRPrinting pass - this pass prints out the LLVM IR into the given stream
386 /// using the MIR serialization format.
387 MachineFunctionPass *createPrintMIRPass(raw_ostream &OS);
389 /// createCodeGenPreparePass - Transform the code to expose more pattern
390 /// matching during instruction selection.
391 FunctionPass *createCodeGenPreparePass(const TargetMachine *TM = nullptr);
393 /// AtomicExpandID -- Lowers atomic operations in terms of either cmpxchg
394 /// load-linked/store-conditional loops.
395 extern char &AtomicExpandID;
397 /// MachineLoopInfo - This pass is a loop analysis pass.
398 extern char &MachineLoopInfoID;
400 /// MachineDominators - This pass is a machine dominators analysis pass.
401 extern char &MachineDominatorsID;
403 /// MachineDominanaceFrontier - This pass is a machine dominators analysis pass.
404 extern char &MachineDominanceFrontierID;
406 /// EdgeBundles analysis - Bundle machine CFG edges.
407 extern char &EdgeBundlesID;
409 /// LiveVariables pass - This pass computes the set of blocks in which each
410 /// variable is life and sets machine operand kill flags.
411 extern char &LiveVariablesID;
413 /// PHIElimination - This pass eliminates machine instruction PHI nodes
414 /// by inserting copy instructions. This destroys SSA information, but is the
415 /// desired input for some register allocators. This pass is "required" by
416 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
417 extern char &PHIEliminationID;
419 /// LiveIntervals - This analysis keeps track of the live ranges of virtual
420 /// and physical registers.
421 extern char &LiveIntervalsID;
423 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
424 extern char &LiveStacksID;
426 /// TwoAddressInstruction - This pass reduces two-address instructions to
427 /// use two operands. This destroys SSA information but it is desired by
428 /// register allocators.
429 extern char &TwoAddressInstructionPassID;
431 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
432 extern char &ProcessImplicitDefsID;
434 /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
435 extern char &RegisterCoalescerID;
437 /// MachineScheduler - This pass schedules machine instructions.
438 extern char &MachineSchedulerID;
440 /// PostMachineScheduler - This pass schedules machine instructions postRA.
441 extern char &PostMachineSchedulerID;
443 /// SpillPlacement analysis. Suggest optimal placement of spill code between
445 extern char &SpillPlacementID;
447 /// ShrinkWrap pass. Look for the best place to insert save and restore
448 // instruction and update the MachineFunctionInfo with that information.
449 extern char &ShrinkWrapID;
451 /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
452 /// assigned in VirtRegMap.
453 extern char &VirtRegRewriterID;
455 /// UnreachableMachineBlockElimination - This pass removes unreachable
456 /// machine basic blocks.
457 extern char &UnreachableMachineBlockElimID;
459 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
460 extern char &DeadMachineInstructionElimID;
462 /// FastRegisterAllocation Pass - This pass register allocates as fast as
463 /// possible. It is best suited for debug code where live ranges are short.
465 FunctionPass *createFastRegisterAllocator();
467 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
468 /// register allocator using the basic regalloc framework.
470 FunctionPass *createBasicRegisterAllocator();
472 /// Greedy register allocation pass - This pass implements a global register
473 /// allocator for optimized builds.
475 FunctionPass *createGreedyRegisterAllocator();
477 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
478 /// Quadratic Prograaming (PBQP) based register allocator.
480 FunctionPass *createDefaultPBQPRegisterAllocator();
482 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
483 /// and eliminates abstract frame references.
484 extern char &PrologEpilogCodeInserterID;
486 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
487 /// register allocation.
488 extern char &ExpandPostRAPseudosID;
490 /// createPostRAScheduler - This pass performs post register allocation
492 extern char &PostRASchedulerID;
494 /// BranchFolding - This pass performs machine code CFG based
495 /// optimizations to delete branches to branches, eliminate branches to
496 /// successor blocks (creating fall throughs), and eliminating branches over
498 extern char &BranchFolderPassID;
500 /// MachineFunctionPrinterPass - This pass prints out MachineInstr's.
501 extern char &MachineFunctionPrinterPassID;
503 /// MIRPrintingPass - this pass prints out the LLVM IR using the MIR
504 /// serialization format.
505 extern char &MIRPrintingPassID;
507 /// TailDuplicate - Duplicate blocks with unconditional branches
508 /// into tails of their predecessors.
509 extern char &TailDuplicateID;
511 /// MachineTraceMetrics - This pass computes critical path and CPU resource
512 /// usage in an ensemble of traces.
513 extern char &MachineTraceMetricsID;
515 /// EarlyIfConverter - This pass performs if-conversion on SSA form by
516 /// inserting cmov instructions.
517 extern char &EarlyIfConverterID;
519 /// This pass performs instruction combining using trace metrics to estimate
520 /// critical-path and resource depth.
521 extern char &MachineCombinerID;
523 /// StackSlotColoring - This pass performs stack coloring and merging.
524 /// It merges disjoint allocas to reduce the stack size.
525 extern char &StackColoringID;
527 /// IfConverter - This pass performs machine code if conversion.
528 extern char &IfConverterID;
530 FunctionPass *createIfConverter(std::function<bool(const Function &)> Ftor);
532 /// MachineBlockPlacement - This pass places basic blocks based on branch
534 extern char &MachineBlockPlacementID;
536 /// MachineBlockPlacementStats - This pass collects statistics about the
537 /// basic block placement using branch probabilities and block frequency
539 extern char &MachineBlockPlacementStatsID;
541 /// GCLowering Pass - Used by gc.root to perform its default lowering
543 FunctionPass *createGCLoweringPass();
545 /// ShadowStackGCLowering - Implements the custom lowering mechanism
546 /// used by the shadow stack GC. Only runs on functions which opt in to
547 /// the shadow stack collector.
548 FunctionPass *createShadowStackGCLoweringPass();
550 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
551 /// in machine code. Must be added very late during code generation, just
552 /// prior to output, and importantly after all CFG transformations (such as
554 extern char &GCMachineCodeAnalysisID;
556 /// Creates a pass to print GC metadata.
558 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
560 /// MachineCSE - This pass performs global CSE on machine instructions.
561 extern char &MachineCSEID;
563 /// ImplicitNullChecks - This pass folds null pointer checks into nearby
564 /// memory operations.
565 extern char &ImplicitNullChecksID;
567 /// MachineLICM - This pass performs LICM on machine instructions.
568 extern char &MachineLICMID;
570 /// MachineSinking - This pass performs sinking on machine instructions.
571 extern char &MachineSinkingID;
573 /// MachineCopyPropagation - This pass performs copy propagation on
574 /// machine instructions.
575 extern char &MachineCopyPropagationID;
577 /// PeepholeOptimizer - This pass performs peephole optimizations -
578 /// like extension and comparison eliminations.
579 extern char &PeepholeOptimizerID;
581 /// OptimizePHIs - This pass optimizes machine instruction PHIs
582 /// to take advantage of opportunities created during DAG legalization.
583 extern char &OptimizePHIsID;
585 /// StackSlotColoring - This pass performs stack slot coloring.
586 extern char &StackSlotColoringID;
588 /// createStackProtectorPass - This pass adds stack protectors to functions.
590 FunctionPass *createStackProtectorPass(const TargetMachine *TM);
592 /// createMachineVerifierPass - This pass verifies cenerated machine code
593 /// instructions for correctness.
595 FunctionPass *createMachineVerifierPass(const std::string& Banner);
597 /// createDwarfEHPass - This pass mulches exception handling code into a form
598 /// adapted to code generation. Required if using dwarf exception handling.
599 FunctionPass *createDwarfEHPass(const TargetMachine *TM);
601 /// createWinEHPass - Prepares personality functions used by MSVC on Windows,
602 /// in addition to the Itanium LSDA based personalities.
603 FunctionPass *createWinEHPass(const TargetMachine *TM);
605 /// createSjLjEHPreparePass - This pass adapts exception handling code to use
606 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
608 FunctionPass *createSjLjEHPreparePass();
610 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
611 /// slots relative to one another and allocates base registers to access them
612 /// when it is estimated by the target to be out of range of normal frame
613 /// pointer or stack pointer index addressing.
614 extern char &LocalStackSlotAllocationID;
616 /// ExpandISelPseudos - This pass expands pseudo-instructions.
617 extern char &ExpandISelPseudosID;
619 /// createExecutionDependencyFixPass - This pass fixes execution time
620 /// problems with dependent instructions, such as switching execution
621 /// domains to match.
623 /// The pass will examine instructions using and defining registers in RC.
625 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
627 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
628 extern char &UnpackMachineBundlesID;
631 createUnpackMachineBundles(std::function<bool(const Function &)> Ftor);
633 /// FinalizeMachineBundles - This pass finalize machine instruction
634 /// bundles (created earlier, e.g. during pre-RA scheduling).
635 extern char &FinalizeMachineBundlesID;
637 /// StackMapLiveness - This pass analyses the register live-out set of
638 /// stackmap/patchpoint intrinsics and attaches the calculated information to
639 /// the intrinsic for later emission to the StackMap.
640 extern char &StackMapLivenessID;
642 /// createJumpInstrTables - This pass creates jump-instruction tables.
643 ModulePass *createJumpInstrTablesPass();
645 /// createForwardControlFlowIntegrityPass - This pass adds control-flow
647 ModulePass *createForwardControlFlowIntegrityPass();
649 /// InterleavedAccess Pass - This pass identifies and matches interleaved
650 /// memory accesses to target specific intrinsics.
652 FunctionPass *createInterleavedAccessPass(const TargetMachine *TM);
653 } // End llvm namespace
655 /// Target machine pass initializer for passes with dependencies. Use with
656 /// INITIALIZE_TM_PASS_END.
657 #define INITIALIZE_TM_PASS_BEGIN INITIALIZE_PASS_BEGIN
659 /// Target machine pass initializer for passes with dependencies. Use with
660 /// INITIALIZE_TM_PASS_BEGIN.
661 #define INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis) \
662 PassInfo *PI = new PassInfo(name, arg, & passName ::ID, \
663 PassInfo::NormalCtor_t(callDefaultCtor< passName >), cfg, analysis, \
664 PassInfo::TargetMachineCtor_t(callTargetMachineCtor< passName >)); \
665 Registry.registerPass(*PI, true); \
668 void llvm::initialize##passName##Pass(PassRegistry &Registry) { \
669 CALL_ONCE_INITIALIZATION(initialize##passName##PassOnce) \
672 /// This initializer registers TargetMachine constructor, so the pass being
673 /// initialized can use target dependent interfaces. Please do not move this
674 /// macro to be together with INITIALIZE_PASS, which is a complete target
675 /// independent initializer, and we don't want to make libScalarOpts depend
677 #define INITIALIZE_TM_PASS(passName, arg, name, cfg, analysis) \
678 INITIALIZE_TM_PASS_BEGIN(passName, arg, name, cfg, analysis) \
679 INITIALIZE_TM_PASS_END(passName, arg, name, cfg, analysis)