1 //===-- Passes.h - Target independent code generation passes ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code generation
11 // passes provided by the LLVM backend.
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_CODEGEN_PASSES_H
16 #define LLVM_CODEGEN_PASSES_H
18 #include "llvm/Pass.h"
19 #include "llvm/Target/TargetMachine.h"
25 class MachineFunctionPass;
27 class PassManagerBase;
28 class TargetLoweringBase;
30 class TargetRegisterClass;
38 /// Target-Independent Code Generator Pass Configuration Options.
40 /// This is an ImmutablePass solely for the purpose of exposing CodeGen options
41 /// to the internals of other CodeGen passes.
42 class TargetPassConfig : public ImmutablePass {
44 /// Pseudo Pass IDs. These are defined within TargetPassConfig because they
45 /// are unregistered pass IDs. They are only useful for use with
46 /// TargetPassConfig APIs to identify multiple occurrences of the same pass.
49 /// EarlyTailDuplicate - A clone of the TailDuplicate pass that runs early
50 /// during codegen, on SSA form.
51 static char EarlyTailDuplicateID;
53 /// PostRAMachineLICM - A clone of the LICM pass that runs during late machine
54 /// optimization after regalloc.
55 static char PostRAMachineLICMID;
59 AnalysisID StartAfter;
66 PassConfigImpl *Impl; // Internal data structures
67 bool Initialized; // Flagged after all passes are configured.
69 // Target Pass Options
70 // Targets provide a default setting, user flags override.
74 /// Default setting for -enable-tail-merge on this target.
78 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
82 virtual ~TargetPassConfig();
86 /// Get the right type of TargetMachine for this target.
87 template<typename TMC> TMC &getTM() const {
88 return *static_cast<TMC*>(TM);
91 const TargetLowering *getTargetLowering() const {
92 return TM->getTargetLowering();
96 void setInitialized() { Initialized = true; }
98 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
100 /// setStartStopPasses - Set the StartAfter and StopAfter passes to allow
101 /// running only a portion of the normal code-gen pass sequence. If the
102 /// Start pass ID is zero, then compilation will begin at the normal point;
103 /// otherwise, clear the Started flag to indicate that passes should not be
104 /// added until the starting pass is seen. If the Stop pass ID is zero,
105 /// then compilation will continue to the end.
106 void setStartStopPasses(AnalysisID Start, AnalysisID Stop) {
109 Started = (StartAfter == 0);
112 void setDisableVerify(bool Disable) { setOpt(DisableVerify, Disable); }
114 bool getEnableTailMerge() const { return EnableTailMerge; }
115 void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); }
117 /// Allow the target to override a specific pass without overriding the pass
118 /// pipeline. When passes are added to the standard pipeline at the
119 /// point where StandardID is expected, add TargetID in its place.
120 void substitutePass(AnalysisID StandardID, AnalysisID TargetID);
122 /// Insert InsertedPassID pass after TargetPassID pass.
123 void insertPass(AnalysisID TargetPassID, AnalysisID InsertedPassID);
125 /// Allow the target to enable a specific standard pass by default.
126 void enablePass(AnalysisID PassID) { substitutePass(PassID, PassID); }
128 /// Allow the target to disable a specific standard pass by default.
129 void disablePass(AnalysisID PassID) { substitutePass(PassID, 0); }
131 /// Return the pass substituted for StandardID by the target.
132 /// If no substitution exists, return StandardID.
133 AnalysisID getPassSubstitution(AnalysisID StandardID) const;
135 /// Return true if the optimized regalloc pipeline is enabled.
136 bool getOptimizeRegAlloc() const;
138 /// Add common target configurable passes that perform LLVM IR to IR
139 /// transforms following machine independent optimization.
140 virtual void addIRPasses();
142 /// Add passes to lower exception handling for the code generator.
143 void addPassesToHandleExceptions();
145 /// Add pass to prepare the LLVM IR for code generation. This should be done
146 /// before exception handling preparation passes.
147 virtual void addCodeGenPrepare();
149 /// Add common passes that perform LLVM IR to IR transforms in preparation for
150 /// instruction selection.
151 virtual void addISelPrepare();
153 /// addInstSelector - This method should install an instruction selector pass,
154 /// which converts from LLVM code to machine instructions.
155 virtual bool addInstSelector() {
159 /// Add the complete, standard set of LLVM CodeGen passes.
160 /// Fully developed targets will not generally override this.
161 virtual void addMachinePasses();
164 // Helper to verify the analysis is really immutable.
165 void setOpt(bool &Opt, bool Val);
167 /// Methods with trivial inline returns are convenient points in the common
168 /// codegen pass pipeline where targets may insert passes. Methods with
169 /// out-of-line standard implementations are major CodeGen stages called by
170 /// addMachinePasses. Some targets may override major stages when inserting
171 /// passes is insufficient, but maintaining overriden stages is more work.
174 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
175 /// passes (which are run just before instruction selector).
176 virtual bool addPreISel() {
180 /// addMachineSSAOptimization - Add standard passes that optimize machine
181 /// instructions in SSA form.
182 virtual void addMachineSSAOptimization();
184 /// addPreRegAlloc - This method may be implemented by targets that want to
185 /// run passes immediately before register allocation. This should return
186 /// true if -print-machineinstrs should print after these passes.
187 virtual bool addPreRegAlloc() {
191 /// createTargetRegisterAllocator - Create the register allocator pass for
192 /// this target at the current optimization level.
193 virtual FunctionPass *createTargetRegisterAllocator(bool Optimized);
195 /// addFastRegAlloc - Add the minimum set of target-independent passes that
196 /// are required for fast register allocation.
197 virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
199 /// addOptimizedRegAlloc - Add passes related to register allocation.
200 /// LLVMTargetMachine provides standard regalloc passes for most targets.
201 virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
203 /// addPreRewrite - Add passes to the optimized register allocation pipeline
204 /// after register allocation is complete, but before virtual registers are
205 /// rewritten to physical registers.
207 /// These passes must preserve VirtRegMap and LiveIntervals, and when running
208 /// after RABasic or RAGreedy, they should take advantage of LiveRegMatrix.
209 /// When these passes run, VirtRegMap contains legal physreg assignments for
210 /// all virtual registers.
211 virtual bool addPreRewrite() {
215 /// addFinalizeRegAlloc - This method may be implemented by targets that want
216 /// to run passes within the regalloc pipeline, immediately after the register
217 /// allocation pass itself. These passes run as soon as virtual regisiters
218 /// have been rewritten to physical registers but before and other postRA
219 /// optimization happens. Targets that have marked instructions for bundling
220 /// must have finalized those bundles by the time these passes have run,
221 /// because subsequent passes are not guaranteed to be bundle-aware.
222 virtual bool addFinalizeRegAlloc() {
226 /// addPostRegAlloc - This method may be implemented by targets that want to
227 /// run passes after register allocation pass pipeline but before
228 /// prolog-epilog insertion. This should return true if -print-machineinstrs
229 /// should print after these passes.
230 virtual bool addPostRegAlloc() {
234 /// Add passes that optimize machine instructions after register allocation.
235 virtual void addMachineLateOptimization();
237 /// addPreSched2 - This method may be implemented by targets that want to
238 /// run passes after prolog-epilog insertion and before the second instruction
239 /// scheduling pass. This should return true if -print-machineinstrs should
240 /// print after these passes.
241 virtual bool addPreSched2() {
245 /// addGCPasses - Add late codegen passes that analyze code for garbage
246 /// collection. This should return true if GC info should be printed after
248 virtual bool addGCPasses();
250 /// Add standard basic block placement passes.
251 virtual void addBlockPlacement();
253 /// addPreEmitPass - This pass may be implemented by targets that want to run
254 /// passes immediately before machine code is emitted. This should return
255 /// true if -print-machineinstrs should print out the code after the passes.
256 virtual bool addPreEmitPass() {
260 /// Utilities for targets to add passes to the pass manager.
263 /// Add a CodeGen pass at this point in the pipeline after checking overrides.
264 /// Return the pass that was added, or zero if no pass was added.
265 AnalysisID addPass(AnalysisID PassID);
267 /// Add a pass to the PassManager if that pass is supposed to be run, as
268 /// determined by the StartAfter and StopAfter options.
269 void addPass(Pass *P);
271 /// addMachinePasses helper to create the target-selected or overriden
273 FunctionPass *createRegAllocPass(bool Optimized);
275 /// printAndVerify - Add a pass to dump then verify the machine function, if
276 /// those steps are enabled.
278 void printAndVerify(const char *Banner);
282 /// List of target independent CodeGen pass IDs.
284 /// \brief Create a basic TargetTransformInfo analysis pass.
286 /// This pass implements the target transform info analysis using the target
287 /// independent information available to the LLVM code generator.
289 createBasicTargetTransformInfoPass(const TargetLoweringBase *TLI);
291 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
292 /// work well with unreachable basic blocks (what live ranges make sense for a
293 /// block that cannot be reached?). As such, a code generator should either
294 /// not instruction select unreachable blocks, or run this pass as its
295 /// last LLVM modifying pass to clean up blocks that are not reachable from
297 FunctionPass *createUnreachableBlockEliminationPass();
299 /// MachineFunctionPrinter pass - This pass prints out the machine function to
300 /// the given stream as a debugging tool.
301 MachineFunctionPass *
302 createMachineFunctionPrinterPass(raw_ostream &OS,
303 const std::string &Banner ="");
305 /// MachineLoopInfo - This pass is a loop analysis pass.
306 extern char &MachineLoopInfoID;
308 /// MachineDominators - This pass is a machine dominators analysis pass.
309 extern char &MachineDominatorsID;
311 /// EdgeBundles analysis - Bundle machine CFG edges.
312 extern char &EdgeBundlesID;
314 /// LiveVariables pass - This pass computes the set of blocks in which each
315 /// variable is life and sets machine operand kill flags.
316 extern char &LiveVariablesID;
318 /// PHIElimination - This pass eliminates machine instruction PHI nodes
319 /// by inserting copy instructions. This destroys SSA information, but is the
320 /// desired input for some register allocators. This pass is "required" by
321 /// these register allocator like this: AU.addRequiredID(PHIEliminationID);
322 extern char &PHIEliminationID;
324 /// StrongPHIElimination - This pass eliminates machine instruction PHI
325 /// nodes by inserting copy instructions. This destroys SSA information, but
326 /// is the desired input for some register allocators. This pass is
327 /// "required" by these register allocator like this:
328 /// AU.addRequiredID(PHIEliminationID);
329 /// This pass is still in development
330 extern char &StrongPHIEliminationID;
332 /// LiveIntervals - This analysis keeps track of the live ranges of virtual
333 /// and physical registers.
334 extern char &LiveIntervalsID;
336 /// LiveStacks pass. An analysis keeping track of the liveness of stack slots.
337 extern char &LiveStacksID;
339 /// TwoAddressInstruction - This pass reduces two-address instructions to
340 /// use two operands. This destroys SSA information but it is desired by
341 /// register allocators.
342 extern char &TwoAddressInstructionPassID;
344 /// ProcessImpicitDefs pass - This pass removes IMPLICIT_DEFs.
345 extern char &ProcessImplicitDefsID;
347 /// RegisterCoalescer - This pass merges live ranges to eliminate copies.
348 extern char &RegisterCoalescerID;
350 /// MachineScheduler - This pass schedules machine instructions.
351 extern char &MachineSchedulerID;
353 /// SpillPlacement analysis. Suggest optimal placement of spill code between
355 extern char &SpillPlacementID;
357 /// VirtRegRewriter pass. Rewrite virtual registers to physical registers as
358 /// assigned in VirtRegMap.
359 extern char &VirtRegRewriterID;
361 /// UnreachableMachineBlockElimination - This pass removes unreachable
362 /// machine basic blocks.
363 extern char &UnreachableMachineBlockElimID;
365 /// DeadMachineInstructionElim - This pass removes dead machine instructions.
366 extern char &DeadMachineInstructionElimID;
368 /// FastRegisterAllocation Pass - This pass register allocates as fast as
369 /// possible. It is best suited for debug code where live ranges are short.
371 FunctionPass *createFastRegisterAllocator();
373 /// BasicRegisterAllocation Pass - This pass implements a degenerate global
374 /// register allocator using the basic regalloc framework.
376 FunctionPass *createBasicRegisterAllocator();
378 /// Greedy register allocation pass - This pass implements a global register
379 /// allocator for optimized builds.
381 FunctionPass *createGreedyRegisterAllocator();
383 /// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
384 /// Quadratic Prograaming (PBQP) based register allocator.
386 FunctionPass *createDefaultPBQPRegisterAllocator();
388 /// PrologEpilogCodeInserter - This pass inserts prolog and epilog code,
389 /// and eliminates abstract frame references.
390 extern char &PrologEpilogCodeInserterID;
392 /// ExpandPostRAPseudos - This pass expands pseudo instructions after
393 /// register allocation.
394 extern char &ExpandPostRAPseudosID;
396 /// createPostRAScheduler - This pass performs post register allocation
398 extern char &PostRASchedulerID;
400 /// BranchFolding - This pass performs machine code CFG based
401 /// optimizations to delete branches to branches, eliminate branches to
402 /// successor blocks (creating fall throughs), and eliminating branches over
404 extern char &BranchFolderPassID;
406 /// MachineFunctionPrinterPass - This pass prints out MachineInstr's.
407 extern char &MachineFunctionPrinterPassID;
409 /// TailDuplicate - Duplicate blocks with unconditional branches
410 /// into tails of their predecessors.
411 extern char &TailDuplicateID;
413 /// MachineTraceMetrics - This pass computes critical path and CPU resource
414 /// usage in an ensemble of traces.
415 extern char &MachineTraceMetricsID;
417 /// EarlyIfConverter - This pass performs if-conversion on SSA form by
418 /// inserting cmov instructions.
419 extern char &EarlyIfConverterID;
421 /// StackSlotColoring - This pass performs stack coloring and merging.
422 /// It merges disjoint allocas to reduce the stack size.
423 extern char &StackColoringID;
425 /// IfConverter - This pass performs machine code if conversion.
426 extern char &IfConverterID;
428 /// MachineBlockPlacement - This pass places basic blocks based on branch
430 extern char &MachineBlockPlacementID;
432 /// MachineBlockPlacementStats - This pass collects statistics about the
433 /// basic block placement using branch probabilities and block frequency
435 extern char &MachineBlockPlacementStatsID;
437 /// Code Placement - This pass optimize code placement and aligns loop
438 /// headers to target specific alignment boundary.
439 extern char &CodePlacementOptID;
441 /// GCLowering Pass - Performs target-independent LLVM IR transformations for
442 /// highly portable strategies.
444 FunctionPass *createGCLoweringPass();
446 /// GCMachineCodeAnalysis - Target-independent pass to mark safe points
447 /// in machine code. Must be added very late during code generation, just
448 /// prior to output, and importantly after all CFG transformations (such as
450 extern char &GCMachineCodeAnalysisID;
452 /// Deleter Pass - Releases GC metadata.
454 FunctionPass *createGCInfoDeleter();
456 /// Creates a pass to print GC metadata.
458 FunctionPass *createGCInfoPrinter(raw_ostream &OS);
460 /// MachineCSE - This pass performs global CSE on machine instructions.
461 extern char &MachineCSEID;
463 /// MachineLICM - This pass performs LICM on machine instructions.
464 extern char &MachineLICMID;
466 /// MachineSinking - This pass performs sinking on machine instructions.
467 extern char &MachineSinkingID;
469 /// MachineCopyPropagation - This pass performs copy propagation on
470 /// machine instructions.
471 extern char &MachineCopyPropagationID;
473 /// PeepholeOptimizer - This pass performs peephole optimizations -
474 /// like extension and comparison eliminations.
475 extern char &PeepholeOptimizerID;
477 /// OptimizePHIs - This pass optimizes machine instruction PHIs
478 /// to take advantage of opportunities created during DAG legalization.
479 extern char &OptimizePHIsID;
481 /// StackSlotColoring - This pass performs stack slot coloring.
482 extern char &StackSlotColoringID;
484 /// createStackProtectorPass - This pass adds stack protectors to functions.
486 FunctionPass *createStackProtectorPass(const TargetLoweringBase *tli);
488 /// createMachineVerifierPass - This pass verifies cenerated machine code
489 /// instructions for correctness.
491 FunctionPass *createMachineVerifierPass(const char *Banner = 0);
493 /// createDwarfEHPass - This pass mulches exception handling code into a form
494 /// adapted to code generation. Required if using dwarf exception handling.
495 FunctionPass *createDwarfEHPass(const TargetMachine *tm);
497 /// createSjLjEHPreparePass - This pass adapts exception handling code to use
498 /// the GCC-style builtin setjmp/longjmp (sjlj) to handling EH control flow.
500 FunctionPass *createSjLjEHPreparePass(const TargetLoweringBase *tli);
502 /// LocalStackSlotAllocation - This pass assigns local frame indices to stack
503 /// slots relative to one another and allocates base registers to access them
504 /// when it is estimated by the target to be out of range of normal frame
505 /// pointer or stack pointer index addressing.
506 extern char &LocalStackSlotAllocationID;
508 /// ExpandISelPseudos - This pass expands pseudo-instructions.
509 extern char &ExpandISelPseudosID;
511 /// createExecutionDependencyFixPass - This pass fixes execution time
512 /// problems with dependent instructions, such as switching execution
513 /// domains to match.
515 /// The pass will examine instructions using and defining registers in RC.
517 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
519 /// UnpackMachineBundles - This pass unpack machine instruction bundles.
520 extern char &UnpackMachineBundlesID;
522 /// FinalizeMachineBundles - This pass finalize machine instruction
523 /// bundles (created earlier, e.g. during pre-RA scheduling).
524 extern char &FinalizeMachineBundlesID;
526 } // End llvm namespace