1 //==- MachineScheduler.h - MachineInstr Scheduling Pass ----------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides a MachineSchedRegistry for registering alternative machine
11 // schedulers. A Target may provide an alternative scheduler implementation by
12 // implementing the following boilerplate:
14 // static ScheduleDAGInstrs *createCustomMachineSched(MachineSchedContext *C) {
15 // return new CustomMachineScheduler(C);
17 // static MachineSchedRegistry
18 // SchedCustomRegistry("custom", "Run my target's custom scheduler",
19 // createCustomMachineSched);
21 // Inside <Target>PassConfig:
22 // enablePass(&MachineSchedulerID);
23 // MachineSchedRegistry::setDefault(createCustomMachineSched);
25 //===----------------------------------------------------------------------===//
27 #ifndef MACHINESCHEDULER_H
28 #define MACHINESCHEDULER_H
30 #include "llvm/CodeGen/MachinePassRegistry.h"
31 #include "llvm/CodeGen/RegisterPressure.h"
32 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
33 #include "llvm/Target/TargetInstrInfo.h"
34 #include "llvm/MC/MCInstrItineraries.h"
38 extern cl::opt<bool> ForceTopDown;
39 extern cl::opt<bool> ForceBottomUp;
43 class MachineDominatorTree;
44 class MachineLoopInfo;
45 class RegisterClassInfo;
46 class ScheduleDAGInstrs;
48 /// MachineSchedContext provides enough context from the MachineScheduler pass
49 /// for the target to instantiate a scheduler.
50 struct MachineSchedContext {
52 const MachineLoopInfo *MLI;
53 const MachineDominatorTree *MDT;
54 const TargetPassConfig *PassConfig;
58 RegisterClassInfo *RegClassInfo;
60 MachineSchedContext();
61 virtual ~MachineSchedContext();
64 /// MachineSchedRegistry provides a selection of available machine instruction
66 class MachineSchedRegistry : public MachinePassRegistryNode {
68 typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedContext *);
70 // RegisterPassParser requires a (misnamed) FunctionPassCtor type.
71 typedef ScheduleDAGCtor FunctionPassCtor;
73 static MachinePassRegistry Registry;
75 MachineSchedRegistry(const char *N, const char *D, ScheduleDAGCtor C)
76 : MachinePassRegistryNode(N, D, (MachinePassCtor)C) {
79 ~MachineSchedRegistry() { Registry.Remove(this); }
83 MachineSchedRegistry *getNext() const {
84 return (MachineSchedRegistry *)MachinePassRegistryNode::getNext();
86 static MachineSchedRegistry *getList() {
87 return (MachineSchedRegistry *)Registry.getList();
89 static ScheduleDAGCtor getDefault() {
90 return (ScheduleDAGCtor)Registry.getDefault();
92 static void setDefault(ScheduleDAGCtor C) {
93 Registry.setDefault((MachinePassCtor)C);
95 static void setDefault(StringRef Name) {
96 Registry.setDefault(Name);
98 static void setListener(MachinePassRegistryListener *L) {
99 Registry.setListener(L);
105 /// MachineSchedStrategy - Interface to the scheduling algorithm used by
107 class MachineSchedStrategy {
109 virtual ~MachineSchedStrategy() {}
111 /// Initialize the strategy after building the DAG for a new region.
112 virtual void initialize(ScheduleDAGMI *DAG) = 0;
114 /// Pick the next node to schedule, or return NULL. Set IsTopNode to true to
115 /// schedule the node at the top of the unscheduled region. Otherwise it will
116 /// be scheduled at the bottom.
117 virtual SUnit *pickNode(bool &IsTopNode) = 0;
119 /// Notify MachineSchedStrategy that ScheduleDAGMI has scheduled an
120 /// instruction and updated scheduled/remaining flags in the DAG nodes.
121 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
123 /// When all predecessor dependencies have been resolved, free this node for
124 /// top-down scheduling.
125 virtual void releaseTopNode(SUnit *SU) = 0;
126 /// When all successor dependencies have been resolved, free this node for
127 /// bottom-up scheduling.
128 virtual void releaseBottomNode(SUnit *SU) = 0;
131 /// ReadyQueue encapsulates vector of "ready" SUnits with basic convenience
132 /// methods for pushing and removing nodes. ReadyQueue's are uniquely identified
133 /// by an ID. SUnit::NodeQueueId is a mask of the ReadyQueues the SUnit is in.
135 /// This is a convenience class that may be used by implementations of
136 /// MachineSchedStrategy.
140 std::vector<SUnit*> Queue;
143 ReadyQueue(unsigned id, const Twine &name): ID(id), Name(name.str()) {}
145 unsigned getID() const { return ID; }
147 StringRef getName() const { return Name; }
149 // SU is in this queue if it's NodeQueueID is a superset of this ID.
150 bool isInQueue(SUnit *SU) const { return (SU->NodeQueueId & ID); }
152 bool empty() const { return Queue.empty(); }
154 unsigned size() const { return Queue.size(); }
156 typedef std::vector<SUnit*>::iterator iterator;
158 iterator begin() { return Queue.begin(); }
160 iterator end() { return Queue.end(); }
162 iterator find(SUnit *SU) {
163 return std::find(Queue.begin(), Queue.end(), SU);
166 void push(SUnit *SU) {
168 SU->NodeQueueId |= ID;
171 void remove(iterator I) {
172 (*I)->NodeQueueId &= ~ID;
182 /// ScheduleDAGMI is an implementation of ScheduleDAGInstrs that schedules
183 /// machine instructions while updating LiveIntervals and tracking regpressure.
184 class ScheduleDAGMI : public ScheduleDAGInstrs {
187 RegisterClassInfo *RegClassInfo;
188 MachineSchedStrategy *SchedImpl;
190 MachineBasicBlock::iterator LiveRegionEnd;
192 /// Register pressure in this region computed by buildSchedGraph.
193 IntervalPressure RegPressure;
194 RegPressureTracker RPTracker;
196 /// List of pressure sets that exceed the target's pressure limit before
197 /// scheduling, listed in increasing set ID order. Each pressure set is paired
198 /// with its max pressure in the currently scheduled regions.
199 std::vector<PressureElement> RegionCriticalPSets;
201 /// The top of the unscheduled zone.
202 MachineBasicBlock::iterator CurrentTop;
203 IntervalPressure TopPressure;
204 RegPressureTracker TopRPTracker;
206 /// The bottom of the unscheduled zone.
207 MachineBasicBlock::iterator CurrentBottom;
208 IntervalPressure BotPressure;
209 RegPressureTracker BotRPTracker;
212 /// The number of instructions scheduled so far. Used to cut off the
213 /// scheduler at the point determined by misched-cutoff.
214 unsigned NumInstrsScheduled;
218 ScheduleDAGMI(MachineSchedContext *C, MachineSchedStrategy *S):
219 ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
220 AA(C->AA), RegClassInfo(C->RegClassInfo), SchedImpl(S),
221 RPTracker(RegPressure), CurrentTop(), TopRPTracker(TopPressure),
222 CurrentBottom(), BotRPTracker(BotPressure) {
224 NumInstrsScheduled = 0;
228 virtual ~ScheduleDAGMI() {
232 MachineBasicBlock::iterator top() const { return CurrentTop; }
233 MachineBasicBlock::iterator bottom() const { return CurrentBottom; }
235 /// Implement the ScheduleDAGInstrs interface for handling the next scheduling
236 /// region. This covers all instructions in a block, while schedule() may only
238 void enterRegion(MachineBasicBlock *bb,
239 MachineBasicBlock::iterator begin,
240 MachineBasicBlock::iterator end,
244 /// Implement ScheduleDAGInstrs interface for scheduling a sequence of
245 /// reorderable instructions.
246 virtual void schedule();
248 /// Get current register pressure for the top scheduled instructions.
249 const IntervalPressure &getTopPressure() const { return TopPressure; }
250 const RegPressureTracker &getTopRPTracker() const { return TopRPTracker; }
252 /// Get current register pressure for the bottom scheduled instructions.
253 const IntervalPressure &getBotPressure() const { return BotPressure; }
254 const RegPressureTracker &getBotRPTracker() const { return BotRPTracker; }
256 /// Get register pressure for the entire scheduling region before scheduling.
257 const IntervalPressure &getRegPressure() const { return RegPressure; }
259 const std::vector<PressureElement> &getRegionCriticalPSets() const {
260 return RegionCriticalPSets;
263 /// getIssueWidth - Return the max instructions per scheduling group.
264 unsigned getIssueWidth() const {
265 return (InstrItins && InstrItins->SchedModel)
266 ? InstrItins->SchedModel->IssueWidth : 1;
269 /// getNumMicroOps - Return the number of issue slots required for this MI.
270 unsigned getNumMicroOps(MachineInstr *MI) const {
271 if (!InstrItins) return 1;
272 int UOps = InstrItins->getNumMicroOps(MI->getDesc().getSchedClass());
273 return (UOps >= 0) ? UOps : TII->getNumMicroOps(InstrItins, MI);
277 // Top-Level entry points for the schedule() driver...
279 /// Call ScheduleDAGInstrs::buildSchedGraph with register pressure tracking
280 /// enabled. This sets up three trackers. RPTracker will cover the entire DAG
281 /// region, TopTracker and BottomTracker will be initialized to the top and
282 /// bottom of the DAG region without covereing any unscheduled instruction.
283 void buildDAGWithRegPressure();
285 /// Identify DAG roots and setup scheduler queues.
288 /// Move an instruction and update register pressure.
289 void scheduleMI(SUnit *SU, bool IsTopNode);
291 /// Update scheduler DAG and queues after scheduling an instruction.
292 void updateQueues(SUnit *SU, bool IsTopNode);
294 /// Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues.
295 void placeDebugValues();
299 void initRegPressure();
301 void updateScheduledPressure(std::vector<unsigned> NewMaxPressure);
303 void moveInstruction(MachineInstr *MI, MachineBasicBlock::iterator InsertPos);
304 bool checkSchedLimit();
308 void releaseSucc(SUnit *SU, SDep *SuccEdge);
309 void releaseSuccessors(SUnit *SU);
310 void releasePred(SUnit *SU, SDep *PredEdge);
311 void releasePredecessors(SUnit *SU);