1 //==- MachineScheduler.h - MachineInstr Scheduling Pass ----------*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file provides a MachineSchedRegistry for registering alternative machine
11 // schedulers. A Target may provide an alternative scheduler implementation by
12 // implementing the following boilerplate:
14 // static ScheduleDAGInstrs *createCustomMachineSched(MachineSchedContext *C) {
15 // return new CustomMachineScheduler(C);
17 // static MachineSchedRegistry
18 // SchedCustomRegistry("custom", "Run my target's custom scheduler",
19 // createCustomMachineSched);
21 // Inside <Target>PassConfig:
22 // enablePass(&MachineSchedulerID);
23 // MachineSchedRegistry::setDefault(createCustomMachineSched);
25 //===----------------------------------------------------------------------===//
27 #ifndef LLVM_CODEGEN_MACHINESCHEDULER_H
28 #define LLVM_CODEGEN_MACHINESCHEDULER_H
30 #include "llvm/CodeGen/MachinePassRegistry.h"
31 #include "llvm/CodeGen/RegisterPressure.h"
32 #include "llvm/CodeGen/ScheduleDAGInstrs.h"
36 extern cl::opt<bool> ForceTopDown;
37 extern cl::opt<bool> ForceBottomUp;
41 class MachineDominatorTree;
42 class MachineLoopInfo;
43 class RegisterClassInfo;
44 class ScheduleDAGInstrs;
47 /// MachineSchedContext provides enough context from the MachineScheduler pass
48 /// for the target to instantiate a scheduler.
49 struct MachineSchedContext {
51 const MachineLoopInfo *MLI;
52 const MachineDominatorTree *MDT;
53 const TargetPassConfig *PassConfig;
57 RegisterClassInfo *RegClassInfo;
59 MachineSchedContext();
60 virtual ~MachineSchedContext();
63 /// MachineSchedRegistry provides a selection of available machine instruction
65 class MachineSchedRegistry : public MachinePassRegistryNode {
67 typedef ScheduleDAGInstrs *(*ScheduleDAGCtor)(MachineSchedContext *);
69 // RegisterPassParser requires a (misnamed) FunctionPassCtor type.
70 typedef ScheduleDAGCtor FunctionPassCtor;
72 static MachinePassRegistry Registry;
74 MachineSchedRegistry(const char *N, const char *D, ScheduleDAGCtor C)
75 : MachinePassRegistryNode(N, D, (MachinePassCtor)C) {
78 ~MachineSchedRegistry() { Registry.Remove(this); }
82 MachineSchedRegistry *getNext() const {
83 return (MachineSchedRegistry *)MachinePassRegistryNode::getNext();
85 static MachineSchedRegistry *getList() {
86 return (MachineSchedRegistry *)Registry.getList();
88 static ScheduleDAGCtor getDefault() {
89 return (ScheduleDAGCtor)Registry.getDefault();
91 static void setDefault(ScheduleDAGCtor C) {
92 Registry.setDefault((MachinePassCtor)C);
94 static void setDefault(StringRef Name) {
95 Registry.setDefault(Name);
97 static void setListener(MachinePassRegistryListener *L) {
98 Registry.setListener(L);
104 /// Define a generic scheduling policy for targets that don't provide their own
105 /// MachineSchedStrategy. This can be overriden for each scheduling region
106 /// before building the DAG.
107 struct MachineSchedPolicy {
108 // Allow the scheduler to disable register pressure tracking.
109 bool ShouldTrackPressure;
111 // Allow the scheduler to force top-down or bottom-up scheduling. If neither
112 // is true, the scheduler runs in both directions and converges.
116 MachineSchedPolicy():
117 ShouldTrackPressure(false), OnlyTopDown(false), OnlyBottomUp(false) {}
120 /// MachineSchedStrategy - Interface to the scheduling algorithm used by
123 /// Initialization sequence:
124 /// initPolicy -> shouldTrackPressure -> initialize(DAG) -> registerRoots
125 class MachineSchedStrategy {
127 virtual ~MachineSchedStrategy() {}
129 /// Optionally override the per-region scheduling policy.
130 virtual void initPolicy(MachineBasicBlock::iterator Begin,
131 MachineBasicBlock::iterator End,
132 unsigned NumRegionInstrs) {}
134 /// Check if pressure tracking is needed before building the DAG and
135 /// initializing this strategy. Called after initPolicy.
136 virtual bool shouldTrackPressure() const { return true; }
138 /// Initialize the strategy after building the DAG for a new region.
139 virtual void initialize(ScheduleDAGMI *DAG) = 0;
141 /// Notify this strategy that all roots have been released (including those
142 /// that depend on EntrySU or ExitSU).
143 virtual void registerRoots() {}
145 /// Pick the next node to schedule, or return NULL. Set IsTopNode to true to
146 /// schedule the node at the top of the unscheduled region. Otherwise it will
147 /// be scheduled at the bottom.
148 virtual SUnit *pickNode(bool &IsTopNode) = 0;
150 /// \brief Scheduler callback to notify that a new subtree is scheduled.
151 virtual void scheduleTree(unsigned SubtreeID) {}
153 /// Notify MachineSchedStrategy that ScheduleDAGMI has scheduled an
154 /// instruction and updated scheduled/remaining flags in the DAG nodes.
155 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
157 /// When all predecessor dependencies have been resolved, free this node for
158 /// top-down scheduling.
159 virtual void releaseTopNode(SUnit *SU) = 0;
160 /// When all successor dependencies have been resolved, free this node for
161 /// bottom-up scheduling.
162 virtual void releaseBottomNode(SUnit *SU) = 0;
165 /// ReadyQueue encapsulates vector of "ready" SUnits with basic convenience
166 /// methods for pushing and removing nodes. ReadyQueue's are uniquely identified
167 /// by an ID. SUnit::NodeQueueId is a mask of the ReadyQueues the SUnit is in.
169 /// This is a convenience class that may be used by implementations of
170 /// MachineSchedStrategy.
174 std::vector<SUnit*> Queue;
177 ReadyQueue(unsigned id, const Twine &name): ID(id), Name(name.str()) {}
179 unsigned getID() const { return ID; }
181 StringRef getName() const { return Name; }
183 // SU is in this queue if it's NodeQueueID is a superset of this ID.
184 bool isInQueue(SUnit *SU) const { return (SU->NodeQueueId & ID); }
186 bool empty() const { return Queue.empty(); }
188 void clear() { Queue.clear(); }
190 unsigned size() const { return Queue.size(); }
192 typedef std::vector<SUnit*>::iterator iterator;
194 iterator begin() { return Queue.begin(); }
196 iterator end() { return Queue.end(); }
198 ArrayRef<SUnit*> elements() { return Queue; }
200 iterator find(SUnit *SU) {
201 return std::find(Queue.begin(), Queue.end(), SU);
204 void push(SUnit *SU) {
206 SU->NodeQueueId |= ID;
209 iterator remove(iterator I) {
210 (*I)->NodeQueueId &= ~ID;
212 unsigned idx = I - Queue.begin();
214 return Queue.begin() + idx;
217 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
222 /// Mutate the DAG as a postpass after normal DAG building.
223 class ScheduleDAGMutation {
225 virtual ~ScheduleDAGMutation() {}
227 virtual void apply(ScheduleDAGMI *DAG) = 0;
230 /// ScheduleDAGMI is an implementation of ScheduleDAGInstrs that schedules
231 /// machine instructions while updating LiveIntervals and tracking regpressure.
232 class ScheduleDAGMI : public ScheduleDAGInstrs {
235 RegisterClassInfo *RegClassInfo;
236 MachineSchedStrategy *SchedImpl;
238 /// Information about DAG subtrees. If DFSResult is NULL, then SchedulerTrees
240 SchedDFSResult *DFSResult;
241 BitVector ScheduledTrees;
243 /// Topo - A topological ordering for SUnits which permits fast IsReachable
244 /// and similar queries.
245 ScheduleDAGTopologicalSort Topo;
247 /// Ordered list of DAG postprocessing steps.
248 std::vector<ScheduleDAGMutation*> Mutations;
250 MachineBasicBlock::iterator LiveRegionEnd;
252 // Map each SU to its summary of pressure changes. This array is updated for
253 // liveness during bottom-up scheduling. Top-down scheduling may proceed but
254 // has no affect on the pressure diffs.
255 PressureDiffs SUPressureDiffs;
257 /// Register pressure in this region computed by initRegPressure.
258 bool ShouldTrackPressure;
259 IntervalPressure RegPressure;
260 RegPressureTracker RPTracker;
262 /// List of pressure sets that exceed the target's pressure limit before
263 /// scheduling, listed in increasing set ID order. Each pressure set is paired
264 /// with its max pressure in the currently scheduled regions.
265 std::vector<PressureChange> RegionCriticalPSets;
267 /// The top of the unscheduled zone.
268 MachineBasicBlock::iterator CurrentTop;
269 IntervalPressure TopPressure;
270 RegPressureTracker TopRPTracker;
272 /// The bottom of the unscheduled zone.
273 MachineBasicBlock::iterator CurrentBottom;
274 IntervalPressure BotPressure;
275 RegPressureTracker BotRPTracker;
277 /// Record the next node in a scheduled cluster.
278 const SUnit *NextClusterPred;
279 const SUnit *NextClusterSucc;
282 /// The number of instructions scheduled so far. Used to cut off the
283 /// scheduler at the point determined by misched-cutoff.
284 unsigned NumInstrsScheduled;
288 ScheduleDAGMI(MachineSchedContext *C, MachineSchedStrategy *S):
289 ScheduleDAGInstrs(*C->MF, *C->MLI, *C->MDT, /*IsPostRA=*/false, C->LIS),
290 AA(C->AA), RegClassInfo(C->RegClassInfo), SchedImpl(S), DFSResult(0),
291 Topo(SUnits, &ExitSU), ShouldTrackPressure(false),
292 RPTracker(RegPressure), CurrentTop(), TopRPTracker(TopPressure),
293 CurrentBottom(), BotRPTracker(BotPressure),
294 NextClusterPred(NULL), NextClusterSucc(NULL) {
296 NumInstrsScheduled = 0;
300 virtual ~ScheduleDAGMI();
302 /// \brief Return true if register pressure tracking is enabled.
303 bool isTrackingPressure() const { return ShouldTrackPressure; }
305 /// Add a postprocessing step to the DAG builder.
306 /// Mutations are applied in the order that they are added after normal DAG
307 /// building and before MachineSchedStrategy initialization.
309 /// ScheduleDAGMI takes ownership of the Mutation object.
310 void addMutation(ScheduleDAGMutation *Mutation) {
311 Mutations.push_back(Mutation);
314 /// \brief True if an edge can be added from PredSU to SuccSU without creating
316 bool canAddEdge(SUnit *SuccSU, SUnit *PredSU);
318 /// \brief Add a DAG edge to the given SU with the given predecessor
321 /// \returns true if the edge may be added without creating a cycle OR if an
322 /// equivalent edge already existed (false indicates failure).
323 bool addEdge(SUnit *SuccSU, const SDep &PredDep);
325 MachineBasicBlock::iterator top() const { return CurrentTop; }
326 MachineBasicBlock::iterator bottom() const { return CurrentBottom; }
328 /// Implement the ScheduleDAGInstrs interface for handling the next scheduling
329 /// region. This covers all instructions in a block, while schedule() may only
331 void enterRegion(MachineBasicBlock *bb,
332 MachineBasicBlock::iterator begin,
333 MachineBasicBlock::iterator end,
334 unsigned regioninstrs) LLVM_OVERRIDE;
336 /// Implement ScheduleDAGInstrs interface for scheduling a sequence of
337 /// reorderable instructions.
338 virtual void schedule();
340 /// Change the position of an instruction within the basic block and update
341 /// live ranges and region boundary iterators.
342 void moveInstruction(MachineInstr *MI, MachineBasicBlock::iterator InsertPos);
344 /// Get current register pressure for the top scheduled instructions.
345 const IntervalPressure &getTopPressure() const { return TopPressure; }
346 const RegPressureTracker &getTopRPTracker() const { return TopRPTracker; }
348 /// Get current register pressure for the bottom scheduled instructions.
349 const IntervalPressure &getBotPressure() const { return BotPressure; }
350 const RegPressureTracker &getBotRPTracker() const { return BotRPTracker; }
352 /// Get register pressure for the entire scheduling region before scheduling.
353 const IntervalPressure &getRegPressure() const { return RegPressure; }
355 const std::vector<PressureChange> &getRegionCriticalPSets() const {
356 return RegionCriticalPSets;
359 PressureDiff &getPressureDiff(const SUnit *SU) {
360 return SUPressureDiffs[SU->NodeNum];
363 const SUnit *getNextClusterPred() const { return NextClusterPred; }
365 const SUnit *getNextClusterSucc() const { return NextClusterSucc; }
367 /// Compute a DFSResult after DAG building is complete, and before any
368 /// queue comparisons.
369 void computeDFSResult();
371 /// Return a non-null DFS result if the scheduling strategy initialized it.
372 const SchedDFSResult *getDFSResult() const { return DFSResult; }
374 BitVector &getScheduledTrees() { return ScheduledTrees; }
376 /// Compute the cyclic critical path through the DAG.
377 unsigned computeCyclicCriticalPath();
379 void viewGraph(const Twine &Name, const Twine &Title) LLVM_OVERRIDE;
380 void viewGraph() LLVM_OVERRIDE;
383 // Top-Level entry points for the schedule() driver...
385 /// Call ScheduleDAGInstrs::buildSchedGraph with register pressure tracking
386 /// enabled. This sets up three trackers. RPTracker will cover the entire DAG
387 /// region, TopTracker and BottomTracker will be initialized to the top and
388 /// bottom of the DAG region without covereing any unscheduled instruction.
389 void buildDAGWithRegPressure();
391 /// Apply each ScheduleDAGMutation step in order. This allows different
392 /// instances of ScheduleDAGMI to perform custom DAG postprocessing.
393 void postprocessDAG();
395 /// Release ExitSU predecessors and setup scheduler queues.
396 void initQueues(ArrayRef<SUnit*> TopRoots, ArrayRef<SUnit*> BotRoots);
398 /// Move an instruction and update register pressure.
399 void scheduleMI(SUnit *SU, bool IsTopNode);
401 /// Update scheduler DAG and queues after scheduling an instruction.
402 void updateQueues(SUnit *SU, bool IsTopNode);
404 /// Reinsert debug_values recorded in ScheduleDAGInstrs::DbgValues.
405 void placeDebugValues();
407 /// \brief dump the scheduled Sequence.
408 void dumpSchedule() const;
412 void initRegPressure();
414 void updatePressureDiffs(ArrayRef<unsigned> LiveUses);
416 void updateScheduledPressure(const std::vector<unsigned> &NewMaxPressure);
418 bool checkSchedLimit();
420 void findRootsAndBiasEdges(SmallVectorImpl<SUnit*> &TopRoots,
421 SmallVectorImpl<SUnit*> &BotRoots);
423 void releaseSucc(SUnit *SU, SDep *SuccEdge);
424 void releaseSuccessors(SUnit *SU);
425 void releasePred(SUnit *SU, SDep *PredEdge);
426 void releasePredecessors(SUnit *SU);