1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "llvm/CodeGen/MachineInstrBundle.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/IndexedMap.h"
25 /// MachineRegisterInfo - Keep track of information for virtual and physical
26 /// registers, including vreg register classes, use/def chains for registers,
28 class MachineRegisterInfo {
29 const TargetRegisterInfo *const TRI;
31 /// IsSSA - True when the machine function is in SSA form and virtual
32 /// registers have a single def.
35 /// TracksLiveness - True while register liveness is being tracked accurately.
36 /// Basic block live-in lists, kill flags, and implicit defs may not be
37 /// accurate when after this flag is cleared.
40 /// VRegInfo - Information we keep for each virtual register.
42 /// Each element in this list contains the register class of the vreg and the
43 /// start of the use/def list for the register.
44 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>,
45 VirtReg2IndexFunctor> VRegInfo;
47 /// RegAllocHints - This vector records register allocation hints for virtual
48 /// registers. For each virtual register, it keeps a register and hint type
49 /// pair making up the allocation hint. Hint type is target specific except
50 /// for the value 0 which means the second value of the pair is the preferred
51 /// register for allocation. For example, if the hint is <0, 1024>, it means
52 /// the allocator should prefer the physical register allocated to the virtual
53 /// register of the hint.
54 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints;
56 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
57 /// physical registers.
58 MachineOperand **PhysRegUseDefLists;
60 /// getRegUseDefListHead - Return the head pointer for the register use/def
61 /// list for the specified virtual or physical register.
62 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
63 if (TargetRegisterInfo::isVirtualRegister(RegNo))
64 return VRegInfo[RegNo].second;
65 return PhysRegUseDefLists[RegNo];
68 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
69 if (TargetRegisterInfo::isVirtualRegister(RegNo))
70 return VRegInfo[RegNo].second;
71 return PhysRegUseDefLists[RegNo];
74 /// Get the next element in the use-def chain.
75 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
76 assert(MO && MO->isReg() && "This is not a register operand!");
77 return MO->Contents.Reg.Next;
80 /// UsedPhysRegs - This is a bit vector that is computed and set by the
81 /// register allocator, and must be kept up to date by passes that run after
82 /// register allocation (though most don't modify this). This is used
83 /// so that the code generator knows which callee save registers to save and
84 /// for other target specific uses.
85 /// This vector only has bits set for registers explicitly used, not their
87 BitVector UsedPhysRegs;
89 /// UsedPhysRegMask - Additional used physregs, but including aliases.
90 BitVector UsedPhysRegMask;
92 /// ReservedRegs - This is a bit vector of reserved registers. The target
93 /// may change its mind about which registers should be reserved. This
94 /// vector is the frozen set of reserved registers when register allocation
96 BitVector ReservedRegs;
98 /// LiveIns/LiveOuts - Keep track of the physical registers that are
99 /// livein/liveout of the function. Live in values are typically arguments in
100 /// registers, live out values are typically return values in registers.
101 /// LiveIn values are allowed to have virtual registers associated with them,
102 /// stored in the second element.
103 std::vector<std::pair<unsigned, unsigned> > LiveIns;
104 std::vector<unsigned> LiveOuts;
106 MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
107 void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
109 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);
110 ~MachineRegisterInfo();
112 //===--------------------------------------------------------------------===//
114 //===--------------------------------------------------------------------===//
116 // isSSA - Returns true when the machine function is in SSA form. Early
117 // passes require the machine function to be in SSA form where every virtual
118 // register has a single defining instruction.
120 // The TwoAddressInstructionPass and PHIElimination passes take the machine
121 // function out of SSA form when they introduce multiple defs per virtual
123 bool isSSA() const { return IsSSA; }
125 // leaveSSA - Indicates that the machine function is no longer in SSA form.
126 void leaveSSA() { IsSSA = false; }
128 /// tracksLiveness - Returns true when tracking register liveness accurately.
130 /// While this flag is true, register liveness information in basic block
131 /// live-in lists and machine instruction operands is accurate. This means it
132 /// can be used to change the code in ways that affect the values in
133 /// registers, for example by the register scavenger.
135 /// When this flag is false, liveness is no longer reliable.
136 bool tracksLiveness() const { return TracksLiveness; }
138 /// invalidateLiveness - Indicates that register liveness is no longer being
139 /// tracked accurately.
141 /// This should be called by late passes that invalidate the liveness
143 void invalidateLiveness() { TracksLiveness = false; }
145 //===--------------------------------------------------------------------===//
147 //===--------------------------------------------------------------------===//
149 // Strictly for use by MachineInstr.cpp.
150 void addRegOperandToUseList(MachineOperand *MO);
152 // Strictly for use by MachineInstr.cpp.
153 void removeRegOperandFromUseList(MachineOperand *MO);
155 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
156 /// and uses of a register within the MachineFunction that corresponds to this
157 /// MachineRegisterInfo object.
158 template<bool Uses, bool Defs, bool SkipDebug>
159 class defusechain_iterator;
161 // Make it a friend so it can access getNextOperandForReg().
162 template<bool, bool, bool> friend class defusechain_iterator;
164 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
166 typedef defusechain_iterator<true,true,false> reg_iterator;
167 reg_iterator reg_begin(unsigned RegNo) const {
168 return reg_iterator(getRegUseDefListHead(RegNo));
170 static reg_iterator reg_end() { return reg_iterator(0); }
172 /// reg_empty - Return true if there are no instructions using or defining the
173 /// specified register (it may be live-in).
174 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
176 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
177 /// of the specified register, skipping those marked as Debug.
178 typedef defusechain_iterator<true,true,true> reg_nodbg_iterator;
179 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
180 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
182 static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); }
184 /// reg_nodbg_empty - Return true if the only instructions using or defining
185 /// Reg are Debug instructions.
186 bool reg_nodbg_empty(unsigned RegNo) const {
187 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
190 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
191 typedef defusechain_iterator<false,true,false> def_iterator;
192 def_iterator def_begin(unsigned RegNo) const {
193 return def_iterator(getRegUseDefListHead(RegNo));
195 static def_iterator def_end() { return def_iterator(0); }
197 /// def_empty - Return true if there are no instructions defining the
198 /// specified register (it may be live-in).
199 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
201 /// hasOneDef - Return true if there is exactly one instruction defining the
202 /// specified register.
203 bool hasOneDef(unsigned RegNo) const {
204 def_iterator DI = def_begin(RegNo);
207 return ++DI == def_end();
210 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
211 typedef defusechain_iterator<true,false,false> use_iterator;
212 use_iterator use_begin(unsigned RegNo) const {
213 return use_iterator(getRegUseDefListHead(RegNo));
215 static use_iterator use_end() { return use_iterator(0); }
217 /// use_empty - Return true if there are no instructions using the specified
219 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
221 /// hasOneUse - Return true if there is exactly one instruction using the
222 /// specified register.
223 bool hasOneUse(unsigned RegNo) const {
224 use_iterator UI = use_begin(RegNo);
227 return ++UI == use_end();
230 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
231 /// specified register, skipping those marked as Debug.
232 typedef defusechain_iterator<true,false,true> use_nodbg_iterator;
233 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
234 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
236 static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); }
238 /// use_nodbg_empty - Return true if there are no non-Debug instructions
239 /// using the specified register.
240 bool use_nodbg_empty(unsigned RegNo) const {
241 return use_nodbg_begin(RegNo) == use_nodbg_end();
244 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
245 /// instruction using the specified register.
246 bool hasOneNonDBGUse(unsigned RegNo) const;
248 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
249 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
250 /// except that it also changes any definitions of the register as well.
252 /// Note that it is usually necessary to first constrain ToReg's register
253 /// class to match the FromReg constraints using:
255 /// constrainRegClass(ToReg, getRegClass(FromReg))
257 /// That function will return NULL if the virtual registers have incompatible
259 void replaceRegWith(unsigned FromReg, unsigned ToReg);
261 /// getVRegDef - Return the machine instr that defines the specified virtual
262 /// register or null if none is found. This assumes that the code is in SSA
263 /// form, so there should only be one definition.
264 MachineInstr *getVRegDef(unsigned Reg) const;
266 /// getUniqueVRegDef - Return the unique machine instr that defines the
267 /// specified virtual register or null if none is found. If there are
268 /// multiple definitions or no definition, return null.
269 MachineInstr *getUniqueVRegDef(unsigned Reg) const;
271 /// clearKillFlags - Iterate over all the uses of the given register and
272 /// clear the kill flag from the MachineOperand. This function is used by
273 /// optimization passes which extend register lifetimes and need only
274 /// preserve conservative kill flag information.
275 void clearKillFlags(unsigned Reg) const;
278 void dumpUses(unsigned RegNo) const;
281 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
282 /// throughout the function. It is safe to move instructions that read such
284 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
286 //===--------------------------------------------------------------------===//
287 // Virtual Register Info
288 //===--------------------------------------------------------------------===//
290 /// getRegClass - Return the register class of the specified virtual register.
292 const TargetRegisterClass *getRegClass(unsigned Reg) const {
293 return VRegInfo[Reg].first;
296 /// setRegClass - Set the register class of the specified virtual register.
298 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
300 /// constrainRegClass - Constrain the register class of the specified virtual
301 /// register to be a common subclass of RC and the current register class,
302 /// but only if the new class has at least MinNumRegs registers. Return the
303 /// new register class, or NULL if no such class exists.
304 /// This should only be used when the constraint is known to be trivial, like
305 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
307 const TargetRegisterClass *constrainRegClass(unsigned Reg,
308 const TargetRegisterClass *RC,
309 unsigned MinNumRegs = 0);
311 /// recomputeRegClass - Try to find a legal super-class of Reg's register
312 /// class that still satisfies the constraints from the instructions using
313 /// Reg. Returns true if Reg was upgraded.
315 /// This method can be used after constraints have been removed from a
316 /// virtual register, for example after removing instructions or splitting
319 bool recomputeRegClass(unsigned Reg, const TargetMachine&);
321 /// createVirtualRegister - Create and return a new virtual register in the
322 /// function with the specified register class.
324 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
326 /// getNumVirtRegs - Return the number of virtual registers created.
328 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
330 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
331 void clearVirtRegs();
333 /// setRegAllocationHint - Specify a register allocation hint for the
334 /// specified virtual register.
335 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
336 RegAllocHints[Reg].first = Type;
337 RegAllocHints[Reg].second = PrefReg;
340 /// getRegAllocationHint - Return the register allocation hint for the
341 /// specified virtual register.
342 std::pair<unsigned, unsigned>
343 getRegAllocationHint(unsigned Reg) const {
344 return RegAllocHints[Reg];
347 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
348 /// standard simple hint (Type == 0) is not set.
349 unsigned getSimpleHint(unsigned Reg) const {
350 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg);
351 return Hint.first ? 0 : Hint.second;
355 //===--------------------------------------------------------------------===//
356 // Physical Register Use Info
357 //===--------------------------------------------------------------------===//
359 /// isPhysRegUsed - Return true if the specified register is used in this
360 /// function. This only works after register allocation.
361 bool isPhysRegUsed(unsigned Reg) const {
362 return UsedPhysRegs.test(Reg) || UsedPhysRegMask.test(Reg);
365 /// isPhysRegOrOverlapUsed - Return true if Reg or any overlapping register
366 /// is used in this function.
367 bool isPhysRegOrOverlapUsed(unsigned Reg) const {
368 if (UsedPhysRegMask.test(Reg))
370 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
371 if (UsedPhysRegs.test(*AI))
376 /// setPhysRegUsed - Mark the specified register used in this function.
377 /// This should only be called during and after register allocation.
378 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs.set(Reg); }
380 /// addPhysRegsUsed - Mark the specified registers used in this function.
381 /// This should only be called during and after register allocation.
382 void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; }
384 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
385 /// This corresponds to the bit mask attached to register mask operands.
386 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
387 UsedPhysRegMask.setBitsNotInMask(RegMask);
390 /// setPhysRegUnused - Mark the specified register unused in this function.
391 /// This should only be called during and after register allocation.
392 void setPhysRegUnused(unsigned Reg) {
393 UsedPhysRegs.reset(Reg);
394 UsedPhysRegMask.reset(Reg);
398 //===--------------------------------------------------------------------===//
399 // Reserved Register Info
400 //===--------------------------------------------------------------------===//
402 // The set of reserved registers must be invariant during register
403 // allocation. For example, the target cannot suddenly decide it needs a
404 // frame pointer when the register allocator has already used the frame
405 // pointer register for something else.
407 // These methods can be used by target hooks like hasFP() to avoid changing
408 // the reserved register set during register allocation.
410 /// freezeReservedRegs - Called by the register allocator to freeze the set
411 /// of reserved registers before allocation begins.
412 void freezeReservedRegs(const MachineFunction&);
414 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
415 /// to ensure the set of reserved registers stays constant.
416 bool reservedRegsFrozen() const {
417 return !ReservedRegs.empty();
420 /// canReserveReg - Returns true if PhysReg can be used as a reserved
421 /// register. Any register can be reserved before freezeReservedRegs() is
423 bool canReserveReg(unsigned PhysReg) const {
424 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
427 /// getReservedRegs - Returns a reference to the frozen set of reserved
428 /// registers. This method should always be preferred to calling
429 /// TRI::getReservedRegs() when possible.
430 const BitVector &getReservedRegs() const {
431 assert(reservedRegsFrozen() &&
432 "Reserved registers haven't been frozen yet. "
433 "Use TRI::getReservedRegs().");
437 /// isReserved - Returns true when PhysReg is a reserved register.
439 /// Reserved registers may belong to an allocatable register class, but the
440 /// target has explicitly requested that they are not used.
442 bool isReserved(unsigned PhysReg) const {
443 return getReservedRegs().test(PhysReg);
446 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
447 /// register class and it hasn't been reserved.
449 /// Allocatable registers may show up in the allocation order of some virtual
450 /// register, so a register allocator needs to track its liveness and
452 bool isAllocatable(unsigned PhysReg) const {
453 return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg);
456 //===--------------------------------------------------------------------===//
457 // LiveIn/LiveOut Management
458 //===--------------------------------------------------------------------===//
460 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it
461 /// is an error to add the same register to the same set more than once.
462 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
463 LiveIns.push_back(std::make_pair(Reg, vreg));
465 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
467 // Iteration support for live in/out sets. These sets are kept in sorted
468 // order by their register number.
469 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
471 typedef std::vector<unsigned>::const_iterator liveout_iterator;
472 livein_iterator livein_begin() const { return LiveIns.begin(); }
473 livein_iterator livein_end() const { return LiveIns.end(); }
474 bool livein_empty() const { return LiveIns.empty(); }
475 liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
476 liveout_iterator liveout_end() const { return LiveOuts.end(); }
477 bool liveout_empty() const { return LiveOuts.empty(); }
479 bool isLiveIn(unsigned Reg) const;
480 bool isLiveOut(unsigned Reg) const;
482 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
483 /// corresponding live-in physical register.
484 unsigned getLiveInPhysReg(unsigned VReg) const;
486 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
487 /// corresponding live-in physical register.
488 unsigned getLiveInVirtReg(unsigned PReg) const;
490 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
491 /// into the given entry block.
492 void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
493 const TargetRegisterInfo &TRI,
494 const TargetInstrInfo &TII);
496 /// defusechain_iterator - This class provides iterator support for machine
497 /// operands in the function that use or define a specific register. If
498 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
499 /// returns defs. If neither are true then you are silly and it always
500 /// returns end(). If SkipDebug is true it skips uses marked Debug
501 /// when incrementing.
502 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug>
503 class defusechain_iterator
504 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
506 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
507 // If the first node isn't one we're interested in, advance to one that
508 // we are interested in.
510 if ((!ReturnUses && op->isUse()) ||
511 (!ReturnDefs && op->isDef()) ||
512 (SkipDebug && op->isDebug()))
516 friend class MachineRegisterInfo;
518 typedef std::iterator<std::forward_iterator_tag,
519 MachineInstr, ptrdiff_t>::reference reference;
520 typedef std::iterator<std::forward_iterator_tag,
521 MachineInstr, ptrdiff_t>::pointer pointer;
523 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
524 defusechain_iterator() : Op(0) {}
526 bool operator==(const defusechain_iterator &x) const {
529 bool operator!=(const defusechain_iterator &x) const {
530 return !operator==(x);
533 /// atEnd - return true if this iterator is equal to reg_end() on the value.
534 bool atEnd() const { return Op == 0; }
536 // Iterator traversal: forward iteration only
537 defusechain_iterator &operator++() { // Preincrement
538 assert(Op && "Cannot increment end iterator!");
539 Op = getNextOperandForReg(Op);
541 // All defs come before the uses, so stop def_iterator early.
547 assert(!Op->isDebug() && "Can't have debug defs");
550 // If this is an operand we don't care about, skip it.
551 while (Op && ((!ReturnDefs && Op->isDef()) ||
552 (SkipDebug && Op->isDebug())))
553 Op = getNextOperandForReg(Op);
558 defusechain_iterator operator++(int) { // Postincrement
559 defusechain_iterator tmp = *this; ++*this; return tmp;
562 /// skipInstruction - move forward until reaching a different instruction.
563 /// Return the skipped instruction that is no longer pointed to, or NULL if
564 /// already pointing to end().
565 MachineInstr *skipInstruction() {
567 MachineInstr *MI = Op->getParent();
569 while (Op && Op->getParent() == MI);
573 MachineInstr *skipBundle() {
575 MachineInstr *MI = getBundleStart(Op->getParent());
577 while (Op && getBundleStart(Op->getParent()) == MI);
581 MachineOperand &getOperand() const {
582 assert(Op && "Cannot dereference end iterator!");
586 /// getOperandNo - Return the operand # of this MachineOperand in its
588 unsigned getOperandNo() const {
589 assert(Op && "Cannot dereference end iterator!");
590 return Op - &Op->getParent()->getOperand(0);
593 // Retrieve a reference to the current operand.
594 MachineInstr &operator*() const {
595 assert(Op && "Cannot dereference end iterator!");
596 return *Op->getParent();
599 MachineInstr *operator->() const {
600 assert(Op && "Cannot dereference end iterator!");
601 return Op->getParent();
607 } // End llvm namespace