1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/iterator"
24 /// MachineRegisterInfo - Keep track of information for virtual and physical
25 /// registers, including vreg register classes, use/def chains for registers,
27 class MachineRegisterInfo {
28 /// VRegInfo - Information we keep for each virtual register. The entries in
29 /// this vector are actually converted to vreg numbers by adding the
30 /// TargetRegisterInfo::FirstVirtualRegister delta to their index.
32 /// Each element in this list contains the register class of the vreg and the
33 /// start of the use/def list for the register.
34 std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo;
36 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
37 /// physical registers.
38 MachineOperand **PhysRegUseDefLists;
40 /// UsedPhysRegs - This is a bit vector that is computed and set by the
41 /// register allocator, and must be kept up to date by passes that run after
42 /// register allocation (though most don't modify this). This is used
43 /// so that the code generator knows which callee save registers to save and
44 /// for other target specific uses.
45 BitVector UsedPhysRegs;
47 /// LiveIns/LiveOuts - Keep track of the physical registers that are
48 /// livein/liveout of the function. Live in values are typically arguments in
49 /// registers, live out values are typically return values in registers.
50 /// LiveIn values are allowed to have virtual registers associated with them,
51 /// stored in the second element.
52 std::vector<std::pair<unsigned, unsigned> > LiveIns;
53 std::vector<unsigned> LiveOuts;
55 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT
56 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT
58 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);
59 ~MachineRegisterInfo();
61 //===--------------------------------------------------------------------===//
63 //===--------------------------------------------------------------------===//
65 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
66 /// and uses of a register within the MachineFunction that corresponds to this
67 /// MachineRegisterInfo object.
68 template<bool Uses, bool Defs>
69 class defusechain_iterator;
71 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
73 typedef defusechain_iterator<true,true> reg_iterator;
74 reg_iterator reg_begin(unsigned RegNo) const {
75 return reg_iterator(getRegUseDefListHead(RegNo));
77 static reg_iterator reg_end() { return reg_iterator(0); }
79 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
80 typedef defusechain_iterator<false,true> def_iterator;
81 def_iterator def_begin(unsigned RegNo) const {
82 return def_iterator(getRegUseDefListHead(RegNo));
84 static def_iterator def_end() { return def_iterator(0); }
86 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
87 typedef defusechain_iterator<true,false> use_iterator;
88 use_iterator use_begin(unsigned RegNo) const {
89 return use_iterator(getRegUseDefListHead(RegNo));
91 static use_iterator use_end() { return use_iterator(0); }
94 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
95 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
96 /// except that it also changes any definitions of the register as well.
97 void replaceRegWith(unsigned FromReg, unsigned ToReg);
99 /// getRegUseDefListHead - Return the head pointer for the register use/def
100 /// list for the specified virtual or physical register.
101 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
102 if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
103 return PhysRegUseDefLists[RegNo];
104 RegNo -= TargetRegisterInfo::FirstVirtualRegister;
105 return VRegInfo[RegNo].second;
108 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
109 if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
110 return PhysRegUseDefLists[RegNo];
111 RegNo -= TargetRegisterInfo::FirstVirtualRegister;
112 return VRegInfo[RegNo].second;
115 /// getVRegDef - Return the machine instr that defines the specified virtual
116 /// register or null if none is found. This assumes that the code is in SSA
117 /// form, so there should only be one definition.
118 MachineInstr *getVRegDef(unsigned Reg) const;
121 void dumpUses(unsigned RegNo) const;
124 //===--------------------------------------------------------------------===//
125 // Virtual Register Info
126 //===--------------------------------------------------------------------===//
128 /// getRegClass - Return the register class of the specified virtual register.
129 const TargetRegisterClass *getRegClass(unsigned Reg) const {
130 Reg -= TargetRegisterInfo::FirstVirtualRegister;
131 assert(Reg < VRegInfo.size() && "Invalid vreg!");
132 return VRegInfo[Reg].first;
135 /// createVirtualRegister - Create and return a new virtual register in the
136 /// function with the specified register class.
138 unsigned createVirtualRegister(const TargetRegisterClass *RegClass) {
139 assert(RegClass && "Cannot create register without RegClass!");
140 // Add a reg, but keep track of whether the vector reallocated or not.
141 void *ArrayBase = VRegInfo.empty() ? 0 : &VRegInfo[0];
142 VRegInfo.push_back(std::make_pair(RegClass, (MachineOperand*)0));
144 if (&VRegInfo[0] == ArrayBase || VRegInfo.size() == 1)
145 return getLastVirtReg();
147 // Otherwise, the vector reallocated, handle this now.
148 HandleVRegListReallocation();
149 return getLastVirtReg();
152 /// getLastVirtReg - Return the highest currently assigned virtual register.
154 unsigned getLastVirtReg() const {
155 return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1;
159 //===--------------------------------------------------------------------===//
160 // Physical Register Use Info
161 //===--------------------------------------------------------------------===//
163 /// isPhysRegUsed - Return true if the specified register is used in this
164 /// function. This only works after register allocation.
165 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; }
167 /// setPhysRegUsed - Mark the specified register used in this function.
168 /// This should only be called during and after register allocation.
169 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; }
171 /// setPhysRegUnused - Mark the specified register unused in this function.
172 /// This should only be called during and after register allocation.
173 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; }
176 //===--------------------------------------------------------------------===//
177 // LiveIn/LiveOut Management
178 //===--------------------------------------------------------------------===//
180 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it
181 /// is an error to add the same register to the same set more than once.
182 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
183 LiveIns.push_back(std::make_pair(Reg, vreg));
185 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
187 // Iteration support for live in/out sets. These sets are kept in sorted
188 // order by their register number.
189 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
191 typedef std::vector<unsigned>::const_iterator liveout_iterator;
192 livein_iterator livein_begin() const { return LiveIns.begin(); }
193 livein_iterator livein_end() const { return LiveIns.end(); }
194 bool livein_empty() const { return LiveIns.empty(); }
195 liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
196 liveout_iterator liveout_end() const { return LiveOuts.end(); }
197 bool liveout_empty() const { return LiveOuts.empty(); }
199 void HandleVRegListReallocation();
202 /// defusechain_iterator - This class provides iterator support for machine
203 /// operands in the function that use or define a specific register. If
204 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
205 /// returns defs. If neither are true then you are silly and it always
207 template<bool ReturnUses, bool ReturnDefs>
208 class defusechain_iterator
209 : public forward_iterator<MachineInstr, ptrdiff_t> {
211 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
212 // If the first node isn't one we're interested in, advance to one that
213 // we are interested in.
215 if ((!ReturnUses && op->isUse()) ||
216 (!ReturnDefs && op->isDef()))
220 friend class MachineRegisterInfo;
222 typedef forward_iterator<MachineInstr, ptrdiff_t>::reference reference;
223 typedef forward_iterator<MachineInstr, ptrdiff_t>::pointer pointer;
225 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
226 defusechain_iterator() : Op(0) {}
228 bool operator==(const defusechain_iterator &x) const {
231 bool operator!=(const defusechain_iterator &x) const {
232 return !operator==(x);
235 /// atEnd - return true if this iterator is equal to reg_end() on the value.
236 bool atEnd() const { return Op == 0; }
238 // Iterator traversal: forward iteration only
239 defusechain_iterator &operator++() { // Preincrement
240 assert(Op && "Cannot increment end iterator!");
241 Op = Op->getNextOperandForReg();
243 // If this is an operand we don't care about, skip it.
244 while (Op && ((!ReturnUses && Op->isUse()) ||
245 (!ReturnDefs && Op->isDef())))
246 Op = Op->getNextOperandForReg();
250 defusechain_iterator operator++(int) { // Postincrement
251 defusechain_iterator tmp = *this; ++*this; return tmp;
254 MachineOperand &getOperand() const {
255 assert(Op && "Cannot dereference end iterator!");
259 /// getOperandNo - Return the operand # of this MachineOperand in its
261 unsigned getOperandNo() const {
262 assert(Op && "Cannot dereference end iterator!");
263 return Op - &Op->getParent()->getOperand(0);
266 // Retrieve a reference to the current operand.
267 MachineInstr &operator*() const {
268 assert(Op && "Cannot dereference end iterator!");
269 return *Op->getParent();
272 MachineInstr *operator->() const {
273 assert(Op && "Cannot dereference end iterator!");
274 return Op->getParent();
280 } // End llvm namespace