1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "llvm/CodeGen/MachineInstrBundle.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/IndexedMap.h"
25 /// MachineRegisterInfo - Keep track of information for virtual and physical
26 /// registers, including vreg register classes, use/def chains for registers,
28 class MachineRegisterInfo {
29 const TargetRegisterInfo *const TRI;
31 /// IsSSA - True when the machine function is in SSA form and virtual
32 /// registers have a single def.
35 /// TracksLiveness - True while register liveness is being tracked accurately.
36 /// Basic block live-in lists, kill flags, and implicit defs may not be
37 /// accurate when after this flag is cleared.
40 /// VRegInfo - Information we keep for each virtual register.
42 /// Each element in this list contains the register class of the vreg and the
43 /// start of the use/def list for the register.
44 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>,
45 VirtReg2IndexFunctor> VRegInfo;
47 /// RegAllocHints - This vector records register allocation hints for virtual
48 /// registers. For each virtual register, it keeps a register and hint type
49 /// pair making up the allocation hint. Hint type is target specific except
50 /// for the value 0 which means the second value of the pair is the preferred
51 /// register for allocation. For example, if the hint is <0, 1024>, it means
52 /// the allocator should prefer the physical register allocated to the virtual
53 /// register of the hint.
54 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints;
56 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
57 /// physical registers.
58 MachineOperand **PhysRegUseDefLists;
60 /// Get the next element in the use-def chain.
61 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
62 assert(MO && MO->isReg() && "This is not a register operand!");
63 return MO->Contents.Reg.Next;
66 /// UsedPhysRegs - This is a bit vector that is computed and set by the
67 /// register allocator, and must be kept up to date by passes that run after
68 /// register allocation (though most don't modify this). This is used
69 /// so that the code generator knows which callee save registers to save and
70 /// for other target specific uses.
71 /// This vector only has bits set for registers explicitly used, not their
73 BitVector UsedPhysRegs;
75 /// UsedPhysRegMask - Additional used physregs, but including aliases.
76 BitVector UsedPhysRegMask;
78 /// ReservedRegs - This is a bit vector of reserved registers. The target
79 /// may change its mind about which registers should be reserved. This
80 /// vector is the frozen set of reserved registers when register allocation
82 BitVector ReservedRegs;
84 /// AllocatableRegs - From TRI->getAllocatableSet.
85 mutable BitVector AllocatableRegs;
87 /// LiveIns/LiveOuts - Keep track of the physical registers that are
88 /// livein/liveout of the function. Live in values are typically arguments in
89 /// registers, live out values are typically return values in registers.
90 /// LiveIn values are allowed to have virtual registers associated with them,
91 /// stored in the second element.
92 std::vector<std::pair<unsigned, unsigned> > LiveIns;
93 std::vector<unsigned> LiveOuts;
95 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT
96 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT
98 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);
99 ~MachineRegisterInfo();
101 //===--------------------------------------------------------------------===//
103 //===--------------------------------------------------------------------===//
105 // isSSA - Returns true when the machine function is in SSA form. Early
106 // passes require the machine function to be in SSA form where every virtual
107 // register has a single defining instruction.
109 // The TwoAddressInstructionPass and PHIElimination passes take the machine
110 // function out of SSA form when they introduce multiple defs per virtual
112 bool isSSA() const { return IsSSA; }
114 // leaveSSA - Indicates that the machine function is no longer in SSA form.
115 void leaveSSA() { IsSSA = false; }
117 /// tracksLiveness - Returns true when tracking register liveness accurately.
119 /// While this flag is true, register liveness information in basic block
120 /// live-in lists and machine instruction operands is accurate. This means it
121 /// can be used to change the code in ways that affect the values in
122 /// registers, for example by the register scavenger.
124 /// When this flag is false, liveness is no longer reliable.
125 bool tracksLiveness() const { return TracksLiveness; }
127 /// invalidateLiveness - Indicates that register liveness is no longer being
128 /// tracked accurately.
130 /// This should be called by late passes that invalidate the liveness
132 void invalidateLiveness() { TracksLiveness = false; }
134 //===--------------------------------------------------------------------===//
136 //===--------------------------------------------------------------------===//
138 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
139 /// and uses of a register within the MachineFunction that corresponds to this
140 /// MachineRegisterInfo object.
141 template<bool Uses, bool Defs, bool SkipDebug>
142 class defusechain_iterator;
144 // Make it a friend so it can access getNextOperandForReg().
145 template<bool, bool, bool> friend class defusechain_iterator;
147 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
149 typedef defusechain_iterator<true,true,false> reg_iterator;
150 reg_iterator reg_begin(unsigned RegNo) const {
151 return reg_iterator(getRegUseDefListHead(RegNo));
153 static reg_iterator reg_end() { return reg_iterator(0); }
155 /// reg_empty - Return true if there are no instructions using or defining the
156 /// specified register (it may be live-in).
157 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
159 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
160 /// of the specified register, skipping those marked as Debug.
161 typedef defusechain_iterator<true,true,true> reg_nodbg_iterator;
162 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
163 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
165 static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); }
167 /// reg_nodbg_empty - Return true if the only instructions using or defining
168 /// Reg are Debug instructions.
169 bool reg_nodbg_empty(unsigned RegNo) const {
170 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
173 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
174 typedef defusechain_iterator<false,true,false> def_iterator;
175 def_iterator def_begin(unsigned RegNo) const {
176 return def_iterator(getRegUseDefListHead(RegNo));
178 static def_iterator def_end() { return def_iterator(0); }
180 /// def_empty - Return true if there are no instructions defining the
181 /// specified register (it may be live-in).
182 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
184 /// hasOneDef - Return true if there is exactly one instruction defining the
185 /// specified register.
186 bool hasOneDef(unsigned RegNo) const {
187 def_iterator DI = def_begin(RegNo);
190 return ++DI == def_end();
193 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
194 typedef defusechain_iterator<true,false,false> use_iterator;
195 use_iterator use_begin(unsigned RegNo) const {
196 return use_iterator(getRegUseDefListHead(RegNo));
198 static use_iterator use_end() { return use_iterator(0); }
200 /// use_empty - Return true if there are no instructions using the specified
202 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
204 /// hasOneUse - Return true if there is exactly one instruction using the
205 /// specified register.
206 bool hasOneUse(unsigned RegNo) const {
207 use_iterator UI = use_begin(RegNo);
210 return ++UI == use_end();
213 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
214 /// specified register, skipping those marked as Debug.
215 typedef defusechain_iterator<true,false,true> use_nodbg_iterator;
216 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
217 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
219 static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); }
221 /// use_nodbg_empty - Return true if there are no non-Debug instructions
222 /// using the specified register.
223 bool use_nodbg_empty(unsigned RegNo) const {
224 return use_nodbg_begin(RegNo) == use_nodbg_end();
227 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
228 /// instruction using the specified register.
229 bool hasOneNonDBGUse(unsigned RegNo) const;
231 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
232 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
233 /// except that it also changes any definitions of the register as well.
235 /// Note that it is usually necessary to first constrain ToReg's register
236 /// class to match the FromReg constraints using:
238 /// constrainRegClass(ToReg, getRegClass(FromReg))
240 /// That function will return NULL if the virtual registers have incompatible
242 void replaceRegWith(unsigned FromReg, unsigned ToReg);
244 /// getRegUseDefListHead - Return the head pointer for the register use/def
245 /// list for the specified virtual or physical register.
246 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
247 if (TargetRegisterInfo::isVirtualRegister(RegNo))
248 return VRegInfo[RegNo].second;
249 return PhysRegUseDefLists[RegNo];
252 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
253 if (TargetRegisterInfo::isVirtualRegister(RegNo))
254 return VRegInfo[RegNo].second;
255 return PhysRegUseDefLists[RegNo];
258 /// getVRegDef - Return the machine instr that defines the specified virtual
259 /// register or null if none is found. This assumes that the code is in SSA
260 /// form, so there should only be one definition.
261 MachineInstr *getVRegDef(unsigned Reg) const;
263 /// getUniqueVRegDef - Return the unique machine instr that defines the
264 /// specified virtual register or null if none is found. If there are
265 /// multiple definitions or no definition, return null.
266 MachineInstr *getUniqueVRegDef(unsigned Reg) const;
268 /// clearKillFlags - Iterate over all the uses of the given register and
269 /// clear the kill flag from the MachineOperand. This function is used by
270 /// optimization passes which extend register lifetimes and need only
271 /// preserve conservative kill flag information.
272 void clearKillFlags(unsigned Reg) const;
275 void dumpUses(unsigned RegNo) const;
278 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
279 /// throughout the function. It is safe to move instructions that read such
281 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
283 //===--------------------------------------------------------------------===//
284 // Virtual Register Info
285 //===--------------------------------------------------------------------===//
287 /// getRegClass - Return the register class of the specified virtual register.
289 const TargetRegisterClass *getRegClass(unsigned Reg) const {
290 return VRegInfo[Reg].first;
293 /// setRegClass - Set the register class of the specified virtual register.
295 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
297 /// constrainRegClass - Constrain the register class of the specified virtual
298 /// register to be a common subclass of RC and the current register class,
299 /// but only if the new class has at least MinNumRegs registers. Return the
300 /// new register class, or NULL if no such class exists.
301 /// This should only be used when the constraint is known to be trivial, like
302 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
304 const TargetRegisterClass *constrainRegClass(unsigned Reg,
305 const TargetRegisterClass *RC,
306 unsigned MinNumRegs = 0);
308 /// recomputeRegClass - Try to find a legal super-class of Reg's register
309 /// class that still satisfies the constraints from the instructions using
310 /// Reg. Returns true if Reg was upgraded.
312 /// This method can be used after constraints have been removed from a
313 /// virtual register, for example after removing instructions or splitting
316 bool recomputeRegClass(unsigned Reg, const TargetMachine&);
318 /// createVirtualRegister - Create and return a new virtual register in the
319 /// function with the specified register class.
321 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
323 /// getNumVirtRegs - Return the number of virtual registers created.
325 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
327 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
328 void clearVirtRegs();
330 /// setRegAllocationHint - Specify a register allocation hint for the
331 /// specified virtual register.
332 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
333 RegAllocHints[Reg].first = Type;
334 RegAllocHints[Reg].second = PrefReg;
337 /// getRegAllocationHint - Return the register allocation hint for the
338 /// specified virtual register.
339 std::pair<unsigned, unsigned>
340 getRegAllocationHint(unsigned Reg) const {
341 return RegAllocHints[Reg];
344 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
345 /// standard simple hint (Type == 0) is not set.
346 unsigned getSimpleHint(unsigned Reg) const {
347 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg);
348 return Hint.first ? 0 : Hint.second;
352 //===--------------------------------------------------------------------===//
353 // Physical Register Use Info
354 //===--------------------------------------------------------------------===//
356 /// isPhysRegUsed - Return true if the specified register is used in this
357 /// function. This only works after register allocation.
358 bool isPhysRegUsed(unsigned Reg) const {
359 return UsedPhysRegs.test(Reg) || UsedPhysRegMask.test(Reg);
362 /// isPhysRegOrOverlapUsed - Return true if Reg or any overlapping register
363 /// is used in this function.
364 bool isPhysRegOrOverlapUsed(unsigned Reg) const {
365 if (UsedPhysRegMask.test(Reg))
367 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
368 if (UsedPhysRegs.test(*AI))
373 /// setPhysRegUsed - Mark the specified register used in this function.
374 /// This should only be called during and after register allocation.
375 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs.set(Reg); }
377 /// addPhysRegsUsed - Mark the specified registers used in this function.
378 /// This should only be called during and after register allocation.
379 void addPhysRegsUsed(const BitVector &Regs) { UsedPhysRegs |= Regs; }
381 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
382 /// This corresponds to the bit mask attached to register mask operands.
383 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
384 UsedPhysRegMask.setBitsNotInMask(RegMask);
387 /// setPhysRegUnused - Mark the specified register unused in this function.
388 /// This should only be called during and after register allocation.
389 void setPhysRegUnused(unsigned Reg) {
390 UsedPhysRegs.reset(Reg);
391 UsedPhysRegMask.reset(Reg);
395 //===--------------------------------------------------------------------===//
396 // Reserved Register Info
397 //===--------------------------------------------------------------------===//
399 // The set of reserved registers must be invariant during register
400 // allocation. For example, the target cannot suddenly decide it needs a
401 // frame pointer when the register allocator has already used the frame
402 // pointer register for something else.
404 // These methods can be used by target hooks like hasFP() to avoid changing
405 // the reserved register set during register allocation.
407 /// freezeReservedRegs - Called by the register allocator to freeze the set
408 /// of reserved registers before allocation begins.
409 void freezeReservedRegs(const MachineFunction&);
411 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
412 /// to ensure the set of reserved registers stays constant.
413 bool reservedRegsFrozen() const {
414 return !ReservedRegs.empty();
417 /// canReserveReg - Returns true if PhysReg can be used as a reserved
418 /// register. Any register can be reserved before freezeReservedRegs() is
420 bool canReserveReg(unsigned PhysReg) const {
421 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
425 //===--------------------------------------------------------------------===//
426 // LiveIn/LiveOut Management
427 //===--------------------------------------------------------------------===//
429 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it
430 /// is an error to add the same register to the same set more than once.
431 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
432 LiveIns.push_back(std::make_pair(Reg, vreg));
434 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
436 // Iteration support for live in/out sets. These sets are kept in sorted
437 // order by their register number.
438 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
440 typedef std::vector<unsigned>::const_iterator liveout_iterator;
441 livein_iterator livein_begin() const { return LiveIns.begin(); }
442 livein_iterator livein_end() const { return LiveIns.end(); }
443 bool livein_empty() const { return LiveIns.empty(); }
444 liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
445 liveout_iterator liveout_end() const { return LiveOuts.end(); }
446 bool liveout_empty() const { return LiveOuts.empty(); }
448 bool isLiveIn(unsigned Reg) const;
449 bool isLiveOut(unsigned Reg) const;
451 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
452 /// corresponding live-in physical register.
453 unsigned getLiveInPhysReg(unsigned VReg) const;
455 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
456 /// corresponding live-in physical register.
457 unsigned getLiveInVirtReg(unsigned PReg) const;
459 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
460 /// into the given entry block.
461 void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
462 const TargetRegisterInfo &TRI,
463 const TargetInstrInfo &TII);
466 void HandleVRegListReallocation();
469 /// defusechain_iterator - This class provides iterator support for machine
470 /// operands in the function that use or define a specific register. If
471 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
472 /// returns defs. If neither are true then you are silly and it always
473 /// returns end(). If SkipDebug is true it skips uses marked Debug
474 /// when incrementing.
475 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug>
476 class defusechain_iterator
477 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
479 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
480 // If the first node isn't one we're interested in, advance to one that
481 // we are interested in.
483 if ((!ReturnUses && op->isUse()) ||
484 (!ReturnDefs && op->isDef()) ||
485 (SkipDebug && op->isDebug()))
489 friend class MachineRegisterInfo;
491 typedef std::iterator<std::forward_iterator_tag,
492 MachineInstr, ptrdiff_t>::reference reference;
493 typedef std::iterator<std::forward_iterator_tag,
494 MachineInstr, ptrdiff_t>::pointer pointer;
496 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
497 defusechain_iterator() : Op(0) {}
499 bool operator==(const defusechain_iterator &x) const {
502 bool operator!=(const defusechain_iterator &x) const {
503 return !operator==(x);
506 /// atEnd - return true if this iterator is equal to reg_end() on the value.
507 bool atEnd() const { return Op == 0; }
509 // Iterator traversal: forward iteration only
510 defusechain_iterator &operator++() { // Preincrement
511 assert(Op && "Cannot increment end iterator!");
512 Op = getNextOperandForReg(Op);
514 // If this is an operand we don't care about, skip it.
515 while (Op && ((!ReturnUses && Op->isUse()) ||
516 (!ReturnDefs && Op->isDef()) ||
517 (SkipDebug && Op->isDebug())))
518 Op = getNextOperandForReg(Op);
522 defusechain_iterator operator++(int) { // Postincrement
523 defusechain_iterator tmp = *this; ++*this; return tmp;
526 /// skipInstruction - move forward until reaching a different instruction.
527 /// Return the skipped instruction that is no longer pointed to, or NULL if
528 /// already pointing to end().
529 MachineInstr *skipInstruction() {
531 MachineInstr *MI = Op->getParent();
533 while (Op && Op->getParent() == MI);
537 MachineInstr *skipBundle() {
539 MachineInstr *MI = getBundleStart(Op->getParent());
541 while (Op && getBundleStart(Op->getParent()) == MI);
545 MachineOperand &getOperand() const {
546 assert(Op && "Cannot dereference end iterator!");
550 /// getOperandNo - Return the operand # of this MachineOperand in its
552 unsigned getOperandNo() const {
553 assert(Op && "Cannot dereference end iterator!");
554 return Op - &Op->getParent()->getOperand(0);
557 // Retrieve a reference to the current operand.
558 MachineInstr &operator*() const {
559 assert(Op && "Cannot dereference end iterator!");
560 return *Op->getParent();
563 MachineInstr *operator->() const {
564 assert(Op && "Cannot dereference end iterator!");
565 return Op->getParent();
571 } // End llvm namespace