1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/iterator.h"
24 /// MachineRegisterInfo - Keep track of information for virtual and physical
25 /// registers, including vreg register classes, use/def chains for registers,
27 class MachineRegisterInfo {
28 /// VRegInfo - Information we keep for each virtual register. The entries in
29 /// this vector are actually converted to vreg numbers by adding the
30 /// TargetRegisterInfo::FirstVirtualRegister delta to their index.
32 /// Each element in this list contains the register class of the vreg and the
33 /// start of the use/def list for the register.
34 std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo;
36 /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to
37 /// virtual registers. For each target register class, it keeps a list of
38 /// virtual registers belonging to the class.
39 std::vector<std::vector<unsigned> > RegClass2VRegMap;
41 /// RegAllocHints - This vector records register allocation hints for virtual
42 /// registers. For each virtual register, it keeps a register and hint type
43 /// pair making up the allocation hint. Hint type is target specific except
44 /// for the value 0 which means the second value of the pair is the preferred
45 /// register for allocation. For example, if the hint is <0, 1024>, it means
46 /// the allocator should prefer the physical register allocated to the virtual
47 /// register of the hint.
48 std::vector<std::pair<unsigned, unsigned> > RegAllocHints;
50 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
51 /// physical registers.
52 MachineOperand **PhysRegUseDefLists;
54 /// UsedPhysRegs - This is a bit vector that is computed and set by the
55 /// register allocator, and must be kept up to date by passes that run after
56 /// register allocation (though most don't modify this). This is used
57 /// so that the code generator knows which callee save registers to save and
58 /// for other target specific uses.
59 BitVector UsedPhysRegs;
61 /// LiveIns/LiveOuts - Keep track of the physical registers that are
62 /// livein/liveout of the function. Live in values are typically arguments in
63 /// registers, live out values are typically return values in registers.
64 /// LiveIn values are allowed to have virtual registers associated with them,
65 /// stored in the second element.
66 std::vector<std::pair<unsigned, unsigned> > LiveIns;
67 std::vector<unsigned> LiveOuts;
69 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT
70 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT
72 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);
73 ~MachineRegisterInfo();
75 //===--------------------------------------------------------------------===//
77 //===--------------------------------------------------------------------===//
79 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
80 /// and uses of a register within the MachineFunction that corresponds to this
81 /// MachineRegisterInfo object.
82 template<bool Uses, bool Defs>
83 class defusechain_iterator;
85 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
87 typedef defusechain_iterator<true,true> reg_iterator;
88 reg_iterator reg_begin(unsigned RegNo) const {
89 return reg_iterator(getRegUseDefListHead(RegNo));
91 static reg_iterator reg_end() { return reg_iterator(0); }
93 /// reg_empty - Return true if there are no instructions using or defining the
94 /// specified register (it may be live-in).
95 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
97 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
98 typedef defusechain_iterator<false,true> def_iterator;
99 def_iterator def_begin(unsigned RegNo) const {
100 return def_iterator(getRegUseDefListHead(RegNo));
102 static def_iterator def_end() { return def_iterator(0); }
104 /// def_empty - Return true if there are no instructions defining the
105 /// specified register (it may be live-in).
106 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
108 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
109 typedef defusechain_iterator<true,false> use_iterator;
110 use_iterator use_begin(unsigned RegNo) const {
111 return use_iterator(getRegUseDefListHead(RegNo));
113 static use_iterator use_end() { return use_iterator(0); }
115 /// use_empty - Return true if there are no instructions using the specified
117 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
120 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
121 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
122 /// except that it also changes any definitions of the register as well.
123 void replaceRegWith(unsigned FromReg, unsigned ToReg);
125 /// getRegUseDefListHead - Return the head pointer for the register use/def
126 /// list for the specified virtual or physical register.
127 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
128 if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
129 return PhysRegUseDefLists[RegNo];
130 RegNo -= TargetRegisterInfo::FirstVirtualRegister;
131 return VRegInfo[RegNo].second;
134 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
135 if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
136 return PhysRegUseDefLists[RegNo];
137 RegNo -= TargetRegisterInfo::FirstVirtualRegister;
138 return VRegInfo[RegNo].second;
141 /// getVRegDef - Return the machine instr that defines the specified virtual
142 /// register or null if none is found. This assumes that the code is in SSA
143 /// form, so there should only be one definition.
144 MachineInstr *getVRegDef(unsigned Reg) const;
147 void dumpUses(unsigned RegNo) const;
150 //===--------------------------------------------------------------------===//
151 // Virtual Register Info
152 //===--------------------------------------------------------------------===//
154 /// getRegClass - Return the register class of the specified virtual register.
156 const TargetRegisterClass *getRegClass(unsigned Reg) const {
157 Reg -= TargetRegisterInfo::FirstVirtualRegister;
158 assert(Reg < VRegInfo.size() && "Invalid vreg!");
159 return VRegInfo[Reg].first;
162 /// setRegClass - Set the register class of the specified virtual register.
164 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
166 /// createVirtualRegister - Create and return a new virtual register in the
167 /// function with the specified register class.
169 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
171 /// getLastVirtReg - Return the highest currently assigned virtual register.
173 unsigned getLastVirtReg() const {
174 return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1;
177 /// getRegClassVirtRegs - Return the list of virtual registers of the given
178 /// target register class.
179 std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) {
180 return RegClass2VRegMap[RC->getID()];
183 /// setRegAllocationHint - Specify a register allocation hint for the
184 /// specified virtual register.
185 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
186 Reg -= TargetRegisterInfo::FirstVirtualRegister;
187 assert(Reg < VRegInfo.size() && "Invalid vreg!");
188 RegAllocHints[Reg].first = Type;
189 RegAllocHints[Reg].second = PrefReg;
192 /// getRegAllocationHint - Return the register allocation hint for the
193 /// specified virtual register.
194 std::pair<unsigned, unsigned>
195 getRegAllocationHint(unsigned Reg) const {
196 Reg -= TargetRegisterInfo::FirstVirtualRegister;
197 assert(Reg < VRegInfo.size() && "Invalid vreg!");
198 return RegAllocHints[Reg];
201 //===--------------------------------------------------------------------===//
202 // Physical Register Use Info
203 //===--------------------------------------------------------------------===//
205 /// isPhysRegUsed - Return true if the specified register is used in this
206 /// function. This only works after register allocation.
207 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; }
209 /// setPhysRegUsed - Mark the specified register used in this function.
210 /// This should only be called during and after register allocation.
211 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; }
213 /// setPhysRegUnused - Mark the specified register unused in this function.
214 /// This should only be called during and after register allocation.
215 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; }
218 //===--------------------------------------------------------------------===//
219 // LiveIn/LiveOut Management
220 //===--------------------------------------------------------------------===//
222 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it
223 /// is an error to add the same register to the same set more than once.
224 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
225 LiveIns.push_back(std::make_pair(Reg, vreg));
227 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
229 // Iteration support for live in/out sets. These sets are kept in sorted
230 // order by their register number.
231 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
233 typedef std::vector<unsigned>::const_iterator liveout_iterator;
234 livein_iterator livein_begin() const { return LiveIns.begin(); }
235 livein_iterator livein_end() const { return LiveIns.end(); }
236 bool livein_empty() const { return LiveIns.empty(); }
237 liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
238 liveout_iterator liveout_end() const { return LiveOuts.end(); }
239 bool liveout_empty() const { return LiveOuts.empty(); }
241 bool isLiveIn(unsigned Reg) const {
242 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
243 if (I->first == Reg || I->second == Reg)
249 void HandleVRegListReallocation();
252 /// defusechain_iterator - This class provides iterator support for machine
253 /// operands in the function that use or define a specific register. If
254 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
255 /// returns defs. If neither are true then you are silly and it always
257 template<bool ReturnUses, bool ReturnDefs>
258 class defusechain_iterator
259 : public forward_iterator<MachineInstr, ptrdiff_t> {
261 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
262 // If the first node isn't one we're interested in, advance to one that
263 // we are interested in.
265 if ((!ReturnUses && op->isUse()) ||
266 (!ReturnDefs && op->isDef()))
270 friend class MachineRegisterInfo;
272 typedef forward_iterator<MachineInstr, ptrdiff_t>::reference reference;
273 typedef forward_iterator<MachineInstr, ptrdiff_t>::pointer pointer;
275 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
276 defusechain_iterator() : Op(0) {}
278 bool operator==(const defusechain_iterator &x) const {
281 bool operator!=(const defusechain_iterator &x) const {
282 return !operator==(x);
285 /// atEnd - return true if this iterator is equal to reg_end() on the value.
286 bool atEnd() const { return Op == 0; }
288 // Iterator traversal: forward iteration only
289 defusechain_iterator &operator++() { // Preincrement
290 assert(Op && "Cannot increment end iterator!");
291 Op = Op->getNextOperandForReg();
293 // If this is an operand we don't care about, skip it.
294 while (Op && ((!ReturnUses && Op->isUse()) ||
295 (!ReturnDefs && Op->isDef())))
296 Op = Op->getNextOperandForReg();
300 defusechain_iterator operator++(int) { // Postincrement
301 defusechain_iterator tmp = *this; ++*this; return tmp;
304 MachineOperand &getOperand() const {
305 assert(Op && "Cannot dereference end iterator!");
309 /// getOperandNo - Return the operand # of this MachineOperand in its
311 unsigned getOperandNo() const {
312 assert(Op && "Cannot dereference end iterator!");
313 return Op - &Op->getParent()->getOperand(0);
316 // Retrieve a reference to the current operand.
317 MachineInstr &operator*() const {
318 assert(Op && "Cannot dereference end iterator!");
319 return *Op->getParent();
322 MachineInstr *operator->() const {
323 assert(Op && "Cannot dereference end iterator!");
324 return Op->getParent();
330 } // End llvm namespace