1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/IndexedMap.h"
19 #include "llvm/ADT/iterator_range.h"
20 #include "llvm/CodeGen/MachineInstrBundle.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
28 /// MachineRegisterInfo - Keep track of information for virtual and physical
29 /// registers, including vreg register classes, use/def chains for registers,
31 class MachineRegisterInfo {
34 virtual void anchor();
36 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
38 virtual ~Delegate() {}
42 const TargetMachine &TM;
43 Delegate *TheDelegate;
45 /// IsSSA - True when the machine function is in SSA form and virtual
46 /// registers have a single def.
49 /// TracksLiveness - True while register liveness is being tracked accurately.
50 /// Basic block live-in lists, kill flags, and implicit defs may not be
51 /// accurate when after this flag is cleared.
54 /// VRegInfo - Information we keep for each virtual register.
56 /// Each element in this list contains the register class of the vreg and the
57 /// start of the use/def list for the register.
58 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>,
59 VirtReg2IndexFunctor> VRegInfo;
61 /// RegAllocHints - This vector records register allocation hints for virtual
62 /// registers. For each virtual register, it keeps a register and hint type
63 /// pair making up the allocation hint. Hint type is target specific except
64 /// for the value 0 which means the second value of the pair is the preferred
65 /// register for allocation. For example, if the hint is <0, 1024>, it means
66 /// the allocator should prefer the physical register allocated to the virtual
67 /// register of the hint.
68 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints;
70 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
71 /// physical registers.
72 MachineOperand **PhysRegUseDefLists;
74 /// getRegUseDefListHead - Return the head pointer for the register use/def
75 /// list for the specified virtual or physical register.
76 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
77 if (TargetRegisterInfo::isVirtualRegister(RegNo))
78 return VRegInfo[RegNo].second;
79 return PhysRegUseDefLists[RegNo];
82 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
83 if (TargetRegisterInfo::isVirtualRegister(RegNo))
84 return VRegInfo[RegNo].second;
85 return PhysRegUseDefLists[RegNo];
88 /// Get the next element in the use-def chain.
89 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
90 assert(MO && MO->isReg() && "This is not a register operand!");
91 return MO->Contents.Reg.Next;
94 /// UsedRegUnits - This is a bit vector that is computed and set by the
95 /// register allocator, and must be kept up to date by passes that run after
96 /// register allocation (though most don't modify this). This is used
97 /// so that the code generator knows which callee save registers to save and
98 /// for other target specific uses.
99 /// This vector has bits set for register units that are modified in the
100 /// current function. It doesn't include registers clobbered by function
101 /// calls with register mask operands.
102 BitVector UsedRegUnits;
104 /// UsedPhysRegMask - Additional used physregs including aliases.
105 /// This bit vector represents all the registers clobbered by function calls.
106 /// It can model things that UsedRegUnits can't, such as function calls that
107 /// clobber ymm7 but preserve the low half in xmm7.
108 BitVector UsedPhysRegMask;
110 /// ReservedRegs - This is a bit vector of reserved registers. The target
111 /// may change its mind about which registers should be reserved. This
112 /// vector is the frozen set of reserved registers when register allocation
114 BitVector ReservedRegs;
116 /// Keep track of the physical registers that are live in to the function.
117 /// Live in values are typically arguments in registers. LiveIn values are
118 /// allowed to have virtual registers associated with them, stored in the
120 std::vector<std::pair<unsigned, unsigned> > LiveIns;
122 MachineRegisterInfo(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
123 void operator=(const MachineRegisterInfo&) LLVM_DELETED_FUNCTION;
125 explicit MachineRegisterInfo(const TargetMachine &TM);
126 ~MachineRegisterInfo();
128 const TargetRegisterInfo *getTargetRegisterInfo() const {
129 return TM.getRegisterInfo();
132 void resetDelegate(Delegate *delegate) {
133 // Ensure another delegate does not take over unless the current
134 // delegate first unattaches itself. If we ever need to multicast
135 // notifications, we will need to change to using a list.
136 assert(TheDelegate == delegate &&
137 "Only the current delegate can perform reset!");
141 void setDelegate(Delegate *delegate) {
142 assert(delegate && !TheDelegate &&
143 "Attempted to set delegate to null, or to change it without "
144 "first resetting it!");
146 TheDelegate = delegate;
149 //===--------------------------------------------------------------------===//
151 //===--------------------------------------------------------------------===//
153 // isSSA - Returns true when the machine function is in SSA form. Early
154 // passes require the machine function to be in SSA form where every virtual
155 // register has a single defining instruction.
157 // The TwoAddressInstructionPass and PHIElimination passes take the machine
158 // function out of SSA form when they introduce multiple defs per virtual
160 bool isSSA() const { return IsSSA; }
162 // leaveSSA - Indicates that the machine function is no longer in SSA form.
163 void leaveSSA() { IsSSA = false; }
165 /// tracksLiveness - Returns true when tracking register liveness accurately.
167 /// While this flag is true, register liveness information in basic block
168 /// live-in lists and machine instruction operands is accurate. This means it
169 /// can be used to change the code in ways that affect the values in
170 /// registers, for example by the register scavenger.
172 /// When this flag is false, liveness is no longer reliable.
173 bool tracksLiveness() const { return TracksLiveness; }
175 /// invalidateLiveness - Indicates that register liveness is no longer being
176 /// tracked accurately.
178 /// This should be called by late passes that invalidate the liveness
180 void invalidateLiveness() { TracksLiveness = false; }
182 //===--------------------------------------------------------------------===//
184 //===--------------------------------------------------------------------===//
186 // Strictly for use by MachineInstr.cpp.
187 void addRegOperandToUseList(MachineOperand *MO);
189 // Strictly for use by MachineInstr.cpp.
190 void removeRegOperandFromUseList(MachineOperand *MO);
192 // Strictly for use by MachineInstr.cpp.
193 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
195 /// Verify the sanity of the use list for Reg.
196 void verifyUseList(unsigned Reg) const;
198 /// Verify the use list of all registers.
199 void verifyUseLists() const;
201 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
202 /// and uses of a register within the MachineFunction that corresponds to this
203 /// MachineRegisterInfo object.
204 template<bool Uses, bool Defs, bool SkipDebug,
205 bool ByOperand, bool ByInstr, bool ByBundle>
206 class defusechain_iterator;
207 template<bool Uses, bool Defs, bool SkipDebug,
208 bool ByOperand, bool ByInstr, bool ByBundle>
209 class defusechain_instr_iterator;
211 // Make it a friend so it can access getNextOperandForReg().
212 template<bool, bool, bool, bool, bool, bool>
213 friend class defusechain_iterator;
214 template<bool, bool, bool, bool, bool, bool>
215 friend class defusechain_instr_iterator;
219 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
221 typedef defusechain_iterator<true,true,false,true,false,false>
223 reg_iterator reg_begin(unsigned RegNo) const {
224 return reg_iterator(getRegUseDefListHead(RegNo));
226 static reg_iterator reg_end() { return reg_iterator(0); }
228 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const {
229 return iterator_range<reg_iterator>(reg_begin(Reg), reg_end());
232 /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
233 /// of the specified register, stepping by MachineInstr.
234 typedef defusechain_instr_iterator<true,true,false,false,true,false>
236 reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
237 return reg_instr_iterator(getRegUseDefListHead(RegNo));
239 static reg_instr_iterator reg_instr_end() { return reg_instr_iterator(0); }
241 inline iterator_range<reg_instr_iterator>
242 reg_instructions(unsigned Reg) const {
243 return iterator_range<reg_instr_iterator>(reg_instr_begin(Reg),
247 /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
248 /// of the specified register, stepping by bundle.
249 typedef defusechain_instr_iterator<true,true,false,false,false,true>
251 reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
252 return reg_bundle_iterator(getRegUseDefListHead(RegNo));
254 static reg_bundle_iterator reg_bundle_end() { return reg_bundle_iterator(0); }
256 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const {
257 return iterator_range<reg_bundle_iterator>(reg_bundle_begin(Reg),
261 /// reg_empty - Return true if there are no instructions using or defining the
262 /// specified register (it may be live-in).
263 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
265 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
266 /// of the specified register, skipping those marked as Debug.
267 typedef defusechain_iterator<true,true,true,true,false,false>
269 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
270 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
272 static reg_nodbg_iterator reg_nodbg_end() { return reg_nodbg_iterator(0); }
274 inline iterator_range<reg_nodbg_iterator>
275 reg_nodbg_operands(unsigned Reg) const {
276 return iterator_range<reg_nodbg_iterator>(reg_nodbg_begin(Reg),
280 /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
281 /// all defs and uses of the specified register, stepping by MachineInstr,
282 /// skipping those marked as Debug.
283 typedef defusechain_instr_iterator<true,true,true,false,true,false>
284 reg_instr_nodbg_iterator;
285 reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const {
286 return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
288 static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
289 return reg_instr_nodbg_iterator(0);
292 inline iterator_range<reg_instr_nodbg_iterator>
293 reg_nodbg_instructions(unsigned Reg) const {
294 return iterator_range<reg_instr_nodbg_iterator>(reg_instr_nodbg_begin(Reg),
295 reg_instr_nodbg_end());
298 /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
299 /// all defs and uses of the specified register, stepping by bundle,
300 /// skipping those marked as Debug.
301 typedef defusechain_instr_iterator<true,true,true,false,false,true>
302 reg_bundle_nodbg_iterator;
303 reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const {
304 return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
306 static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
307 return reg_bundle_nodbg_iterator(0);
310 inline iterator_range<reg_bundle_nodbg_iterator>
311 reg_nodbg_bundles(unsigned Reg) const {
312 return iterator_range<reg_bundle_nodbg_iterator>(reg_bundle_nodbg_begin(Reg),
313 reg_bundle_nodbg_end());
316 /// reg_nodbg_empty - Return true if the only instructions using or defining
317 /// Reg are Debug instructions.
318 bool reg_nodbg_empty(unsigned RegNo) const {
319 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
322 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
323 typedef defusechain_iterator<false,true,false,true,false,false>
325 def_iterator def_begin(unsigned RegNo) const {
326 return def_iterator(getRegUseDefListHead(RegNo));
328 static def_iterator def_end() { return def_iterator(0); }
330 inline iterator_range<def_iterator> def_operands(unsigned Reg) const {
331 return iterator_range<def_iterator>(def_begin(Reg), def_end());
334 /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
335 /// specified register, stepping by MachineInst.
336 typedef defusechain_instr_iterator<false,true,false,false,true,false>
338 def_instr_iterator def_instr_begin(unsigned RegNo) const {
339 return def_instr_iterator(getRegUseDefListHead(RegNo));
341 static def_instr_iterator def_instr_end() { return def_instr_iterator(0); }
343 inline iterator_range<def_instr_iterator>
344 def_instructions(unsigned Reg) const {
345 return iterator_range<def_instr_iterator>(def_instr_begin(Reg),
349 /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
350 /// specified register, stepping by bundle.
351 typedef defusechain_instr_iterator<false,true,false,false,false,true>
353 def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
354 return def_bundle_iterator(getRegUseDefListHead(RegNo));
356 static def_bundle_iterator def_bundle_end() { return def_bundle_iterator(0); }
358 inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const {
359 return iterator_range<def_bundle_iterator>(def_bundle_begin(Reg),
363 /// def_empty - Return true if there are no instructions defining the
364 /// specified register (it may be live-in).
365 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
367 /// hasOneDef - Return true if there is exactly one instruction defining the
368 /// specified register.
369 bool hasOneDef(unsigned RegNo) const {
370 def_iterator DI = def_begin(RegNo);
373 return ++DI == def_end();
376 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
377 typedef defusechain_iterator<true,false,false,true,false,false>
379 use_iterator use_begin(unsigned RegNo) const {
380 return use_iterator(getRegUseDefListHead(RegNo));
382 static use_iterator use_end() { return use_iterator(0); }
384 inline iterator_range<use_iterator> use_operands(unsigned Reg) const {
385 return iterator_range<use_iterator>(use_begin(Reg), use_end());
388 /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
389 /// specified register, stepping by MachineInstr.
390 typedef defusechain_instr_iterator<true,false,false,false,true,false>
392 use_instr_iterator use_instr_begin(unsigned RegNo) const {
393 return use_instr_iterator(getRegUseDefListHead(RegNo));
395 static use_instr_iterator use_instr_end() { return use_instr_iterator(0); }
397 inline iterator_range<use_instr_iterator>
398 use_instructions(unsigned Reg) const {
399 return iterator_range<use_instr_iterator>(use_instr_begin(Reg),
403 /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
404 /// specified register, stepping by bundle.
405 typedef defusechain_instr_iterator<true,false,false,false,false,true>
407 use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
408 return use_bundle_iterator(getRegUseDefListHead(RegNo));
410 static use_bundle_iterator use_bundle_end() { return use_bundle_iterator(0); }
412 inline iterator_range<use_bundle_iterator> use_bundles(unsigned Reg) const {
413 return iterator_range<use_bundle_iterator>(use_bundle_begin(Reg),
417 /// use_empty - Return true if there are no instructions using the specified
419 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
421 /// hasOneUse - Return true if there is exactly one instruction using the
422 /// specified register.
423 bool hasOneUse(unsigned RegNo) const {
424 use_iterator UI = use_begin(RegNo);
427 return ++UI == use_end();
430 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
431 /// specified register, skipping those marked as Debug.
432 typedef defusechain_iterator<true,false,true,true,false,false>
434 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
435 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
437 static use_nodbg_iterator use_nodbg_end() { return use_nodbg_iterator(0); }
439 inline iterator_range<use_nodbg_iterator>
440 use_nodbg_operands(unsigned Reg) const {
441 return iterator_range<use_nodbg_iterator>(use_nodbg_begin(Reg),
445 /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
446 /// all uses of the specified register, stepping by MachineInstr, skipping
447 /// those marked as Debug.
448 typedef defusechain_instr_iterator<true,false,true,false,true,false>
449 use_instr_nodbg_iterator;
450 use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const {
451 return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
453 static use_instr_nodbg_iterator use_instr_nodbg_end() {
454 return use_instr_nodbg_iterator(0);
457 inline iterator_range<use_instr_nodbg_iterator>
458 use_nodbg_instructions(unsigned Reg) const {
459 return iterator_range<use_instr_nodbg_iterator>(use_instr_nodbg_begin(Reg),
460 use_instr_nodbg_end());
463 /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
464 /// all uses of the specified register, stepping by bundle, skipping
465 /// those marked as Debug.
466 typedef defusechain_instr_iterator<true,false,true,false,false,true>
467 use_bundle_nodbg_iterator;
468 use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const {
469 return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
471 static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
472 return use_bundle_nodbg_iterator(0);
475 inline iterator_range<use_bundle_nodbg_iterator>
476 use_nodbg_bundles(unsigned Reg) const {
477 return iterator_range<use_bundle_nodbg_iterator>(use_bundle_nodbg_begin(Reg),
478 use_bundle_nodbg_end());
481 /// use_nodbg_empty - Return true if there are no non-Debug instructions
482 /// using the specified register.
483 bool use_nodbg_empty(unsigned RegNo) const {
484 return use_nodbg_begin(RegNo) == use_nodbg_end();
487 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
488 /// instruction using the specified register.
489 bool hasOneNonDBGUse(unsigned RegNo) const;
491 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
492 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
493 /// except that it also changes any definitions of the register as well.
495 /// Note that it is usually necessary to first constrain ToReg's register
496 /// class to match the FromReg constraints using:
498 /// constrainRegClass(ToReg, getRegClass(FromReg))
500 /// That function will return NULL if the virtual registers have incompatible
502 void replaceRegWith(unsigned FromReg, unsigned ToReg);
504 /// getVRegDef - Return the machine instr that defines the specified virtual
505 /// register or null if none is found. This assumes that the code is in SSA
506 /// form, so there should only be one definition.
507 MachineInstr *getVRegDef(unsigned Reg) const;
509 /// getUniqueVRegDef - Return the unique machine instr that defines the
510 /// specified virtual register or null if none is found. If there are
511 /// multiple definitions or no definition, return null.
512 MachineInstr *getUniqueVRegDef(unsigned Reg) const;
514 /// clearKillFlags - Iterate over all the uses of the given register and
515 /// clear the kill flag from the MachineOperand. This function is used by
516 /// optimization passes which extend register lifetimes and need only
517 /// preserve conservative kill flag information.
518 void clearKillFlags(unsigned Reg) const;
521 void dumpUses(unsigned RegNo) const;
524 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
525 /// throughout the function. It is safe to move instructions that read such
527 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
529 /// Get an iterator over the pressure sets affected by the given physical or
530 /// virtual register. If RegUnit is physical, it must be a register unit (from
531 /// MCRegUnitIterator).
532 PSetIterator getPressureSets(unsigned RegUnit) const;
534 //===--------------------------------------------------------------------===//
535 // Virtual Register Info
536 //===--------------------------------------------------------------------===//
538 /// getRegClass - Return the register class of the specified virtual register.
540 const TargetRegisterClass *getRegClass(unsigned Reg) const {
541 return VRegInfo[Reg].first;
544 /// setRegClass - Set the register class of the specified virtual register.
546 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
548 /// constrainRegClass - Constrain the register class of the specified virtual
549 /// register to be a common subclass of RC and the current register class,
550 /// but only if the new class has at least MinNumRegs registers. Return the
551 /// new register class, or NULL if no such class exists.
552 /// This should only be used when the constraint is known to be trivial, like
553 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
555 const TargetRegisterClass *constrainRegClass(unsigned Reg,
556 const TargetRegisterClass *RC,
557 unsigned MinNumRegs = 0);
559 /// recomputeRegClass - Try to find a legal super-class of Reg's register
560 /// class that still satisfies the constraints from the instructions using
561 /// Reg. Returns true if Reg was upgraded.
563 /// This method can be used after constraints have been removed from a
564 /// virtual register, for example after removing instructions or splitting
567 bool recomputeRegClass(unsigned Reg, const TargetMachine&);
569 /// createVirtualRegister - Create and return a new virtual register in the
570 /// function with the specified register class.
572 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
574 /// getNumVirtRegs - Return the number of virtual registers created.
576 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
578 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
579 void clearVirtRegs();
581 /// setRegAllocationHint - Specify a register allocation hint for the
582 /// specified virtual register.
583 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) {
584 RegAllocHints[Reg].first = Type;
585 RegAllocHints[Reg].second = PrefReg;
588 /// getRegAllocationHint - Return the register allocation hint for the
589 /// specified virtual register.
590 std::pair<unsigned, unsigned>
591 getRegAllocationHint(unsigned Reg) const {
592 return RegAllocHints[Reg];
595 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
596 /// standard simple hint (Type == 0) is not set.
597 unsigned getSimpleHint(unsigned Reg) const {
598 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(Reg);
599 return Hint.first ? 0 : Hint.second;
602 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
603 /// specified register as undefined which causes the DBG_VALUE to be
604 /// deleted during LiveDebugVariables analysis.
605 void markUsesInDebugValueAsUndef(unsigned Reg) const;
607 //===--------------------------------------------------------------------===//
608 // Physical Register Use Info
609 //===--------------------------------------------------------------------===//
611 /// isPhysRegUsed - Return true if the specified register is used in this
612 /// function. Also check for clobbered aliases and registers clobbered by
613 /// function calls with register mask operands.
615 /// This only works after register allocation. It is primarily used by
616 /// PrologEpilogInserter to determine which callee-saved registers need
618 bool isPhysRegUsed(unsigned Reg) const {
619 if (UsedPhysRegMask.test(Reg))
621 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
622 Units.isValid(); ++Units)
623 if (UsedRegUnits.test(*Units))
628 /// Mark the specified register unit as used in this function.
629 /// This should only be called during and after register allocation.
630 void setRegUnitUsed(unsigned RegUnit) {
631 UsedRegUnits.set(RegUnit);
634 /// setPhysRegUsed - Mark the specified register used in this function.
635 /// This should only be called during and after register allocation.
636 void setPhysRegUsed(unsigned Reg) {
637 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
638 Units.isValid(); ++Units)
639 UsedRegUnits.set(*Units);
642 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
643 /// This corresponds to the bit mask attached to register mask operands.
644 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
645 UsedPhysRegMask.setBitsNotInMask(RegMask);
648 /// setPhysRegUnused - Mark the specified register unused in this function.
649 /// This should only be called during and after register allocation.
650 void setPhysRegUnused(unsigned Reg) {
651 UsedPhysRegMask.reset(Reg);
652 for (MCRegUnitIterator Units(Reg, getTargetRegisterInfo());
653 Units.isValid(); ++Units)
654 UsedRegUnits.reset(*Units);
658 //===--------------------------------------------------------------------===//
659 // Reserved Register Info
660 //===--------------------------------------------------------------------===//
662 // The set of reserved registers must be invariant during register
663 // allocation. For example, the target cannot suddenly decide it needs a
664 // frame pointer when the register allocator has already used the frame
665 // pointer register for something else.
667 // These methods can be used by target hooks like hasFP() to avoid changing
668 // the reserved register set during register allocation.
670 /// freezeReservedRegs - Called by the register allocator to freeze the set
671 /// of reserved registers before allocation begins.
672 void freezeReservedRegs(const MachineFunction&);
674 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
675 /// to ensure the set of reserved registers stays constant.
676 bool reservedRegsFrozen() const {
677 return !ReservedRegs.empty();
680 /// canReserveReg - Returns true if PhysReg can be used as a reserved
681 /// register. Any register can be reserved before freezeReservedRegs() is
683 bool canReserveReg(unsigned PhysReg) const {
684 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
687 /// getReservedRegs - Returns a reference to the frozen set of reserved
688 /// registers. This method should always be preferred to calling
689 /// TRI::getReservedRegs() when possible.
690 const BitVector &getReservedRegs() const {
691 assert(reservedRegsFrozen() &&
692 "Reserved registers haven't been frozen yet. "
693 "Use TRI::getReservedRegs().");
697 /// isReserved - Returns true when PhysReg is a reserved register.
699 /// Reserved registers may belong to an allocatable register class, but the
700 /// target has explicitly requested that they are not used.
702 bool isReserved(unsigned PhysReg) const {
703 return getReservedRegs().test(PhysReg);
706 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
707 /// register class and it hasn't been reserved.
709 /// Allocatable registers may show up in the allocation order of some virtual
710 /// register, so a register allocator needs to track its liveness and
712 bool isAllocatable(unsigned PhysReg) const {
713 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
714 !isReserved(PhysReg);
717 //===--------------------------------------------------------------------===//
719 //===--------------------------------------------------------------------===//
721 /// addLiveIn - Add the specified register as a live-in. Note that it
722 /// is an error to add the same register to the same set more than once.
723 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
724 LiveIns.push_back(std::make_pair(Reg, vreg));
727 // Iteration support for the live-ins set. It's kept in sorted order
728 // by register number.
729 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
731 livein_iterator livein_begin() const { return LiveIns.begin(); }
732 livein_iterator livein_end() const { return LiveIns.end(); }
733 bool livein_empty() const { return LiveIns.empty(); }
735 bool isLiveIn(unsigned Reg) const;
737 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
738 /// corresponding live-in physical register.
739 unsigned getLiveInPhysReg(unsigned VReg) const;
741 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
742 /// corresponding live-in physical register.
743 unsigned getLiveInVirtReg(unsigned PReg) const;
745 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
746 /// into the given entry block.
747 void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
748 const TargetRegisterInfo &TRI,
749 const TargetInstrInfo &TII);
751 /// defusechain_iterator - This class provides iterator support for machine
752 /// operands in the function that use or define a specific register. If
753 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
754 /// returns defs. If neither are true then you are silly and it always
755 /// returns end(). If SkipDebug is true it skips uses marked Debug
756 /// when incrementing.
757 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
758 bool ByOperand, bool ByInstr, bool ByBundle>
759 class defusechain_iterator
760 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
762 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
763 // If the first node isn't one we're interested in, advance to one that
764 // we are interested in.
766 if ((!ReturnUses && op->isUse()) ||
767 (!ReturnDefs && op->isDef()) ||
768 (SkipDebug && op->isDebug()))
772 friend class MachineRegisterInfo;
775 assert(Op && "Cannot increment end iterator!");
776 Op = getNextOperandForReg(Op);
778 // All defs come before the uses, so stop def_iterator early.
784 assert(!Op->isDebug() && "Can't have debug defs");
787 // If this is an operand we don't care about, skip it.
788 while (Op && ((!ReturnDefs && Op->isDef()) ||
789 (SkipDebug && Op->isDebug())))
790 Op = getNextOperandForReg(Op);
794 typedef std::iterator<std::forward_iterator_tag,
795 MachineInstr, ptrdiff_t>::reference reference;
796 typedef std::iterator<std::forward_iterator_tag,
797 MachineInstr, ptrdiff_t>::pointer pointer;
799 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
800 defusechain_iterator() : Op(0) {}
802 bool operator==(const defusechain_iterator &x) const {
805 bool operator!=(const defusechain_iterator &x) const {
806 return !operator==(x);
809 /// atEnd - return true if this iterator is equal to reg_end() on the value.
810 bool atEnd() const { return Op == 0; }
812 // Iterator traversal: forward iteration only
813 defusechain_iterator &operator++() { // Preincrement
814 assert(Op && "Cannot increment end iterator!");
818 MachineInstr *P = Op->getParent();
821 } while (Op && Op->getParent() == P);
822 } else if (ByBundle) {
823 MachineInstr *P = getBundleStart(Op->getParent());
826 } while (Op && getBundleStart(Op->getParent()) == P);
831 defusechain_iterator operator++(int) { // Postincrement
832 defusechain_iterator tmp = *this; ++*this; return tmp;
835 /// getOperandNo - Return the operand # of this MachineOperand in its
837 unsigned getOperandNo() const {
838 assert(Op && "Cannot dereference end iterator!");
839 return Op - &Op->getParent()->getOperand(0);
842 // Retrieve a reference to the current operand.
843 MachineOperand &operator*() const {
844 assert(Op && "Cannot dereference end iterator!");
848 MachineOperand *operator->() const {
849 assert(Op && "Cannot dereference end iterator!");
854 /// defusechain_iterator - This class provides iterator support for machine
855 /// operands in the function that use or define a specific register. If
856 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
857 /// returns defs. If neither are true then you are silly and it always
858 /// returns end(). If SkipDebug is true it skips uses marked Debug
859 /// when incrementing.
860 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
861 bool ByOperand, bool ByInstr, bool ByBundle>
862 class defusechain_instr_iterator
863 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
865 explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
866 // If the first node isn't one we're interested in, advance to one that
867 // we are interested in.
869 if ((!ReturnUses && op->isUse()) ||
870 (!ReturnDefs && op->isDef()) ||
871 (SkipDebug && op->isDebug()))
875 friend class MachineRegisterInfo;
878 assert(Op && "Cannot increment end iterator!");
879 Op = getNextOperandForReg(Op);
881 // All defs come before the uses, so stop def_iterator early.
887 assert(!Op->isDebug() && "Can't have debug defs");
890 // If this is an operand we don't care about, skip it.
891 while (Op && ((!ReturnDefs && Op->isDef()) ||
892 (SkipDebug && Op->isDebug())))
893 Op = getNextOperandForReg(Op);
897 typedef std::iterator<std::forward_iterator_tag,
898 MachineInstr, ptrdiff_t>::reference reference;
899 typedef std::iterator<std::forward_iterator_tag,
900 MachineInstr, ptrdiff_t>::pointer pointer;
902 defusechain_instr_iterator(const defusechain_instr_iterator &I) : Op(I.Op){}
903 defusechain_instr_iterator() : Op(0) {}
905 bool operator==(const defusechain_instr_iterator &x) const {
908 bool operator!=(const defusechain_instr_iterator &x) const {
909 return !operator==(x);
912 /// atEnd - return true if this iterator is equal to reg_end() on the value.
913 bool atEnd() const { return Op == 0; }
915 // Iterator traversal: forward iteration only
916 defusechain_instr_iterator &operator++() { // Preincrement
917 assert(Op && "Cannot increment end iterator!");
921 MachineInstr *P = Op->getParent();
924 } while (Op && Op->getParent() == P);
925 } else if (ByBundle) {
926 MachineInstr *P = getBundleStart(Op->getParent());
929 } while (Op && getBundleStart(Op->getParent()) == P);
934 defusechain_instr_iterator operator++(int) { // Postincrement
935 defusechain_instr_iterator tmp = *this; ++*this; return tmp;
938 // Retrieve a reference to the current operand.
939 MachineInstr &operator*() const {
940 assert(Op && "Cannot dereference end iterator!");
941 if (ByBundle) return *(getBundleStart(Op->getParent()));
942 return *Op->getParent();
945 MachineInstr *operator->() const {
946 assert(Op && "Cannot dereference end iterator!");
947 if (ByBundle) return getBundleStart(Op->getParent());
948 return Op->getParent();
953 /// Iterate over the pressure sets affected by the given physical or virtual
954 /// register. If Reg is physical, it must be a register unit (from
955 /// MCRegUnitIterator).
960 PSetIterator(): PSet(0), Weight(0) {}
961 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
962 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
963 if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
964 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
965 PSet = TRI->getRegClassPressureSets(RC);
966 Weight = TRI->getRegClassWeight(RC).RegWeight;
969 PSet = TRI->getRegUnitPressureSets(RegUnit);
970 Weight = TRI->getRegUnitWeight(RegUnit);
975 bool isValid() const { return PSet; }
977 unsigned getWeight() const { return Weight; }
979 unsigned operator*() const { return *PSet; }
982 assert(isValid() && "Invalid PSetIterator.");
989 inline PSetIterator MachineRegisterInfo::
990 getPressureSets(unsigned RegUnit) const {
991 return PSetIterator(RegUnit, this);
994 } // End llvm namespace