1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/ADT/BitVector.h"
18 #include "llvm/ADT/IndexedMap.h"
19 #include "llvm/ADT/iterator_range.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBundle.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
29 /// MachineRegisterInfo - Keep track of information for virtual and physical
30 /// registers, including vreg register classes, use/def chains for registers,
32 class MachineRegisterInfo {
35 virtual void anchor();
37 virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
39 virtual ~Delegate() {}
43 const MachineFunction *MF;
44 Delegate *TheDelegate;
46 /// IsSSA - True when the machine function is in SSA form and virtual
47 /// registers have a single def.
50 /// TracksLiveness - True while register liveness is being tracked accurately.
51 /// Basic block live-in lists, kill flags, and implicit defs may not be
52 /// accurate when after this flag is cleared.
55 /// True if subregister liveness is tracked.
56 bool TracksSubRegLiveness;
58 /// VRegInfo - Information we keep for each virtual register.
60 /// Each element in this list contains the register class of the vreg and the
61 /// start of the use/def list for the register.
62 IndexedMap<std::pair<const TargetRegisterClass*, MachineOperand*>,
63 VirtReg2IndexFunctor> VRegInfo;
65 /// RegAllocHints - This vector records register allocation hints for virtual
66 /// registers. For each virtual register, it keeps a register and hint type
67 /// pair making up the allocation hint. Hint type is target specific except
68 /// for the value 0 which means the second value of the pair is the preferred
69 /// register for allocation. For example, if the hint is <0, 1024>, it means
70 /// the allocator should prefer the physical register allocated to the virtual
71 /// register of the hint.
72 IndexedMap<std::pair<unsigned, unsigned>, VirtReg2IndexFunctor> RegAllocHints;
74 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
75 /// physical registers.
76 std::unique_ptr<MachineOperand *[]> PhysRegUseDefLists;
78 /// getRegUseDefListHead - Return the head pointer for the register use/def
79 /// list for the specified virtual or physical register.
80 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
81 if (TargetRegisterInfo::isVirtualRegister(RegNo))
82 return VRegInfo[RegNo].second;
83 return PhysRegUseDefLists[RegNo];
86 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
87 if (TargetRegisterInfo::isVirtualRegister(RegNo))
88 return VRegInfo[RegNo].second;
89 return PhysRegUseDefLists[RegNo];
92 /// Get the next element in the use-def chain.
93 static MachineOperand *getNextOperandForReg(const MachineOperand *MO) {
94 assert(MO && MO->isReg() && "This is not a register operand!");
95 return MO->Contents.Reg.Next;
98 /// UsedPhysRegMask - Additional used physregs including aliases.
99 /// This bit vector represents all the registers clobbered by function calls.
100 BitVector UsedPhysRegMask;
102 /// ReservedRegs - This is a bit vector of reserved registers. The target
103 /// may change its mind about which registers should be reserved. This
104 /// vector is the frozen set of reserved registers when register allocation
106 BitVector ReservedRegs;
108 /// Keep track of the physical registers that are live in to the function.
109 /// Live in values are typically arguments in registers. LiveIn values are
110 /// allowed to have virtual registers associated with them, stored in the
112 std::vector<std::pair<unsigned, unsigned> > LiveIns;
114 MachineRegisterInfo(const MachineRegisterInfo&) = delete;
115 void operator=(const MachineRegisterInfo&) = delete;
117 explicit MachineRegisterInfo(const MachineFunction *MF);
119 const TargetRegisterInfo *getTargetRegisterInfo() const {
120 return MF->getSubtarget().getRegisterInfo();
123 void resetDelegate(Delegate *delegate) {
124 // Ensure another delegate does not take over unless the current
125 // delegate first unattaches itself. If we ever need to multicast
126 // notifications, we will need to change to using a list.
127 assert(TheDelegate == delegate &&
128 "Only the current delegate can perform reset!");
129 TheDelegate = nullptr;
132 void setDelegate(Delegate *delegate) {
133 assert(delegate && !TheDelegate &&
134 "Attempted to set delegate to null, or to change it without "
135 "first resetting it!");
137 TheDelegate = delegate;
140 //===--------------------------------------------------------------------===//
142 //===--------------------------------------------------------------------===//
144 // isSSA - Returns true when the machine function is in SSA form. Early
145 // passes require the machine function to be in SSA form where every virtual
146 // register has a single defining instruction.
148 // The TwoAddressInstructionPass and PHIElimination passes take the machine
149 // function out of SSA form when they introduce multiple defs per virtual
151 bool isSSA() const { return IsSSA; }
153 // leaveSSA - Indicates that the machine function is no longer in SSA form.
154 void leaveSSA() { IsSSA = false; }
156 /// tracksLiveness - Returns true when tracking register liveness accurately.
158 /// While this flag is true, register liveness information in basic block
159 /// live-in lists and machine instruction operands is accurate. This means it
160 /// can be used to change the code in ways that affect the values in
161 /// registers, for example by the register scavenger.
163 /// When this flag is false, liveness is no longer reliable.
164 bool tracksLiveness() const { return TracksLiveness; }
166 /// invalidateLiveness - Indicates that register liveness is no longer being
167 /// tracked accurately.
169 /// This should be called by late passes that invalidate the liveness
171 void invalidateLiveness() { TracksLiveness = false; }
173 /// Returns true if liveness for register class @p RC should be tracked at
174 /// the subregister level.
175 bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const {
176 return subRegLivenessEnabled() && RC.HasDisjunctSubRegs;
178 bool shouldTrackSubRegLiveness(unsigned VReg) const {
179 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Must pass a VReg");
180 return shouldTrackSubRegLiveness(*getRegClass(VReg));
182 bool subRegLivenessEnabled() const {
183 return TracksSubRegLiveness;
186 void enableSubRegLiveness(bool Enable = true) {
187 TracksSubRegLiveness = Enable;
190 //===--------------------------------------------------------------------===//
192 //===--------------------------------------------------------------------===//
194 // Strictly for use by MachineInstr.cpp.
195 void addRegOperandToUseList(MachineOperand *MO);
197 // Strictly for use by MachineInstr.cpp.
198 void removeRegOperandFromUseList(MachineOperand *MO);
200 // Strictly for use by MachineInstr.cpp.
201 void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
203 /// Verify the sanity of the use list for Reg.
204 void verifyUseList(unsigned Reg) const;
206 /// Verify the use list of all registers.
207 void verifyUseLists() const;
209 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
210 /// and uses of a register within the MachineFunction that corresponds to this
211 /// MachineRegisterInfo object.
212 template<bool Uses, bool Defs, bool SkipDebug,
213 bool ByOperand, bool ByInstr, bool ByBundle>
214 class defusechain_iterator;
215 template<bool Uses, bool Defs, bool SkipDebug,
216 bool ByOperand, bool ByInstr, bool ByBundle>
217 class defusechain_instr_iterator;
219 // Make it a friend so it can access getNextOperandForReg().
220 template<bool, bool, bool, bool, bool, bool>
221 friend class defusechain_iterator;
222 template<bool, bool, bool, bool, bool, bool>
223 friend class defusechain_instr_iterator;
227 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
229 typedef defusechain_iterator<true,true,false,true,false,false>
231 reg_iterator reg_begin(unsigned RegNo) const {
232 return reg_iterator(getRegUseDefListHead(RegNo));
234 static reg_iterator reg_end() { return reg_iterator(nullptr); }
236 inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const {
237 return make_range(reg_begin(Reg), reg_end());
240 /// reg_instr_iterator/reg_instr_begin/reg_instr_end - Walk all defs and uses
241 /// of the specified register, stepping by MachineInstr.
242 typedef defusechain_instr_iterator<true,true,false,false,true,false>
244 reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
245 return reg_instr_iterator(getRegUseDefListHead(RegNo));
247 static reg_instr_iterator reg_instr_end() {
248 return reg_instr_iterator(nullptr);
251 inline iterator_range<reg_instr_iterator>
252 reg_instructions(unsigned Reg) const {
253 return make_range(reg_instr_begin(Reg), reg_instr_end());
256 /// reg_bundle_iterator/reg_bundle_begin/reg_bundle_end - Walk all defs and uses
257 /// of the specified register, stepping by bundle.
258 typedef defusechain_instr_iterator<true,true,false,false,false,true>
260 reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
261 return reg_bundle_iterator(getRegUseDefListHead(RegNo));
263 static reg_bundle_iterator reg_bundle_end() {
264 return reg_bundle_iterator(nullptr);
267 inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const {
268 return make_range(reg_bundle_begin(Reg), reg_bundle_end());
271 /// reg_empty - Return true if there are no instructions using or defining the
272 /// specified register (it may be live-in).
273 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
275 /// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
276 /// of the specified register, skipping those marked as Debug.
277 typedef defusechain_iterator<true,true,true,true,false,false>
279 reg_nodbg_iterator reg_nodbg_begin(unsigned RegNo) const {
280 return reg_nodbg_iterator(getRegUseDefListHead(RegNo));
282 static reg_nodbg_iterator reg_nodbg_end() {
283 return reg_nodbg_iterator(nullptr);
286 inline iterator_range<reg_nodbg_iterator>
287 reg_nodbg_operands(unsigned Reg) const {
288 return make_range(reg_nodbg_begin(Reg), reg_nodbg_end());
291 /// reg_instr_nodbg_iterator/reg_instr_nodbg_begin/reg_instr_nodbg_end - Walk
292 /// all defs and uses of the specified register, stepping by MachineInstr,
293 /// skipping those marked as Debug.
294 typedef defusechain_instr_iterator<true,true,true,false,true,false>
295 reg_instr_nodbg_iterator;
296 reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const {
297 return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
299 static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
300 return reg_instr_nodbg_iterator(nullptr);
303 inline iterator_range<reg_instr_nodbg_iterator>
304 reg_nodbg_instructions(unsigned Reg) const {
305 return make_range(reg_instr_nodbg_begin(Reg), reg_instr_nodbg_end());
308 /// reg_bundle_nodbg_iterator/reg_bundle_nodbg_begin/reg_bundle_nodbg_end - Walk
309 /// all defs and uses of the specified register, stepping by bundle,
310 /// skipping those marked as Debug.
311 typedef defusechain_instr_iterator<true,true,true,false,false,true>
312 reg_bundle_nodbg_iterator;
313 reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const {
314 return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
316 static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
317 return reg_bundle_nodbg_iterator(nullptr);
320 inline iterator_range<reg_bundle_nodbg_iterator>
321 reg_nodbg_bundles(unsigned Reg) const {
322 return make_range(reg_bundle_nodbg_begin(Reg), reg_bundle_nodbg_end());
325 /// reg_nodbg_empty - Return true if the only instructions using or defining
326 /// Reg are Debug instructions.
327 bool reg_nodbg_empty(unsigned RegNo) const {
328 return reg_nodbg_begin(RegNo) == reg_nodbg_end();
331 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
332 typedef defusechain_iterator<false,true,false,true,false,false>
334 def_iterator def_begin(unsigned RegNo) const {
335 return def_iterator(getRegUseDefListHead(RegNo));
337 static def_iterator def_end() { return def_iterator(nullptr); }
339 inline iterator_range<def_iterator> def_operands(unsigned Reg) const {
340 return make_range(def_begin(Reg), def_end());
343 /// def_instr_iterator/def_instr_begin/def_instr_end - Walk all defs of the
344 /// specified register, stepping by MachineInst.
345 typedef defusechain_instr_iterator<false,true,false,false,true,false>
347 def_instr_iterator def_instr_begin(unsigned RegNo) const {
348 return def_instr_iterator(getRegUseDefListHead(RegNo));
350 static def_instr_iterator def_instr_end() {
351 return def_instr_iterator(nullptr);
354 inline iterator_range<def_instr_iterator>
355 def_instructions(unsigned Reg) const {
356 return make_range(def_instr_begin(Reg), def_instr_end());
359 /// def_bundle_iterator/def_bundle_begin/def_bundle_end - Walk all defs of the
360 /// specified register, stepping by bundle.
361 typedef defusechain_instr_iterator<false,true,false,false,false,true>
363 def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
364 return def_bundle_iterator(getRegUseDefListHead(RegNo));
366 static def_bundle_iterator def_bundle_end() {
367 return def_bundle_iterator(nullptr);
370 inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const {
371 return make_range(def_bundle_begin(Reg), def_bundle_end());
374 /// def_empty - Return true if there are no instructions defining the
375 /// specified register (it may be live-in).
376 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
378 /// hasOneDef - Return true if there is exactly one instruction defining the
379 /// specified register.
380 bool hasOneDef(unsigned RegNo) const {
381 def_iterator DI = def_begin(RegNo);
384 return ++DI == def_end();
387 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
388 typedef defusechain_iterator<true,false,false,true,false,false>
390 use_iterator use_begin(unsigned RegNo) const {
391 return use_iterator(getRegUseDefListHead(RegNo));
393 static use_iterator use_end() { return use_iterator(nullptr); }
395 inline iterator_range<use_iterator> use_operands(unsigned Reg) const {
396 return make_range(use_begin(Reg), use_end());
399 /// use_instr_iterator/use_instr_begin/use_instr_end - Walk all uses of the
400 /// specified register, stepping by MachineInstr.
401 typedef defusechain_instr_iterator<true,false,false,false,true,false>
403 use_instr_iterator use_instr_begin(unsigned RegNo) const {
404 return use_instr_iterator(getRegUseDefListHead(RegNo));
406 static use_instr_iterator use_instr_end() {
407 return use_instr_iterator(nullptr);
410 inline iterator_range<use_instr_iterator>
411 use_instructions(unsigned Reg) const {
412 return make_range(use_instr_begin(Reg), use_instr_end());
415 /// use_bundle_iterator/use_bundle_begin/use_bundle_end - Walk all uses of the
416 /// specified register, stepping by bundle.
417 typedef defusechain_instr_iterator<true,false,false,false,false,true>
419 use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
420 return use_bundle_iterator(getRegUseDefListHead(RegNo));
422 static use_bundle_iterator use_bundle_end() {
423 return use_bundle_iterator(nullptr);
426 inline iterator_range<use_bundle_iterator> use_bundles(unsigned Reg) const {
427 return make_range(use_bundle_begin(Reg), use_bundle_end());
430 /// use_empty - Return true if there are no instructions using the specified
432 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
434 /// hasOneUse - Return true if there is exactly one instruction using the
435 /// specified register.
436 bool hasOneUse(unsigned RegNo) const {
437 use_iterator UI = use_begin(RegNo);
440 return ++UI == use_end();
443 /// use_nodbg_iterator/use_nodbg_begin/use_nodbg_end - Walk all uses of the
444 /// specified register, skipping those marked as Debug.
445 typedef defusechain_iterator<true,false,true,true,false,false>
447 use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
448 return use_nodbg_iterator(getRegUseDefListHead(RegNo));
450 static use_nodbg_iterator use_nodbg_end() {
451 return use_nodbg_iterator(nullptr);
454 inline iterator_range<use_nodbg_iterator>
455 use_nodbg_operands(unsigned Reg) const {
456 return make_range(use_nodbg_begin(Reg), use_nodbg_end());
459 /// use_instr_nodbg_iterator/use_instr_nodbg_begin/use_instr_nodbg_end - Walk
460 /// all uses of the specified register, stepping by MachineInstr, skipping
461 /// those marked as Debug.
462 typedef defusechain_instr_iterator<true,false,true,false,true,false>
463 use_instr_nodbg_iterator;
464 use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const {
465 return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
467 static use_instr_nodbg_iterator use_instr_nodbg_end() {
468 return use_instr_nodbg_iterator(nullptr);
471 inline iterator_range<use_instr_nodbg_iterator>
472 use_nodbg_instructions(unsigned Reg) const {
473 return make_range(use_instr_nodbg_begin(Reg), use_instr_nodbg_end());
476 /// use_bundle_nodbg_iterator/use_bundle_nodbg_begin/use_bundle_nodbg_end - Walk
477 /// all uses of the specified register, stepping by bundle, skipping
478 /// those marked as Debug.
479 typedef defusechain_instr_iterator<true,false,true,false,false,true>
480 use_bundle_nodbg_iterator;
481 use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const {
482 return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
484 static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
485 return use_bundle_nodbg_iterator(nullptr);
488 inline iterator_range<use_bundle_nodbg_iterator>
489 use_nodbg_bundles(unsigned Reg) const {
490 return make_range(use_bundle_nodbg_begin(Reg), use_bundle_nodbg_end());
493 /// use_nodbg_empty - Return true if there are no non-Debug instructions
494 /// using the specified register.
495 bool use_nodbg_empty(unsigned RegNo) const {
496 return use_nodbg_begin(RegNo) == use_nodbg_end();
499 /// hasOneNonDBGUse - Return true if there is exactly one non-Debug
500 /// instruction using the specified register.
501 bool hasOneNonDBGUse(unsigned RegNo) const;
503 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
504 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
505 /// except that it also changes any definitions of the register as well.
507 /// Note that it is usually necessary to first constrain ToReg's register
508 /// class to match the FromReg constraints using:
510 /// constrainRegClass(ToReg, getRegClass(FromReg))
512 /// That function will return NULL if the virtual registers have incompatible
515 /// Note that if ToReg is a physical register the function will replace and
516 /// apply sub registers to ToReg in order to obtain a final/proper physical
518 void replaceRegWith(unsigned FromReg, unsigned ToReg);
520 /// getVRegDef - Return the machine instr that defines the specified virtual
521 /// register or null if none is found. This assumes that the code is in SSA
522 /// form, so there should only be one definition.
523 MachineInstr *getVRegDef(unsigned Reg) const;
525 /// getUniqueVRegDef - Return the unique machine instr that defines the
526 /// specified virtual register or null if none is found. If there are
527 /// multiple definitions or no definition, return null.
528 MachineInstr *getUniqueVRegDef(unsigned Reg) const;
530 /// clearKillFlags - Iterate over all the uses of the given register and
531 /// clear the kill flag from the MachineOperand. This function is used by
532 /// optimization passes which extend register lifetimes and need only
533 /// preserve conservative kill flag information.
534 void clearKillFlags(unsigned Reg) const;
537 void dumpUses(unsigned RegNo) const;
540 /// isConstantPhysReg - Returns true if PhysReg is unallocatable and constant
541 /// throughout the function. It is safe to move instructions that read such
543 bool isConstantPhysReg(unsigned PhysReg, const MachineFunction &MF) const;
545 /// Get an iterator over the pressure sets affected by the given physical or
546 /// virtual register. If RegUnit is physical, it must be a register unit (from
547 /// MCRegUnitIterator).
548 PSetIterator getPressureSets(unsigned RegUnit) const;
550 //===--------------------------------------------------------------------===//
551 // Virtual Register Info
552 //===--------------------------------------------------------------------===//
554 /// getRegClass - Return the register class of the specified virtual register.
556 const TargetRegisterClass *getRegClass(unsigned Reg) const {
557 return VRegInfo[Reg].first;
560 /// setRegClass - Set the register class of the specified virtual register.
562 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
564 /// constrainRegClass - Constrain the register class of the specified virtual
565 /// register to be a common subclass of RC and the current register class,
566 /// but only if the new class has at least MinNumRegs registers. Return the
567 /// new register class, or NULL if no such class exists.
568 /// This should only be used when the constraint is known to be trivial, like
569 /// GR32 -> GR32_NOSP. Beware of increasing register pressure.
571 const TargetRegisterClass *constrainRegClass(unsigned Reg,
572 const TargetRegisterClass *RC,
573 unsigned MinNumRegs = 0);
575 /// recomputeRegClass - Try to find a legal super-class of Reg's register
576 /// class that still satisfies the constraints from the instructions using
577 /// Reg. Returns true if Reg was upgraded.
579 /// This method can be used after constraints have been removed from a
580 /// virtual register, for example after removing instructions or splitting
583 bool recomputeRegClass(unsigned Reg);
585 /// createVirtualRegister - Create and return a new virtual register in the
586 /// function with the specified register class.
588 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
590 /// getNumVirtRegs - Return the number of virtual registers created.
592 unsigned getNumVirtRegs() const { return VRegInfo.size(); }
594 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
595 void clearVirtRegs();
597 /// setRegAllocationHint - Specify a register allocation hint for the
598 /// specified virtual register.
599 void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) {
600 assert(TargetRegisterInfo::isVirtualRegister(VReg));
601 RegAllocHints[VReg].first = Type;
602 RegAllocHints[VReg].second = PrefReg;
605 /// Specify the preferred register allocation hint for the specified virtual
607 void setSimpleHint(unsigned VReg, unsigned PrefReg) {
608 setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
611 /// getRegAllocationHint - Return the register allocation hint for the
612 /// specified virtual register.
613 std::pair<unsigned, unsigned>
614 getRegAllocationHint(unsigned VReg) const {
615 assert(TargetRegisterInfo::isVirtualRegister(VReg));
616 return RegAllocHints[VReg];
619 /// getSimpleHint - Return the preferred register allocation hint, or 0 if a
620 /// standard simple hint (Type == 0) is not set.
621 unsigned getSimpleHint(unsigned VReg) const {
622 assert(TargetRegisterInfo::isVirtualRegister(VReg));
623 std::pair<unsigned, unsigned> Hint = getRegAllocationHint(VReg);
624 return Hint.first ? 0 : Hint.second;
627 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
628 /// specified register as undefined which causes the DBG_VALUE to be
629 /// deleted during LiveDebugVariables analysis.
630 void markUsesInDebugValueAsUndef(unsigned Reg) const;
632 /// Return true if the specified register is modified in this function.
633 /// This checks that no defining machine operands exist for the register or
634 /// any of its aliases. Definitions found on functions marked noreturn are
635 /// ignored. The register is also considered modified when it is set in the
637 bool isPhysRegModified(unsigned PhysReg) const;
639 /// Return true if the specified register is modified or read in this
640 /// function. This checks that no machine operands exist for the register or
641 /// any of its aliases. The register is also considered used when it is set
642 /// in the UsedPhysRegMask.
643 bool isPhysRegUsed(unsigned PhysReg) const;
645 /// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
646 /// This corresponds to the bit mask attached to register mask operands.
647 void addPhysRegsUsedFromRegMask(const uint32_t *RegMask) {
648 UsedPhysRegMask.setBitsNotInMask(RegMask);
651 const BitVector &getUsedPhysRegsMask() const { return UsedPhysRegMask; }
653 void setUsedPhysRegMask(BitVector &Mask) { UsedPhysRegMask = Mask; }
655 //===--------------------------------------------------------------------===//
656 // Reserved Register Info
657 //===--------------------------------------------------------------------===//
659 // The set of reserved registers must be invariant during register
660 // allocation. For example, the target cannot suddenly decide it needs a
661 // frame pointer when the register allocator has already used the frame
662 // pointer register for something else.
664 // These methods can be used by target hooks like hasFP() to avoid changing
665 // the reserved register set during register allocation.
667 /// freezeReservedRegs - Called by the register allocator to freeze the set
668 /// of reserved registers before allocation begins.
669 void freezeReservedRegs(const MachineFunction&);
671 /// reservedRegsFrozen - Returns true after freezeReservedRegs() was called
672 /// to ensure the set of reserved registers stays constant.
673 bool reservedRegsFrozen() const {
674 return !ReservedRegs.empty();
677 /// canReserveReg - Returns true if PhysReg can be used as a reserved
678 /// register. Any register can be reserved before freezeReservedRegs() is
680 bool canReserveReg(unsigned PhysReg) const {
681 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
684 /// getReservedRegs - Returns a reference to the frozen set of reserved
685 /// registers. This method should always be preferred to calling
686 /// TRI::getReservedRegs() when possible.
687 const BitVector &getReservedRegs() const {
688 assert(reservedRegsFrozen() &&
689 "Reserved registers haven't been frozen yet. "
690 "Use TRI::getReservedRegs().");
694 /// isReserved - Returns true when PhysReg is a reserved register.
696 /// Reserved registers may belong to an allocatable register class, but the
697 /// target has explicitly requested that they are not used.
699 bool isReserved(unsigned PhysReg) const {
700 return getReservedRegs().test(PhysReg);
703 /// isAllocatable - Returns true when PhysReg belongs to an allocatable
704 /// register class and it hasn't been reserved.
706 /// Allocatable registers may show up in the allocation order of some virtual
707 /// register, so a register allocator needs to track its liveness and
709 bool isAllocatable(unsigned PhysReg) const {
710 return getTargetRegisterInfo()->isInAllocatableClass(PhysReg) &&
711 !isReserved(PhysReg);
714 //===--------------------------------------------------------------------===//
716 //===--------------------------------------------------------------------===//
718 /// addLiveIn - Add the specified register as a live-in. Note that it
719 /// is an error to add the same register to the same set more than once.
720 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
721 LiveIns.push_back(std::make_pair(Reg, vreg));
724 // Iteration support for the live-ins set. It's kept in sorted order
725 // by register number.
726 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
728 livein_iterator livein_begin() const { return LiveIns.begin(); }
729 livein_iterator livein_end() const { return LiveIns.end(); }
730 bool livein_empty() const { return LiveIns.empty(); }
732 bool isLiveIn(unsigned Reg) const;
734 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
735 /// corresponding live-in physical register.
736 unsigned getLiveInPhysReg(unsigned VReg) const;
738 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
739 /// corresponding live-in physical register.
740 unsigned getLiveInVirtReg(unsigned PReg) const;
742 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
743 /// into the given entry block.
744 void EmitLiveInCopies(MachineBasicBlock *EntryMBB,
745 const TargetRegisterInfo &TRI,
746 const TargetInstrInfo &TII);
748 /// Returns a mask covering all bits that can appear in lane masks of
749 /// subregisters of the virtual register @p Reg.
750 LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const;
752 /// defusechain_iterator - This class provides iterator support for machine
753 /// operands in the function that use or define a specific register. If
754 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
755 /// returns defs. If neither are true then you are silly and it always
756 /// returns end(). If SkipDebug is true it skips uses marked Debug
757 /// when incrementing.
758 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
759 bool ByOperand, bool ByInstr, bool ByBundle>
760 class defusechain_iterator
761 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
763 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
764 // If the first node isn't one we're interested in, advance to one that
765 // we are interested in.
767 if ((!ReturnUses && op->isUse()) ||
768 (!ReturnDefs && op->isDef()) ||
769 (SkipDebug && op->isDebug()))
773 friend class MachineRegisterInfo;
776 assert(Op && "Cannot increment end iterator!");
777 Op = getNextOperandForReg(Op);
779 // All defs come before the uses, so stop def_iterator early.
785 assert(!Op->isDebug() && "Can't have debug defs");
788 // If this is an operand we don't care about, skip it.
789 while (Op && ((!ReturnDefs && Op->isDef()) ||
790 (SkipDebug && Op->isDebug())))
791 Op = getNextOperandForReg(Op);
795 typedef std::iterator<std::forward_iterator_tag,
796 MachineInstr, ptrdiff_t>::reference reference;
797 typedef std::iterator<std::forward_iterator_tag,
798 MachineInstr, ptrdiff_t>::pointer pointer;
800 defusechain_iterator() : Op(nullptr) {}
802 bool operator==(const defusechain_iterator &x) const {
805 bool operator!=(const defusechain_iterator &x) const {
806 return !operator==(x);
809 /// atEnd - return true if this iterator is equal to reg_end() on the value.
810 bool atEnd() const { return Op == nullptr; }
812 // Iterator traversal: forward iteration only
813 defusechain_iterator &operator++() { // Preincrement
814 assert(Op && "Cannot increment end iterator!");
818 MachineInstr *P = Op->getParent();
821 } while (Op && Op->getParent() == P);
822 } else if (ByBundle) {
823 MachineInstr *P = getBundleStart(Op->getParent());
826 } while (Op && getBundleStart(Op->getParent()) == P);
831 defusechain_iterator operator++(int) { // Postincrement
832 defusechain_iterator tmp = *this; ++*this; return tmp;
835 /// getOperandNo - Return the operand # of this MachineOperand in its
837 unsigned getOperandNo() const {
838 assert(Op && "Cannot dereference end iterator!");
839 return Op - &Op->getParent()->getOperand(0);
842 // Retrieve a reference to the current operand.
843 MachineOperand &operator*() const {
844 assert(Op && "Cannot dereference end iterator!");
848 MachineOperand *operator->() const {
849 assert(Op && "Cannot dereference end iterator!");
854 /// defusechain_iterator - This class provides iterator support for machine
855 /// operands in the function that use or define a specific register. If
856 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
857 /// returns defs. If neither are true then you are silly and it always
858 /// returns end(). If SkipDebug is true it skips uses marked Debug
859 /// when incrementing.
860 template<bool ReturnUses, bool ReturnDefs, bool SkipDebug,
861 bool ByOperand, bool ByInstr, bool ByBundle>
862 class defusechain_instr_iterator
863 : public std::iterator<std::forward_iterator_tag, MachineInstr, ptrdiff_t> {
865 explicit defusechain_instr_iterator(MachineOperand *op) : Op(op) {
866 // If the first node isn't one we're interested in, advance to one that
867 // we are interested in.
869 if ((!ReturnUses && op->isUse()) ||
870 (!ReturnDefs && op->isDef()) ||
871 (SkipDebug && op->isDebug()))
875 friend class MachineRegisterInfo;
878 assert(Op && "Cannot increment end iterator!");
879 Op = getNextOperandForReg(Op);
881 // All defs come before the uses, so stop def_iterator early.
887 assert(!Op->isDebug() && "Can't have debug defs");
890 // If this is an operand we don't care about, skip it.
891 while (Op && ((!ReturnDefs && Op->isDef()) ||
892 (SkipDebug && Op->isDebug())))
893 Op = getNextOperandForReg(Op);
897 typedef std::iterator<std::forward_iterator_tag,
898 MachineInstr, ptrdiff_t>::reference reference;
899 typedef std::iterator<std::forward_iterator_tag,
900 MachineInstr, ptrdiff_t>::pointer pointer;
902 defusechain_instr_iterator() : Op(nullptr) {}
904 bool operator==(const defusechain_instr_iterator &x) const {
907 bool operator!=(const defusechain_instr_iterator &x) const {
908 return !operator==(x);
911 /// atEnd - return true if this iterator is equal to reg_end() on the value.
912 bool atEnd() const { return Op == nullptr; }
914 // Iterator traversal: forward iteration only
915 defusechain_instr_iterator &operator++() { // Preincrement
916 assert(Op && "Cannot increment end iterator!");
920 MachineInstr *P = Op->getParent();
923 } while (Op && Op->getParent() == P);
924 } else if (ByBundle) {
925 MachineInstr *P = getBundleStart(Op->getParent());
928 } while (Op && getBundleStart(Op->getParent()) == P);
933 defusechain_instr_iterator operator++(int) { // Postincrement
934 defusechain_instr_iterator tmp = *this; ++*this; return tmp;
937 // Retrieve a reference to the current operand.
938 MachineInstr &operator*() const {
939 assert(Op && "Cannot dereference end iterator!");
940 if (ByBundle) return *(getBundleStart(Op->getParent()));
941 return *Op->getParent();
944 MachineInstr *operator->() const {
945 assert(Op && "Cannot dereference end iterator!");
946 if (ByBundle) return getBundleStart(Op->getParent());
947 return Op->getParent();
952 /// Iterate over the pressure sets affected by the given physical or virtual
953 /// register. If Reg is physical, it must be a register unit (from
954 /// MCRegUnitIterator).
959 PSetIterator(): PSet(nullptr), Weight(0) {}
960 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) {
961 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
962 if (TargetRegisterInfo::isVirtualRegister(RegUnit)) {
963 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
964 PSet = TRI->getRegClassPressureSets(RC);
965 Weight = TRI->getRegClassWeight(RC).RegWeight;
968 PSet = TRI->getRegUnitPressureSets(RegUnit);
969 Weight = TRI->getRegUnitWeight(RegUnit);
974 bool isValid() const { return PSet; }
976 unsigned getWeight() const { return Weight; }
978 unsigned operator*() const { return *PSet; }
981 assert(isValid() && "Invalid PSetIterator.");
988 inline PSetIterator MachineRegisterInfo::
989 getPressureSets(unsigned RegUnit) const {
990 return PSetIterator(RegUnit, this);
993 } // End llvm namespace