1 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
15 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
17 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "llvm/ADT/BitVector.h"
19 #include "llvm/ADT/iterator.h"
24 /// MachineRegisterInfo - Keep track of information for virtual and physical
25 /// registers, including vreg register classes, use/def chains for registers,
27 class MachineRegisterInfo {
28 /// VRegInfo - Information we keep for each virtual register. The entries in
29 /// this vector are actually converted to vreg numbers by adding the
30 /// TargetRegisterInfo::FirstVirtualRegister delta to their index.
32 /// Each element in this list contains the register class of the vreg and the
33 /// start of the use/def list for the register.
34 std::vector<std::pair<const TargetRegisterClass*, MachineOperand*> > VRegInfo;
36 /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to
37 /// virtual registers. For each target register class, it keeps a list of
38 /// virtual registers belonging to the class.
39 std::vector<std::vector<unsigned> > RegClass2VRegMap;
41 /// PhysRegUseDefLists - This is an array of the head of the use/def list for
42 /// physical registers.
43 MachineOperand **PhysRegUseDefLists;
45 /// UsedPhysRegs - This is a bit vector that is computed and set by the
46 /// register allocator, and must be kept up to date by passes that run after
47 /// register allocation (though most don't modify this). This is used
48 /// so that the code generator knows which callee save registers to save and
49 /// for other target specific uses.
50 BitVector UsedPhysRegs;
52 /// LiveIns/LiveOuts - Keep track of the physical registers that are
53 /// livein/liveout of the function. Live in values are typically arguments in
54 /// registers, live out values are typically return values in registers.
55 /// LiveIn values are allowed to have virtual registers associated with them,
56 /// stored in the second element.
57 std::vector<std::pair<unsigned, unsigned> > LiveIns;
58 std::vector<unsigned> LiveOuts;
60 MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT
61 void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT
63 explicit MachineRegisterInfo(const TargetRegisterInfo &TRI);
64 ~MachineRegisterInfo();
66 //===--------------------------------------------------------------------===//
68 //===--------------------------------------------------------------------===//
70 /// reg_begin/reg_end - Provide iteration support to walk over all definitions
71 /// and uses of a register within the MachineFunction that corresponds to this
72 /// MachineRegisterInfo object.
73 template<bool Uses, bool Defs>
74 class defusechain_iterator;
76 /// reg_iterator/reg_begin/reg_end - Walk all defs and uses of the specified
78 typedef defusechain_iterator<true,true> reg_iterator;
79 reg_iterator reg_begin(unsigned RegNo) const {
80 return reg_iterator(getRegUseDefListHead(RegNo));
82 static reg_iterator reg_end() { return reg_iterator(0); }
84 /// reg_empty - Return true if there are no instructions using or defining the
85 /// specified register (it may be live-in).
86 bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
88 /// def_iterator/def_begin/def_end - Walk all defs of the specified register.
89 typedef defusechain_iterator<false,true> def_iterator;
90 def_iterator def_begin(unsigned RegNo) const {
91 return def_iterator(getRegUseDefListHead(RegNo));
93 static def_iterator def_end() { return def_iterator(0); }
95 /// def_empty - Return true if there are no instructions defining the
96 /// specified register (it may be live-in).
97 bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
99 /// use_iterator/use_begin/use_end - Walk all uses of the specified register.
100 typedef defusechain_iterator<true,false> use_iterator;
101 use_iterator use_begin(unsigned RegNo) const {
102 return use_iterator(getRegUseDefListHead(RegNo));
104 static use_iterator use_end() { return use_iterator(0); }
106 /// use_empty - Return true if there are no instructions using the specified
108 bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
111 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
112 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
113 /// except that it also changes any definitions of the register as well.
114 void replaceRegWith(unsigned FromReg, unsigned ToReg);
116 /// getRegUseDefListHead - Return the head pointer for the register use/def
117 /// list for the specified virtual or physical register.
118 MachineOperand *&getRegUseDefListHead(unsigned RegNo) {
119 if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
120 return PhysRegUseDefLists[RegNo];
121 RegNo -= TargetRegisterInfo::FirstVirtualRegister;
122 return VRegInfo[RegNo].second;
125 MachineOperand *getRegUseDefListHead(unsigned RegNo) const {
126 if (RegNo < TargetRegisterInfo::FirstVirtualRegister)
127 return PhysRegUseDefLists[RegNo];
128 RegNo -= TargetRegisterInfo::FirstVirtualRegister;
129 return VRegInfo[RegNo].second;
132 /// getVRegDef - Return the machine instr that defines the specified virtual
133 /// register or null if none is found. This assumes that the code is in SSA
134 /// form, so there should only be one definition.
135 MachineInstr *getVRegDef(unsigned Reg) const;
138 void dumpUses(unsigned RegNo) const;
141 //===--------------------------------------------------------------------===//
142 // Virtual Register Info
143 //===--------------------------------------------------------------------===//
145 /// getRegClass - Return the register class of the specified virtual register.
147 const TargetRegisterClass *getRegClass(unsigned Reg) const {
148 Reg -= TargetRegisterInfo::FirstVirtualRegister;
149 assert(Reg < VRegInfo.size() && "Invalid vreg!");
150 return VRegInfo[Reg].first;
153 /// setRegClass - Set the register class of the specified virtual register.
155 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
157 /// createVirtualRegister - Create and return a new virtual register in the
158 /// function with the specified register class.
160 unsigned createVirtualRegister(const TargetRegisterClass *RegClass);
162 /// getLastVirtReg - Return the highest currently assigned virtual register.
164 unsigned getLastVirtReg() const {
165 return (unsigned)VRegInfo.size()+TargetRegisterInfo::FirstVirtualRegister-1;
168 /// getRegClassVirtRegs - Return the list of virtual registers of the given
169 /// target register class.
170 std::vector<unsigned> &getRegClassVirtRegs(const TargetRegisterClass *RC) {
171 return RegClass2VRegMap[RC->getID()];
174 //===--------------------------------------------------------------------===//
175 // Physical Register Use Info
176 //===--------------------------------------------------------------------===//
178 /// isPhysRegUsed - Return true if the specified register is used in this
179 /// function. This only works after register allocation.
180 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; }
182 /// setPhysRegUsed - Mark the specified register used in this function.
183 /// This should only be called during and after register allocation.
184 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; }
186 /// setPhysRegUnused - Mark the specified register unused in this function.
187 /// This should only be called during and after register allocation.
188 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; }
191 //===--------------------------------------------------------------------===//
192 // LiveIn/LiveOut Management
193 //===--------------------------------------------------------------------===//
195 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it
196 /// is an error to add the same register to the same set more than once.
197 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
198 LiveIns.push_back(std::make_pair(Reg, vreg));
200 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
202 // Iteration support for live in/out sets. These sets are kept in sorted
203 // order by their register number.
204 typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator
206 typedef std::vector<unsigned>::const_iterator liveout_iterator;
207 livein_iterator livein_begin() const { return LiveIns.begin(); }
208 livein_iterator livein_end() const { return LiveIns.end(); }
209 bool livein_empty() const { return LiveIns.empty(); }
210 liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
211 liveout_iterator liveout_end() const { return LiveOuts.end(); }
212 bool liveout_empty() const { return LiveOuts.empty(); }
214 bool isLiveIn(unsigned Reg) const {
215 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
216 if (I->first == Reg || I->second == Reg)
222 void HandleVRegListReallocation();
225 /// defusechain_iterator - This class provides iterator support for machine
226 /// operands in the function that use or define a specific register. If
227 /// ReturnUses is true it returns uses of registers, if ReturnDefs is true it
228 /// returns defs. If neither are true then you are silly and it always
230 template<bool ReturnUses, bool ReturnDefs>
231 class defusechain_iterator
232 : public forward_iterator<MachineInstr, ptrdiff_t> {
234 explicit defusechain_iterator(MachineOperand *op) : Op(op) {
235 // If the first node isn't one we're interested in, advance to one that
236 // we are interested in.
238 if ((!ReturnUses && op->isUse()) ||
239 (!ReturnDefs && op->isDef()))
243 friend class MachineRegisterInfo;
245 typedef forward_iterator<MachineInstr, ptrdiff_t>::reference reference;
246 typedef forward_iterator<MachineInstr, ptrdiff_t>::pointer pointer;
248 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {}
249 defusechain_iterator() : Op(0) {}
251 bool operator==(const defusechain_iterator &x) const {
254 bool operator!=(const defusechain_iterator &x) const {
255 return !operator==(x);
258 /// atEnd - return true if this iterator is equal to reg_end() on the value.
259 bool atEnd() const { return Op == 0; }
261 // Iterator traversal: forward iteration only
262 defusechain_iterator &operator++() { // Preincrement
263 assert(Op && "Cannot increment end iterator!");
264 Op = Op->getNextOperandForReg();
266 // If this is an operand we don't care about, skip it.
267 while (Op && ((!ReturnUses && Op->isUse()) ||
268 (!ReturnDefs && Op->isDef())))
269 Op = Op->getNextOperandForReg();
273 defusechain_iterator operator++(int) { // Postincrement
274 defusechain_iterator tmp = *this; ++*this; return tmp;
277 MachineOperand &getOperand() const {
278 assert(Op && "Cannot dereference end iterator!");
282 /// getOperandNo - Return the operand # of this MachineOperand in its
284 unsigned getOperandNo() const {
285 assert(Op && "Cannot dereference end iterator!");
286 return Op - &Op->getParent()->getOperand(0);
289 // Retrieve a reference to the current operand.
290 MachineInstr &operator*() const {
291 assert(Op && "Cannot dereference end iterator!");
292 return *Op->getParent();
295 MachineInstr *operator->() const {
296 assert(Op && "Cannot dereference end iterator!");
297 return Op->getParent();
303 } // End llvm namespace