1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Annotation.h"
13 #include "Support/iterator"
14 #include "Support/NonCopyable.h"
19 typedef int MachineOpCode;
20 typedef int OpCodeMask;
22 //---------------------------------------------------------------------------
23 // class MachineOperand
26 // Representation of each machine instruction operand.
27 // This class is designed so that you can allocate a vector of operands
28 // first and initialize each one later.
30 // E.g, for this VM instruction:
31 // ptr = alloca type, numElements
32 // we generate 2 machine instructions on the SPARC:
34 // mul Constant, Numelements -> Reg
35 // add %sp, Reg -> Ptr
37 // Each instruction has 3 operands, listed above. Of those:
38 // - Reg, NumElements, and Ptr are of operand type MO_Register.
39 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
41 // For the register operands, the virtual register type is as follows:
43 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
44 // MachineInstr* minstr will point to the instruction that computes reg.
46 // - %sp will be of virtual register type MO_MachineReg.
47 // The field regNum identifies the machine register.
49 // - NumElements will be of virtual register type MO_VirtualReg.
50 // The field Value* value identifies the value.
52 // - Ptr will also be of virtual register type MO_VirtualReg.
53 // Again, the field Value* value identifies the value.
55 //---------------------------------------------------------------------------
57 class MachineOperand {
59 enum MachineOperandType {
60 MO_VirtualRegister, // virtual register for *value
61 MO_MachineRegister, // pre-assigned machine register `regNum'
69 // Bit fields of the flags variable used for different operand properties
70 static const char DEFFLAG = 0x1; // this is a def of the operand
71 static const char DEFUSEFLAG = 0x2; // this is both a def and a use
72 static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal)
73 static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal)
74 static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
75 static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
79 Value* value; // BasicBlockVal for a label operand.
80 // ConstantVal for a non-address immediate.
81 // Virtual register for an SSA operand,
82 // including hidden operands required for
83 // the generated machine code.
84 int64_t immedVal; // constant value for an explicit constant
87 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
88 char flags; // see bit field definitions above
89 int regNum; // register number for an explicit register
90 // will be set for a value after reg allocation
93 : immedVal(0), opType(MO_VirtualRegister), flags(0), regNum(-1) {}
94 MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
95 : immedVal(ImmVal), opType(OpTy), flags(0), regNum(-1) {}
96 MachineOperand(int Reg, MachineOperandType OpTy, bool isDef = false)
97 : immedVal(0), opType(OpTy), flags(isDef ? DEFFLAG : 0), regNum(Reg) {}
98 MachineOperand(Value *V, MachineOperandType OpTy,
99 bool isDef = false, bool isDNU = false)
100 : value(V), opType(OpTy), regNum(-1) {
101 flags = (isDef ? DEFFLAG : 0) | (isDNU ? DEFUSEFLAG : 0);
105 MachineOperand(const MachineOperand &M)
106 : immedVal(M.immedVal), opType(M.opType), flags(M.flags), regNum(M.regNum) {
110 // Accessor methods. Caller is responsible for checking the
111 // operand type before invoking the corresponding accessor.
113 MachineOperandType getType() const { return opType; }
115 inline Value* getVRegValue () const {
116 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
117 opType == MO_PCRelativeDisp);
120 inline Value* getVRegValueOrNull() const {
121 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
122 opType == MO_PCRelativeDisp)? value : NULL;
124 inline int getMachineRegNum() const {
125 assert(opType == MO_MachineRegister);
128 inline int64_t getImmedValue () const {
129 assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
132 bool opIsDef () const { return flags & DEFFLAG; }
133 bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
134 bool opHiBits32 () const { return flags & HIFLAG32; }
135 bool opLoBits32 () const { return flags & LOFLAG32; }
136 bool opHiBits64 () const { return flags & HIFLAG64; }
137 bool opLoBits64 () const { return flags & LOFLAG64; }
139 // used to check if a machine register has been allocated to this operand
140 inline bool hasAllocatedReg() const {
141 return (regNum >= 0 &&
142 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
143 opType == MO_MachineRegister));
146 // used to get the reg number if when one is allocated
147 inline int getAllocatedRegNum() const {
148 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
149 opType == MO_MachineRegister);
154 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
158 // Construction methods needed for fine-grain control.
159 // These must be accessed via coresponding methods in MachineInstr.
160 void markDef() { flags |= DEFFLAG; }
161 void markDefAndUse() { flags |= DEFUSEFLAG; }
162 void markHi32() { flags |= HIFLAG32; }
163 void markLo32() { flags |= LOFLAG32; }
164 void markHi64() { flags |= HIFLAG64; }
165 void markLo64() { flags |= LOFLAG64; }
167 // Replaces the Value with its corresponding physical register after
168 // register allocation is complete
169 void setRegForValue(int reg) {
170 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
171 opType == MO_MachineRegister);
175 friend class MachineInstr;
179 //---------------------------------------------------------------------------
180 // class MachineInstr
183 // Representation of each machine instruction.
185 // MachineOpCode must be an enum, defined separately for each target.
186 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
188 // opCodeMask is used to record variants of an instruction.
189 // E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
190 // ANNUL: if 1: Annul delay slot instruction.
191 // PREDICT-NOT-TAKEN: if 1: predict branch not taken.
192 // Instead of creating 4 different opcodes for BNZ, we create a single
193 // opcode and set bits in opCodeMask for each of these flags.
195 // There are 2 kinds of operands:
197 // (1) Explicit operands of the machine instruction in vector operands[]
199 // (2) "Implicit operands" are values implicitly used or defined by the
200 // machine instruction, such as arguments to a CALL, return value of
201 // a CALL (if any), and return value of a RETURN.
202 //---------------------------------------------------------------------------
204 class MachineInstr : public Annotable, // MachineInstrs are annotable
205 public NonCopyable { // Disable copy operations
206 MachineOpCode opCode; // the opcode
207 OpCodeMask opCodeMask; // extra bits for variants of an opcode
208 std::vector<MachineOperand> operands; // the operands
212 bool isDef, isDefAndUse;
214 ImplicitRef(Value *V, bool D, bool DU) : Val(V), isDef(D), isDefAndUse(DU){}
217 // implicitRefs - Values implicitly referenced by this machine instruction
219 std::vector<ImplicitRef> implicitRefs;
221 // regsUsed - all machine registers used for this instruction, including regs
222 // used to save values across the instruction. This is a bitset of registers.
223 std::vector<bool> regsUsed;
225 // OperandComplete - Return true if it's illegal to add a new operand
226 bool OperandsComplete() const;
228 MachineInstr(MachineOpCode Opcode);
229 MachineInstr(MachineOpCode Opcode, unsigned numOperands);
231 /// MachineInstr ctor - This constructor only does a _reserve_ of the
232 /// operands, not a resize for them. It is expected that if you use this that
233 /// you call add* methods below to fill up the operands, instead of the Set
236 MachineInstr(MachineOpCode Opcode, unsigned numOperands, bool XX, bool YY);
239 // Support to rewrite a machine instruction in place: for now, simply
240 // replace() and then set new operands with Set.*Operand methods below.
242 void replace(MachineOpCode Opcode, unsigned numOperands);
247 const MachineOpCode getOpCode() const { return opCode; }
250 // Information about explicit operands of the instruction
252 unsigned getNumOperands() const { return operands.size(); }
254 const MachineOperand& getOperand(unsigned i) const {
255 assert(i < operands.size() && "getOperand() out of range!");
258 MachineOperand& getOperand(unsigned i) {
259 assert(i < operands.size() && "getOperand() out of range!");
263 MachineOperand::MachineOperandType getOperandType(unsigned i) const {
264 return getOperand(i).getType();
267 bool operandIsDefined(unsigned i) const {
268 return getOperand(i).opIsDef();
271 bool operandIsDefinedAndUsed(unsigned i) const {
272 return getOperand(i).opIsDefAndUse();
276 // Information about implicit operands of the instruction
278 unsigned getNumImplicitRefs() const{ return implicitRefs.size();}
280 const Value* getImplicitRef(unsigned i) const {
281 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
282 return implicitRefs[i].Val;
284 Value* getImplicitRef(unsigned i) {
285 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
286 return implicitRefs[i].Val;
289 bool implicitRefIsDefined(unsigned i) const {
290 assert(i < implicitRefs.size() && "implicitRefIsDefined() out of range!");
291 return implicitRefs[i].isDef;
293 bool implicitRefIsDefinedAndUsed(unsigned i) const {
294 assert(i < implicitRefs.size() && "implicitRefIsDef&Used() out of range!");
295 return implicitRefs[i].isDefAndUse;
298 void addImplicitRef(Value* V, bool isDef=false, bool isDefAndUse=false) {
299 implicitRefs.push_back(ImplicitRef(V, isDef, isDefAndUse));
302 void setImplicitRef(unsigned i, Value* V, bool isDef=false,
303 bool isDefAndUse=false) {
304 assert(i < implicitRefs.size() && "setImplicitRef() out of range!");
305 implicitRefs[i] = ImplicitRef(V, isDef, isDefAndUse);
309 // Information about registers used in this instruction
311 const std::vector<bool> &getRegsUsed() const { return regsUsed; }
313 // insertUsedReg - Add a register to the Used registers set...
314 void insertUsedReg(unsigned Reg) {
315 if (Reg >= regsUsed.size())
316 regsUsed.resize(Reg+1);
317 regsUsed[Reg] = true;
324 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
327 // Define iterators to access the Value operands of the Machine Instruction.
328 // begin() and end() are defined to produce these iterators...
330 template<class _MI, class _V> class ValOpIterator;
331 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
332 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
335 // Access to set the operands when building the machine instruction
337 void SetMachineOperandVal(unsigned i,
338 MachineOperand::MachineOperandType operandType,
339 Value* V, bool isDef=false, bool isDefAndUse=false);
340 void SetMachineOperandConst(unsigned i,
341 MachineOperand::MachineOperandType operandType,
343 void SetMachineOperandReg(unsigned i, int regNum, bool isDef=false);
345 //===--------------------------------------------------------------------===//
346 // Accessors to add operands when building up machine instructions
349 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
352 void addRegOperand(Value *V, bool isDef=false, bool isDefAndUse=false) {
353 assert(!OperandsComplete() &&
354 "Trying to add an operand to a machine instr that is already done!");
355 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
356 isDef, isDefAndUse));
359 /// addRegOperand - Add a symbolic virtual register reference...
361 void addRegOperand(int reg) {
362 assert(!OperandsComplete() &&
363 "Trying to add an operand to a machine instr that is already done!");
364 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister));
367 /// addPCDispOperand - Add a PC relative displacement operand to the MI
369 void addPCDispOperand(Value *V) {
370 assert(!OperandsComplete() &&
371 "Trying to add an operand to a machine instr that is already done!");
372 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp));
375 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
377 void addMachineRegOperand(int reg, bool isDef=false) {
378 assert(!OperandsComplete() &&
379 "Trying to add an operand to a machine instr that is already done!");
380 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
385 /// addZeroExtImmOperand - Add a zero extended constant argument to the
386 /// machine instruction.
388 void addZeroExtImmOperand(int64_t intValue) {
389 assert(!OperandsComplete() &&
390 "Trying to add an operand to a machine instr that is already done!");
391 operands.push_back(MachineOperand(intValue,
392 MachineOperand::MO_UnextendedImmed));
395 /// addSignExtImmOperand - Add a zero extended constant argument to the
396 /// machine instruction.
398 void addSignExtImmOperand(int64_t intValue) {
399 assert(!OperandsComplete() &&
400 "Trying to add an operand to a machine instr that is already done!");
401 operands.push_back(MachineOperand(intValue,
402 MachineOperand::MO_SignExtendedImmed));
406 unsigned substituteValue(const Value* oldVal, Value* newVal,
407 bool defsOnly = true);
409 void setOperandHi32(unsigned i) { operands[i].markHi32(); }
410 void setOperandLo32(unsigned i) { operands[i].markLo32(); }
411 void setOperandHi64(unsigned i) { operands[i].markHi64(); }
412 void setOperandLo64(unsigned i) { operands[i].markLo64(); }
415 // SetRegForOperand - Replaces the Value for the operand with its allocated
416 // physical register after register allocation is complete.
418 void SetRegForOperand(unsigned i, int regNum);
421 // Iterator to enumerate machine operands.
423 template<class MITy, class VTy>
424 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
428 void skipToNextVal() {
429 while (i < MI->getNumOperands() &&
430 !((MI->getOperandType(i) == MachineOperand::MO_VirtualRegister ||
431 MI->getOperandType(i) == MachineOperand::MO_CCRegister)
432 && MI->getOperand(i).getVRegValue() != 0))
436 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
441 typedef ValOpIterator<MITy, VTy> _Self;
443 inline VTy operator*() const {
444 return MI->getOperand(i).getVRegValue();
447 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
448 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
450 inline VTy operator->() const { return operator*(); }
452 inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
453 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
455 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
456 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
458 inline bool operator==(const _Self &y) const {
461 inline bool operator!=(const _Self &y) const {
462 return !operator==(y);
465 static _Self begin(MITy MI) {
468 static _Self end(MITy MI) {
469 return _Self(MI, MI->getNumOperands());
473 // define begin() and end()
474 val_op_iterator begin() { return val_op_iterator::begin(this); }
475 val_op_iterator end() { return val_op_iterator::end(this); }
477 const_val_op_iterator begin() const {
478 return const_val_op_iterator::begin(this);
480 const_val_op_iterator end() const {
481 return const_val_op_iterator::end(this);
485 //---------------------------------------------------------------------------
487 //---------------------------------------------------------------------------
489 std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
491 std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
493 void PrintMachineInstructions(const Function *F);