1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Annotation.h"
13 #include "Support/iterator"
14 #include "Support/NonCopyable.h"
19 typedef int MachineOpCode;
21 //---------------------------------------------------------------------------
22 // class MachineOperand
25 // Representation of each machine instruction operand.
26 // This class is designed so that you can allocate a vector of operands
27 // first and initialize each one later.
29 // E.g, for this VM instruction:
30 // ptr = alloca type, numElements
31 // we generate 2 machine instructions on the SPARC:
33 // mul Constant, Numelements -> Reg
34 // add %sp, Reg -> Ptr
36 // Each instruction has 3 operands, listed above. Of those:
37 // - Reg, NumElements, and Ptr are of operand type MO_Register.
38 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
40 // For the register operands, the virtual register type is as follows:
42 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
43 // MachineInstr* minstr will point to the instruction that computes reg.
45 // - %sp will be of virtual register type MO_MachineReg.
46 // The field regNum identifies the machine register.
48 // - NumElements will be of virtual register type MO_VirtualReg.
49 // The field Value* value identifies the value.
51 // - Ptr will also be of virtual register type MO_VirtualReg.
52 // Again, the field Value* value identifies the value.
54 //---------------------------------------------------------------------------
56 class MachineOperand {
58 enum MachineOperandType {
59 MO_VirtualRegister, // virtual register for *value
60 MO_MachineRegister, // pre-assigned machine register `regNum'
68 // Bit fields of the flags variable used for different operand properties
69 static const char DEFFLAG = 0x1; // this is a def of the operand
70 static const char DEFUSEFLAG = 0x2; // this is both a def and a use
71 static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal)
72 static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal)
73 static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
74 static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
78 Value* value; // BasicBlockVal for a label operand.
79 // ConstantVal for a non-address immediate.
80 // Virtual register for an SSA operand,
81 // including hidden operands required for
82 // the generated machine code.
83 int64_t immedVal; // constant value for an explicit constant
86 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
87 char flags; // see bit field definitions above
88 int regNum; // register number for an explicit register
89 // will be set for a value after reg allocation
93 opType(MO_VirtualRegister),
97 MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
103 MachineOperand(int Reg, MachineOperandType OpTy, bool isDef = false)
106 flags(isDef ? DEFFLAG : 0),
109 MachineOperand(Value *V, MachineOperandType OpTy,
110 bool isDef = false, bool isDNU = false)
114 flags = (isDef ? DEFFLAG : 0) | (isDNU ? DEFUSEFLAG : 0);
118 MachineOperand(const MachineOperand &M)
119 : immedVal(M.immedVal),
126 // Accessor methods. Caller is responsible for checking the
127 // operand type before invoking the corresponding accessor.
129 MachineOperandType getType() const { return opType; }
131 inline Value* getVRegValue () const {
132 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
133 opType == MO_PCRelativeDisp);
136 inline Value* getVRegValueOrNull() const {
137 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
138 opType == MO_PCRelativeDisp)? value : NULL;
140 inline int getMachineRegNum() const {
141 assert(opType == MO_MachineRegister);
144 inline int64_t getImmedValue () const {
145 assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
148 bool opIsDef () const { return flags & DEFFLAG; }
149 bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
150 bool opHiBits32 () const { return flags & HIFLAG32; }
151 bool opLoBits32 () const { return flags & LOFLAG32; }
152 bool opHiBits64 () const { return flags & HIFLAG64; }
153 bool opLoBits64 () const { return flags & LOFLAG64; }
155 // used to check if a machine register has been allocated to this operand
156 inline bool hasAllocatedReg() const {
157 return (regNum >= 0 &&
158 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
159 opType == MO_MachineRegister));
162 // used to get the reg number if when one is allocated
163 inline int getAllocatedRegNum() const {
164 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
165 opType == MO_MachineRegister);
170 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
174 // Construction methods needed for fine-grain control.
175 // These must be accessed via coresponding methods in MachineInstr.
176 void markDef() { flags |= DEFFLAG; }
177 void markDefAndUse() { flags |= DEFUSEFLAG; }
178 void markHi32() { flags |= HIFLAG32; }
179 void markLo32() { flags |= LOFLAG32; }
180 void markHi64() { flags |= HIFLAG64; }
181 void markLo64() { flags |= LOFLAG64; }
183 // Replaces the Value with its corresponding physical register after
184 // register allocation is complete
185 void setRegForValue(int reg) {
186 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
187 opType == MO_MachineRegister);
191 friend class MachineInstr;
195 //---------------------------------------------------------------------------
196 // class MachineInstr
199 // Representation of each machine instruction.
201 // MachineOpCode must be an enum, defined separately for each target.
202 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
204 // There are 2 kinds of operands:
206 // (1) Explicit operands of the machine instruction in vector operands[]
208 // (2) "Implicit operands" are values implicitly used or defined by the
209 // machine instruction, such as arguments to a CALL, return value of
210 // a CALL (if any), and return value of a RETURN.
211 //---------------------------------------------------------------------------
213 class MachineInstr: public NonCopyable { // Disable copy operations
215 MachineOpCode opCode; // the opcode
216 std::vector<MachineOperand> operands; // the operands
217 unsigned numImplicitRefs; // number of implicit operands
219 MachineOperand& getImplicitOp(unsigned i) {
220 assert(i < numImplicitRefs && "implicit ref# out of range!");
221 return operands[i + operands.size() - numImplicitRefs];
223 const MachineOperand& getImplicitOp(unsigned i) const {
224 assert(i < numImplicitRefs && "implicit ref# out of range!");
225 return operands[i + operands.size() - numImplicitRefs];
228 // regsUsed - all machine registers used for this instruction, including regs
229 // used to save values across the instruction. This is a bitset of registers.
230 std::vector<bool> regsUsed;
232 // OperandComplete - Return true if it's illegal to add a new operand
233 bool OperandsComplete() const;
236 MachineInstr(MachineOpCode Opcode);
237 MachineInstr(MachineOpCode Opcode, unsigned numOperands);
239 /// MachineInstr ctor - This constructor only does a _reserve_ of the
240 /// operands, not a resize for them. It is expected that if you use this that
241 /// you call add* methods below to fill up the operands, instead of the Set
244 MachineInstr(MachineOpCode Opcode, unsigned numOperands, bool XX, bool YY);
247 // Support to rewrite a machine instruction in place: for now, simply
248 // replace() and then set new operands with Set.*Operand methods below.
250 void replace(MachineOpCode Opcode, unsigned numOperands);
255 const MachineOpCode getOpCode() const { return opCode; }
258 // Information about explicit operands of the instruction
260 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
262 const MachineOperand& getOperand(unsigned i) const {
263 assert(i < getNumOperands() && "getOperand() out of range!");
266 MachineOperand& getOperand(unsigned i) {
267 assert(i < getNumOperands() && "getOperand() out of range!");
271 MachineOperand::MachineOperandType getOperandType(unsigned i) const {
272 return getOperand(i).getType();
275 bool operandIsDefined(unsigned i) const {
276 return getOperand(i).opIsDef();
279 bool operandIsDefinedAndUsed(unsigned i) const {
280 return getOperand(i).opIsDefAndUse();
284 // Information about implicit operands of the instruction
286 unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
288 const Value* getImplicitRef(unsigned i) const {
289 return getImplicitOp(i).getVRegValue();
291 Value* getImplicitRef(unsigned i) {
292 return getImplicitOp(i).getVRegValue();
295 bool implicitRefIsDefined(unsigned i) const {
296 return getImplicitOp(i).opIsDef();
298 bool implicitRefIsDefinedAndUsed(unsigned i) const {
299 return getImplicitOp(i).opIsDefAndUse();
301 inline void addImplicitRef (Value* V,
302 bool isDef=false,bool isDefAndUse=false);
303 inline void setImplicitRef (unsigned i, Value* V,
304 bool isDef=false, bool isDefAndUse=false);
307 // Information about registers used in this instruction
309 const std::vector<bool> &getRegsUsed() const { return regsUsed; }
311 // insertUsedReg - Add a register to the Used registers set...
312 void insertUsedReg(unsigned Reg) {
313 if (Reg >= regsUsed.size())
314 regsUsed.resize(Reg+1);
315 regsUsed[Reg] = true;
322 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
325 // Define iterators to access the Value operands of the Machine Instruction.
326 // Note that these iterators only enumerate the explicit operands.
327 // begin() and end() are defined to produce these iterators...
329 template<class _MI, class _V> class ValOpIterator;
330 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
331 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
333 // Access to set the operands when building the machine instruction
335 void SetMachineOperandVal (unsigned i,
336 MachineOperand::MachineOperandType operandType,
339 bool isDefAndUse=false);
341 void SetMachineOperandConst (unsigned i,
342 MachineOperand::MachineOperandType operandType,
345 void SetMachineOperandReg (unsigned i,
349 //===--------------------------------------------------------------------===//
350 // Accessors to add operands when building up machine instructions
353 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
356 void addRegOperand(Value *V, bool isDef=false, bool isDefAndUse=false) {
357 assert(!OperandsComplete() &&
358 "Trying to add an operand to a machine instr that is already done!");
359 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
360 isDef, isDefAndUse));
363 /// addRegOperand - Add a symbolic virtual register reference...
365 void addRegOperand(int reg) {
366 assert(!OperandsComplete() &&
367 "Trying to add an operand to a machine instr that is already done!");
368 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister));
371 /// addPCDispOperand - Add a PC relative displacement operand to the MI
373 void addPCDispOperand(Value *V) {
374 assert(!OperandsComplete() &&
375 "Trying to add an operand to a machine instr that is already done!");
376 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp));
379 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
381 void addMachineRegOperand(int reg, bool isDef=false) {
382 assert(!OperandsComplete() &&
383 "Trying to add an operand to a machine instr that is already done!");
384 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
389 /// addZeroExtImmOperand - Add a zero extended constant argument to the
390 /// machine instruction.
392 void addZeroExtImmOperand(int64_t intValue) {
393 assert(!OperandsComplete() &&
394 "Trying to add an operand to a machine instr that is already done!");
395 operands.push_back(MachineOperand(intValue,
396 MachineOperand::MO_UnextendedImmed));
399 /// addSignExtImmOperand - Add a zero extended constant argument to the
400 /// machine instruction.
402 void addSignExtImmOperand(int64_t intValue) {
403 assert(!OperandsComplete() &&
404 "Trying to add an operand to a machine instr that is already done!");
405 operands.push_back(MachineOperand(intValue,
406 MachineOperand::MO_SignExtendedImmed));
410 unsigned substituteValue(const Value* oldVal, Value* newVal,
411 bool defsOnly = true);
413 void setOperandHi32(unsigned i) { operands[i].markHi32(); }
414 void setOperandLo32(unsigned i) { operands[i].markLo32(); }
415 void setOperandHi64(unsigned i) { operands[i].markHi64(); }
416 void setOperandLo64(unsigned i) { operands[i].markLo64(); }
419 // SetRegForOperand - Replaces the Value for the operand with its allocated
420 // physical register after register allocation is complete.
422 void SetRegForOperand(unsigned i, int regNum);
425 // Iterator to enumerate machine operands.
427 template<class MITy, class VTy>
428 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
432 void skipToNextVal() {
433 while (i < MI->getNumOperands() &&
434 !( (MI->getOperandType(i) == MachineOperand::MO_VirtualRegister ||
435 MI->getOperandType(i) == MachineOperand::MO_CCRegister)
436 && MI->getOperand(i).getVRegValue() != 0))
440 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
445 typedef ValOpIterator<MITy, VTy> _Self;
447 inline VTy operator*() const {
448 return MI->getOperand(i).getVRegValue();
451 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
452 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
454 inline VTy operator->() const { return operator*(); }
456 inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
457 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
459 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
460 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
462 inline bool operator==(const _Self &y) const {
465 inline bool operator!=(const _Self &y) const {
466 return !operator==(y);
469 static _Self begin(MITy MI) {
472 static _Self end(MITy MI) {
473 return _Self(MI, MI->getNumOperands());
477 // define begin() and end()
478 val_op_iterator begin() { return val_op_iterator::begin(this); }
479 val_op_iterator end() { return val_op_iterator::end(this); }
481 const_val_op_iterator begin() const {
482 return const_val_op_iterator::begin(this);
484 const_val_op_iterator end() const {
485 return const_val_op_iterator::end(this);
490 // Define here to enable inlining of the functions used.
492 void MachineInstr::addImplicitRef(Value* V,
497 addRegOperand(V, isDef, isDefAndUse);
500 void MachineInstr::setImplicitRef(unsigned i,
505 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
506 SetMachineOperandVal(i + getNumImplicitRefs(),
507 MachineOperand::MO_VirtualRegister,
508 V, isDef, isDefAndUse);
512 //---------------------------------------------------------------------------
514 //---------------------------------------------------------------------------
516 std::ostream& operator<< (std::ostream& os,
517 const MachineInstr& minstr);
519 std::ostream& operator<< (std::ostream& os,
520 const MachineOperand& mop);
522 void PrintMachineInstructions (const Function *F);