1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Annotation.h"
13 #include "Support/iterator"
14 #include "Support/NonCopyable.h"
19 typedef int MachineOpCode;
21 //---------------------------------------------------------------------------
22 // class MachineOperand
25 // Representation of each machine instruction operand.
26 // This class is designed so that you can allocate a vector of operands
27 // first and initialize each one later.
29 // E.g, for this VM instruction:
30 // ptr = alloca type, numElements
31 // we generate 2 machine instructions on the SPARC:
33 // mul Constant, Numelements -> Reg
34 // add %sp, Reg -> Ptr
36 // Each instruction has 3 operands, listed above. Of those:
37 // - Reg, NumElements, and Ptr are of operand type MO_Register.
38 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
40 // For the register operands, the virtual register type is as follows:
42 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
43 // MachineInstr* minstr will point to the instruction that computes reg.
45 // - %sp will be of virtual register type MO_MachineReg.
46 // The field regNum identifies the machine register.
48 // - NumElements will be of virtual register type MO_VirtualReg.
49 // The field Value* value identifies the value.
51 // - Ptr will also be of virtual register type MO_VirtualReg.
52 // Again, the field Value* value identifies the value.
54 //---------------------------------------------------------------------------
56 class MachineOperand {
58 enum MachineOperandType {
59 MO_VirtualRegister, // virtual register for *value
60 MO_MachineRegister, // pre-assigned machine register `regNum'
68 // Bit fields of the flags variable used for different operand properties
69 static const char DEFFLAG = 0x1; // this is a def of the operand
70 static const char DEFUSEFLAG = 0x2; // this is both a def and a use
71 static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal)
72 static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal)
73 static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
74 static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
78 Value* value; // BasicBlockVal for a label operand.
79 // ConstantVal for a non-address immediate.
80 // Virtual register for an SSA operand,
81 // including hidden operands required for
82 // the generated machine code.
83 int64_t immedVal; // constant value for an explicit constant
86 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
87 char flags; // see bit field definitions above
88 int regNum; // register number for an explicit register
89 // will be set for a value after reg allocation
92 : immedVal(0), opType(MO_VirtualRegister), flags(0), regNum(-1) {}
93 MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
94 : immedVal(ImmVal), opType(OpTy), flags(0), regNum(-1) {}
95 MachineOperand(int Reg, MachineOperandType OpTy, bool isDef = false)
96 : immedVal(0), opType(OpTy), flags(isDef ? DEFFLAG : 0), regNum(Reg) {}
97 MachineOperand(Value *V, MachineOperandType OpTy,
98 bool isDef = false, bool isDNU = false)
99 : value(V), opType(OpTy), regNum(-1) {
100 flags = (isDef ? DEFFLAG : 0) | (isDNU ? DEFUSEFLAG : 0);
104 MachineOperand(const MachineOperand &M)
105 : immedVal(M.immedVal), opType(M.opType), flags(M.flags), regNum(M.regNum) {
109 // Accessor methods. Caller is responsible for checking the
110 // operand type before invoking the corresponding accessor.
112 MachineOperandType getType() const { return opType; }
114 inline Value* getVRegValue () const {
115 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
116 opType == MO_PCRelativeDisp);
119 inline Value* getVRegValueOrNull() const {
120 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
121 opType == MO_PCRelativeDisp)? value : NULL;
123 inline int getMachineRegNum() const {
124 assert(opType == MO_MachineRegister);
127 inline int64_t getImmedValue () const {
128 assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
131 bool opIsDef () const { return flags & DEFFLAG; }
132 bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
133 bool opHiBits32 () const { return flags & HIFLAG32; }
134 bool opLoBits32 () const { return flags & LOFLAG32; }
135 bool opHiBits64 () const { return flags & HIFLAG64; }
136 bool opLoBits64 () const { return flags & LOFLAG64; }
138 // used to check if a machine register has been allocated to this operand
139 inline bool hasAllocatedReg() const {
140 return (regNum >= 0 &&
141 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
142 opType == MO_MachineRegister));
145 // used to get the reg number if when one is allocated
146 inline int getAllocatedRegNum() const {
147 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
148 opType == MO_MachineRegister);
153 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
157 // Construction methods needed for fine-grain control.
158 // These must be accessed via coresponding methods in MachineInstr.
159 void markDef() { flags |= DEFFLAG; }
160 void markDefAndUse() { flags |= DEFUSEFLAG; }
161 void markHi32() { flags |= HIFLAG32; }
162 void markLo32() { flags |= LOFLAG32; }
163 void markHi64() { flags |= HIFLAG64; }
164 void markLo64() { flags |= LOFLAG64; }
166 // Replaces the Value with its corresponding physical register after
167 // register allocation is complete
168 void setRegForValue(int reg) {
169 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
170 opType == MO_MachineRegister);
174 friend class MachineInstr;
178 //---------------------------------------------------------------------------
179 // class MachineInstr
182 // Representation of each machine instruction.
184 // MachineOpCode must be an enum, defined separately for each target.
185 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
187 // There are 2 kinds of operands:
189 // (1) Explicit operands of the machine instruction in vector operands[]
191 // (2) "Implicit operands" are values implicitly used or defined by the
192 // machine instruction, such as arguments to a CALL, return value of
193 // a CALL (if any), and return value of a RETURN.
194 //---------------------------------------------------------------------------
196 class MachineInstr : public Annotable, // MachineInstrs are annotable
197 public NonCopyable { // Disable copy operations
198 MachineOpCode opCode; // the opcode
199 std::vector<MachineOperand> operands; // the operands
203 bool isDef, isDefAndUse;
205 ImplicitRef(Value *V, bool D, bool DU) : Val(V), isDef(D), isDefAndUse(DU){}
208 // implicitRefs - Values implicitly referenced by this machine instruction
210 std::vector<ImplicitRef> implicitRefs;
212 // regsUsed - all machine registers used for this instruction, including regs
213 // used to save values across the instruction. This is a bitset of registers.
214 std::vector<bool> regsUsed;
216 // OperandComplete - Return true if it's illegal to add a new operand
217 bool OperandsComplete() const;
219 MachineInstr(MachineOpCode Opcode);
220 MachineInstr(MachineOpCode Opcode, unsigned numOperands);
222 /// MachineInstr ctor - This constructor only does a _reserve_ of the
223 /// operands, not a resize for them. It is expected that if you use this that
224 /// you call add* methods below to fill up the operands, instead of the Set
227 MachineInstr(MachineOpCode Opcode, unsigned numOperands, bool XX, bool YY);
230 // Support to rewrite a machine instruction in place: for now, simply
231 // replace() and then set new operands with Set.*Operand methods below.
233 void replace(MachineOpCode Opcode, unsigned numOperands);
238 const MachineOpCode getOpCode() const { return opCode; }
241 // Information about explicit operands of the instruction
243 unsigned getNumOperands() const { return operands.size(); }
245 const MachineOperand& getOperand(unsigned i) const {
246 assert(i < operands.size() && "getOperand() out of range!");
249 MachineOperand& getOperand(unsigned i) {
250 assert(i < operands.size() && "getOperand() out of range!");
254 MachineOperand::MachineOperandType getOperandType(unsigned i) const {
255 return getOperand(i).getType();
258 bool operandIsDefined(unsigned i) const {
259 return getOperand(i).opIsDef();
262 bool operandIsDefinedAndUsed(unsigned i) const {
263 return getOperand(i).opIsDefAndUse();
267 // Information about implicit operands of the instruction
269 unsigned getNumImplicitRefs() const{ return implicitRefs.size();}
271 const Value* getImplicitRef(unsigned i) const {
272 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
273 return implicitRefs[i].Val;
275 Value* getImplicitRef(unsigned i) {
276 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
277 return implicitRefs[i].Val;
280 bool implicitRefIsDefined(unsigned i) const {
281 assert(i < implicitRefs.size() && "implicitRefIsDefined() out of range!");
282 return implicitRefs[i].isDef;
284 bool implicitRefIsDefinedAndUsed(unsigned i) const {
285 assert(i < implicitRefs.size() && "implicitRefIsDef&Used() out of range!");
286 return implicitRefs[i].isDefAndUse;
289 void addImplicitRef(Value* V, bool isDef=false, bool isDefAndUse=false) {
290 implicitRefs.push_back(ImplicitRef(V, isDef, isDefAndUse));
293 void setImplicitRef(unsigned i, Value* V, bool isDef=false,
294 bool isDefAndUse=false) {
295 assert(i < implicitRefs.size() && "setImplicitRef() out of range!");
296 implicitRefs[i] = ImplicitRef(V, isDef, isDefAndUse);
300 // Information about registers used in this instruction
302 const std::vector<bool> &getRegsUsed() const { return regsUsed; }
304 // insertUsedReg - Add a register to the Used registers set...
305 void insertUsedReg(unsigned Reg) {
306 if (Reg >= regsUsed.size())
307 regsUsed.resize(Reg+1);
308 regsUsed[Reg] = true;
315 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
318 // Define iterators to access the Value operands of the Machine Instruction.
319 // begin() and end() are defined to produce these iterators...
321 template<class _MI, class _V> class ValOpIterator;
322 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
323 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
326 // Access to set the operands when building the machine instruction
328 void SetMachineOperandVal(unsigned i,
329 MachineOperand::MachineOperandType operandType,
330 Value* V, bool isDef=false, bool isDefAndUse=false);
331 void SetMachineOperandConst(unsigned i,
332 MachineOperand::MachineOperandType operandType,
334 void SetMachineOperandReg(unsigned i, int regNum, bool isDef=false);
336 //===--------------------------------------------------------------------===//
337 // Accessors to add operands when building up machine instructions
340 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
343 void addRegOperand(Value *V, bool isDef=false, bool isDefAndUse=false) {
344 assert(!OperandsComplete() &&
345 "Trying to add an operand to a machine instr that is already done!");
346 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
347 isDef, isDefAndUse));
350 /// addRegOperand - Add a symbolic virtual register reference...
352 void addRegOperand(int reg) {
353 assert(!OperandsComplete() &&
354 "Trying to add an operand to a machine instr that is already done!");
355 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister));
358 /// addPCDispOperand - Add a PC relative displacement operand to the MI
360 void addPCDispOperand(Value *V) {
361 assert(!OperandsComplete() &&
362 "Trying to add an operand to a machine instr that is already done!");
363 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp));
366 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
368 void addMachineRegOperand(int reg, bool isDef=false) {
369 assert(!OperandsComplete() &&
370 "Trying to add an operand to a machine instr that is already done!");
371 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
376 /// addZeroExtImmOperand - Add a zero extended constant argument to the
377 /// machine instruction.
379 void addZeroExtImmOperand(int64_t intValue) {
380 assert(!OperandsComplete() &&
381 "Trying to add an operand to a machine instr that is already done!");
382 operands.push_back(MachineOperand(intValue,
383 MachineOperand::MO_UnextendedImmed));
386 /// addSignExtImmOperand - Add a zero extended constant argument to the
387 /// machine instruction.
389 void addSignExtImmOperand(int64_t intValue) {
390 assert(!OperandsComplete() &&
391 "Trying to add an operand to a machine instr that is already done!");
392 operands.push_back(MachineOperand(intValue,
393 MachineOperand::MO_SignExtendedImmed));
397 unsigned substituteValue(const Value* oldVal, Value* newVal,
398 bool defsOnly = true);
400 void setOperandHi32(unsigned i) { operands[i].markHi32(); }
401 void setOperandLo32(unsigned i) { operands[i].markLo32(); }
402 void setOperandHi64(unsigned i) { operands[i].markHi64(); }
403 void setOperandLo64(unsigned i) { operands[i].markLo64(); }
406 // SetRegForOperand - Replaces the Value for the operand with its allocated
407 // physical register after register allocation is complete.
409 void SetRegForOperand(unsigned i, int regNum);
412 // Iterator to enumerate machine operands.
414 template<class MITy, class VTy>
415 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
419 void skipToNextVal() {
420 while (i < MI->getNumOperands() &&
421 !((MI->getOperandType(i) == MachineOperand::MO_VirtualRegister ||
422 MI->getOperandType(i) == MachineOperand::MO_CCRegister)
423 && MI->getOperand(i).getVRegValue() != 0))
427 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
432 typedef ValOpIterator<MITy, VTy> _Self;
434 inline VTy operator*() const {
435 return MI->getOperand(i).getVRegValue();
438 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
439 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
441 inline VTy operator->() const { return operator*(); }
443 inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
444 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
446 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
447 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
449 inline bool operator==(const _Self &y) const {
452 inline bool operator!=(const _Self &y) const {
453 return !operator==(y);
456 static _Self begin(MITy MI) {
459 static _Self end(MITy MI) {
460 return _Self(MI, MI->getNumOperands());
464 // define begin() and end()
465 val_op_iterator begin() { return val_op_iterator::begin(this); }
466 val_op_iterator end() { return val_op_iterator::end(this); }
468 const_val_op_iterator begin() const {
469 return const_val_op_iterator::begin(this);
471 const_val_op_iterator end() const {
472 return const_val_op_iterator::end(this);
476 //---------------------------------------------------------------------------
478 //---------------------------------------------------------------------------
480 std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
482 std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
484 void PrintMachineInstructions(const Function *F);