2 //***************************************************************************
12 // 7/2/01 - Vikram Adve - Created
13 //**************************************************************************/
15 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
16 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/InstrForest.h"
20 #include "llvm/Support/DataTypes.h"
21 #include "llvm/Support/NonCopyable.h"
22 #include "llvm/CodeGen/TargetMachine.h"
24 template<class _MI, class _V> class ValOpIterator;
27 //---------------------------------------------------------------------------
28 // class MachineOperand
31 // Representation of each machine instruction operand.
32 // This class is designed so that you can allocate a vector of operands
33 // first and initialize each one later.
35 // E.g, for this VM instruction:
36 // ptr = alloca type, numElements
37 // we generate 2 machine instructions on the SPARC:
39 // mul Constant, Numelements -> Reg
40 // add %sp, Reg -> Ptr
42 // Each instruction has 3 operands, listed above. Of those:
43 // - Reg, NumElements, and Ptr are of operand type MO_Register.
44 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
46 // For the register operands, the virtual register type is as follows:
48 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
49 // MachineInstr* minstr will point to the instruction that computes reg.
51 // - %sp will be of virtual register type MO_MachineReg.
52 // The field regNum identifies the machine register.
54 // - NumElements will be of virtual register type MO_VirtualReg.
55 // The field Value* value identifies the value.
57 // - Ptr will also be of virtual register type MO_VirtualReg.
58 // Again, the field Value* value identifies the value.
60 //---------------------------------------------------------------------------
62 class MachineOperand {
64 enum MachineOperandType {
65 MO_VirtualRegister, // virtual register for *value
66 MO_MachineRegister, // pre-assigned machine register `regNum'
74 MachineOperandType opType;
77 Value* value; // BasicBlockVal for a label operand.
78 // ConstantVal for a non-address immediate.
79 // Virtual register for an SSA operand,
80 // including hidden operands required for
81 // the generated machine code.
83 unsigned int regNum; // register number for an explicit register
85 int64_t immedVal; // constant value for an explicit constant
88 bool isDef; // is this a defition for the value
89 // made public for faster access
92 /*ctor*/ MachineOperand ();
93 /*ctor*/ MachineOperand (MachineOperandType operandType,
95 /*copy ctor*/ MachineOperand (const MachineOperand&);
96 /*dtor*/ ~MachineOperand () {}
98 // Accessor methods. Caller is responsible for checking the
99 // operand type before invoking the corresponding accessor.
101 inline MachineOperandType getOperandType () const {
104 inline Value* getVRegValue () const {
105 assert(opType == MO_VirtualRegister || opType == MO_CCRegister);
108 inline unsigned int getMachineRegNum() const {
109 assert(opType == MO_MachineRegister);
112 inline int64_t getImmedValue () const {
113 assert(opType >= MO_SignExtendedImmed || opType <= MO_PCRelativeDisp);
116 inline bool opIsDef () const {
121 friend ostream& operator<<(ostream& os, const MachineOperand& mop);
125 // These functions are provided so that a vector of operands can be
126 // statically allocated and individual ones can be initialized later.
127 // Give class MachineInstr gets access to these functions.
129 void Initialize (MachineOperandType operandType,
131 void InitializeConst (MachineOperandType operandType,
133 void InitializeReg (unsigned int regNum);
135 friend class MachineInstr;
136 friend class ValOpIterator<const MachineInstr, const Value>;
137 friend class ValOpIterator< MachineInstr, Value>;
142 // this replaces a value with a register after register allcoation
143 void setRegForValue(int Reg) {
144 assert(opType == MO_VirtualRegister || opType == MO_CCRegister);
145 opType = MO_MachineRegister;
153 MachineOperand::MachineOperand()
154 : opType(MO_VirtualRegister),
162 MachineOperand::MachineOperand(MachineOperandType operandType,
164 : opType(operandType),
172 MachineOperand::MachineOperand(const MachineOperand& mo)
177 case MO_VirtualRegister:
178 case MO_CCRegister: value = mo.value; break;
179 case MO_MachineRegister: regNum = mo.regNum; break;
180 case MO_SignExtendedImmed:
181 case MO_UnextendedImmed:
182 case MO_PCRelativeDisp: immedVal = mo.immedVal; break;
188 MachineOperand::Initialize(MachineOperandType operandType,
191 opType = operandType;
196 MachineOperand::InitializeConst(MachineOperandType operandType,
199 opType = operandType;
205 MachineOperand::InitializeReg(unsigned int _regNum)
207 opType = MO_MachineRegister;
213 //---------------------------------------------------------------------------
214 // class MachineInstr
217 // Representation of each machine instruction.
219 // MachineOpCode must be an enum, defined separately for each target.
220 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
222 // opCodeMask is used to record variants of an instruction.
223 // E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
224 // ANNUL: if 1: Annul delay slot instruction.
225 // PREDICT-NOT-TAKEN: if 1: predict branch not taken.
226 // Instead of creating 4 different opcodes for BNZ, we create a single
227 // opcode and set bits in opCodeMask for each of these flags.
228 //---------------------------------------------------------------------------
230 class MachineInstr : public NonCopyable {
232 MachineOpCode opCode;
233 OpCodeMask opCodeMask; // extra bits for variants of an opcode
234 vector<MachineOperand> operands;
237 typedef ValOpIterator<const MachineInstr, const Value> val_op_const_iterator;
238 typedef ValOpIterator< MachineInstr, Value> val_op_iterator;
241 /*ctor*/ MachineInstr (MachineOpCode _opCode,
242 OpCodeMask _opCodeMask = 0x0);
243 /*ctor*/ MachineInstr (MachineOpCode _opCode,
244 unsigned numOperands,
245 OpCodeMask _opCodeMask = 0x0);
246 inline ~MachineInstr () {}
248 const MachineOpCode getOpCode () const;
250 unsigned int getNumOperands () const;
252 const MachineOperand& getOperand (unsigned int i) const;
253 MachineOperand& getOperand (unsigned int i);
255 bool operandIsDefined(unsigned int i) const;
257 void dump (unsigned int indent = 0) const;
264 friend ostream& operator<<(ostream& os, const MachineInstr& minstr);
265 friend val_op_const_iterator;
266 friend val_op_iterator;
269 // Access to set the operands when building the machine instruction
270 void SetMachineOperand(unsigned int i,
271 MachineOperand::MachineOperandType operandType,
272 Value* _val, bool isDef=false);
273 void SetMachineOperand(unsigned int i,
274 MachineOperand::MachineOperandType operandType,
275 int64_t intValue, bool isDef=false);
276 void SetMachineOperand(unsigned int i,
281 inline const MachineOpCode
282 MachineInstr::getOpCode() const
288 MachineInstr::getNumOperands() const
290 return operands.size();
293 inline MachineOperand&
294 MachineInstr::getOperand(unsigned int i)
296 assert(i < operands.size() && "getOperand() out of range!");
300 inline const MachineOperand&
301 MachineInstr::getOperand(unsigned int i) const
303 assert(i < operands.size() && "getOperand() out of range!");
308 MachineInstr::operandIsDefined(unsigned int i) const
310 return getOperand(i).opIsDef();
314 template<class _MI, class _V>
315 class ValOpIterator : public std::forward_iterator<_V, ptrdiff_t> {
321 inline void skipToNextVal() {
322 while (i < minstr->getNumOperands() &&
323 ! ((minstr->operands[i].opType == MachineOperand::MO_VirtualRegister
324 || minstr->operands[i].opType == MachineOperand::MO_CCRegister)
325 && minstr->operands[i].value != NULL))
330 typedef ValOpIterator<_MI, _V> _Self;
332 inline ValOpIterator(_MI* _minstr) : i(0), minstr(_minstr) {
333 resultPos = TargetInstrDescriptors[minstr->opCode].resultPos;
337 inline _V* operator*() const { return minstr->getOperand(i).getVRegValue();}
338 inline _V* operator->() const { return operator*(); }
339 // inline bool isDef () const { return (((int) i) == resultPos); }
341 inline bool isDef () const { return minstr->getOperand(i).isDef; }
342 inline bool done () const { return (i == minstr->getNumOperands()); }
344 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
345 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
349 //---------------------------------------------------------------------------
350 // class MachineCodeForVMInstr
353 // Representation of the sequence of machine instructions created
354 // for a single VM instruction. Additionally records any temporary
355 // "values" used as intermediate values in this sequence.
356 // Note that such values should be treated as pure SSA values with
357 // no interpretation of their operands (i.e., as a TmpInstruction object
358 // which actually represents such a value).
360 //---------------------------------------------------------------------------
362 class MachineCodeForVMInstr: public vector<MachineInstr*>
365 vector<Value*> tempVec;
368 /*ctor*/ MachineCodeForVMInstr () {}
369 /*ctor*/ ~MachineCodeForVMInstr ();
371 const vector<Value*>&
372 getTempValues () const { return tempVec; }
374 void addTempValue (Value* val)
375 { tempVec.push_back(val); }
377 // dropAllReferences() - This function drops all references within
378 // temporary (hidden) instructions created in implementing the original
379 // VM intruction. This ensures there are no remaining "uses" within
380 // these hidden instructions, before the values of a method are freed.
382 // Make this inline because it has to be called from class Instruction
383 // and inlining it avoids a serious circurality in link order.
384 inline void dropAllReferences() {
385 for (unsigned i=0, N=tempVec.size(); i < N; i++)
386 if (tempVec[i]->getValueType() == Value::InstructionVal)
387 ((Instruction*) tempVec[i])->dropAllReferences();
392 MachineCodeForVMInstr::~MachineCodeForVMInstr()
394 // Free the Value objects created to hold intermediate values
395 for (unsigned i=0, N=tempVec.size(); i < N; i++)
398 // Free the MachineInstr objects allocated, if any.
399 for (unsigned i=0, N=this->size(); i < N; i++)
404 //---------------------------------------------------------------------------
405 // class MachineCodeForBasicBlock
408 // Representation of the sequence of machine instructions created
409 // for a basic block.
410 //---------------------------------------------------------------------------
413 class MachineCodeForBasicBlock: public vector<MachineInstr*> {
415 typedef vector<MachineInstr*>::iterator iterator;
416 typedef vector<MachineInstr*>::const_iterator const_iterator;
420 //---------------------------------------------------------------------------
421 // Target-independent utility routines for creating machine instructions
422 //---------------------------------------------------------------------------
425 //------------------------------------------------------------------------
426 // Function Set2OperandsFromInstr
427 // Function Set3OperandsFromInstr
429 // For the common case of 2- and 3-operand arithmetic/logical instructions,
430 // set the m/c instr. operands directly from the VM instruction's operands.
431 // Check whether the first or second operand is 0 and can use a dedicated
433 // Check whether the second operand should use an immediate field or register.
434 // (First and third operands are never immediates for such instructions.)
437 // canDiscardResult: Specifies that the result operand can be discarded
438 // by using the dedicated "0"
440 // op1position, op2position and resultPosition: Specify in which position
441 // in the machine instruction the 3 operands (arg1, arg2
442 // and result) should go.
444 // RETURN VALUE: unsigned int flags, where
445 // flags & 0x01 => operand 1 is constant and needs a register
446 // flags & 0x02 => operand 2 is constant and needs a register
447 //------------------------------------------------------------------------
449 void Set2OperandsFromInstr (MachineInstr* minstr,
450 InstructionNode* vmInstrNode,
451 const TargetMachine& targetMachine,
452 bool canDiscardResult = false,
454 int resultPosition = 1);
456 void Set3OperandsFromInstr (MachineInstr* minstr,
457 InstructionNode* vmInstrNode,
458 const TargetMachine& targetMachine,
459 bool canDiscardResult = false,
462 int resultPosition = 2);
464 MachineOperand::MachineOperandType
465 ChooseRegOrImmed(Value* val,
466 MachineOpCode opCode,
467 const TargetMachine& targetMachine,
469 unsigned int& getMachineRegNum,
470 int64_t& getImmedValue);
473 ostream& operator<<(ostream& os, const MachineInstr& minstr);
476 ostream& operator<<(ostream& os, const MachineOperand& mop);
479 void PrintMachineInstructions (const Method *const method);
482 //**************************************************************************/