1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
24 class TargetInstrDesc;
25 class TargetInstrInfo;
26 class TargetRegisterInfo;
28 template <typename T> struct ilist_traits;
29 template <typename T> struct ilist;
31 //===----------------------------------------------------------------------===//
32 /// MachineInstr - Representation of each machine instruction.
35 const TargetInstrDesc *TID; // Instruction descriptor.
36 unsigned short NumImplicitOps; // Number of implicit operands (which
37 // are determined at construction time).
39 std::vector<MachineOperand> Operands; // the operands
40 std::vector<MachineMemOperand> MemOperands;// information on memory references
41 MachineInstr *Prev, *Next; // Links for MBB's intrusive list.
42 MachineBasicBlock *Parent; // Pointer to the owning basic block.
44 // OperandComplete - Return true if it's illegal to add a new operand
45 bool OperandsComplete() const;
47 MachineInstr(const MachineInstr&);
48 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
50 // Intrusive list support
51 friend struct ilist_traits<MachineInstr>;
52 friend struct ilist_traits<MachineBasicBlock>;
53 void setParent(MachineBasicBlock *P) { Parent = P; }
55 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
56 /// TID NULL and no operands.
59 /// MachineInstr ctor - This constructor create a MachineInstr and add the
60 /// implicit operands. It reserves space for number of operands specified by
62 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
64 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
65 /// the MachineInstr is created and added to the end of the specified basic
68 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
72 const MachineBasicBlock* getParent() const { return Parent; }
73 MachineBasicBlock* getParent() { return Parent; }
75 /// getDesc - Returns the target instruction descriptor of this
77 const TargetInstrDesc &getDesc() const { return *TID; }
79 /// getOpcode - Returns the opcode of this MachineInstr.
81 int getOpcode() const;
83 /// Access to explicit operands of the instruction.
85 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
87 const MachineOperand& getOperand(unsigned i) const {
88 assert(i < getNumOperands() && "getOperand() out of range!");
91 MachineOperand& getOperand(unsigned i) {
92 assert(i < getNumOperands() && "getOperand() out of range!");
96 /// getNumExplicitOperands - Returns the number of non-implicit operands.
98 unsigned getNumExplicitOperands() const;
100 /// Access to memory operands of the instruction
101 unsigned getNumMemOperands() const { return (unsigned)MemOperands.size(); }
103 const MachineMemOperand& getMemOperand(unsigned i) const {
104 assert(i < getNumMemOperands() && "getMemOperand() out of range!");
105 return MemOperands[i];
107 MachineMemOperand& getMemOperand(unsigned i) {
108 assert(i < getNumMemOperands() && "getMemOperand() out of range!");
109 return MemOperands[i];
112 /// isIdenticalTo - Return true if this instruction is identical to (same
113 /// opcode and same operands as) the specified instruction.
114 bool isIdenticalTo(const MachineInstr *Other) const {
115 if (Other->getOpcode() != getOpcode() ||
116 Other->getNumOperands() != getNumOperands())
118 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
119 if (!getOperand(i).isIdenticalTo(Other->getOperand(i)))
124 /// clone - Create a copy of 'this' instruction that is identical in
125 /// all ways except the the instruction has no parent, prev, or next.
126 MachineInstr* clone() const { return new MachineInstr(*this); }
128 /// removeFromParent - This method unlinks 'this' from the containing basic
129 /// block, and returns it, but does not delete it.
130 MachineInstr *removeFromParent();
132 /// eraseFromParent - This method unlinks 'this' from the containing basic
133 /// block and deletes it.
134 void eraseFromParent() {
135 delete removeFromParent();
138 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
140 bool isDebugLabel() const;
142 /// readsRegister - Return true if the MachineInstr reads the specified
143 /// register. If TargetRegisterInfo is passed, then it also checks if there
144 /// is a read of a super-register.
145 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
146 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
149 /// killsRegister - Return true if the MachineInstr kills the specified
150 /// register. If TargetRegisterInfo is passed, then it also checks if there is
151 /// a kill of a super-register.
152 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
153 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
156 /// modifiesRegister - Return true if the MachineInstr modifies the
157 /// specified register. If TargetRegisterInfo is passed, then it also checks
158 /// if there is a def of a super-register.
159 bool modifiesRegister(unsigned Reg,
160 const TargetRegisterInfo *TRI = NULL) const {
161 return findRegisterDefOperandIdx(Reg, false, TRI) != -1;
164 /// registerDefIsDead - Returns true if the register is dead in this machine
165 /// instruction. If TargetRegisterInfo is passed, then it also checks
166 /// if there is a dead def of a super-register.
167 bool registerDefIsDead(unsigned Reg,
168 const TargetRegisterInfo *TRI = NULL) const {
169 return findRegisterDefOperandIdx(Reg, true, TRI) != -1;
172 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
173 /// the specific register or -1 if it is not found. It further tightening
174 /// the search criteria to a use that kills the register if isKill is true.
175 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
176 const TargetRegisterInfo *TRI = NULL) const;
178 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
179 /// a pointer to the MachineOperand rather than an index.
180 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
181 const TargetRegisterInfo *TRI = NULL) {
182 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
183 return (Idx == -1) ? NULL : &getOperand(Idx);
186 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
187 /// the specified register or -1 if it is not found. If isDead is true, defs
188 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
189 /// also checks if there is a def of a super-register.
190 int findRegisterDefOperandIdx(unsigned Reg, bool isDead = false,
191 const TargetRegisterInfo *TRI = NULL) const;
193 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
194 /// a pointer to the MachineOperand rather than an index.
195 MachineOperand *findRegisterDefOperand(unsigned Reg,bool isDead = false,
196 const TargetRegisterInfo *TRI = NULL) {
197 int Idx = findRegisterDefOperandIdx(Reg, isDead, TRI);
198 return (Idx == -1) ? NULL : &getOperand(Idx);
201 /// findFirstPredOperandIdx() - Find the index of the first operand in the
202 /// operand list that is used to represent the predicate. It returns -1 if
204 int findFirstPredOperandIdx() const;
206 /// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
207 /// to two addr elimination.
208 bool isRegReDefinedByTwoAddr(unsigned Reg) const;
210 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
212 void copyKillDeadInfo(const MachineInstr *MI);
214 /// copyPredicates - Copies predicate operand(s) from MI.
215 void copyPredicates(const MachineInstr *MI);
217 /// addRegisterKilled - We have determined MI kills a register. Look for the
218 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
219 /// add a implicit operand if it's not found. Returns true if the operand
220 /// exists / is added.
221 bool addRegisterKilled(unsigned IncomingReg,
222 const TargetRegisterInfo *RegInfo,
223 bool AddIfNotFound = false);
225 /// addRegisterDead - We have determined MI defined a register without a use.
226 /// Look for the operand that defines it and mark it as IsDead. If
227 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
228 /// true if the operand exists / is added.
229 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
230 bool AddIfNotFound = false);
232 /// copyKillDeadInfo - Copies killed/dead information from one instr to another
233 void copyKillDeadInfo(MachineInstr *OldMI,
234 const TargetRegisterInfo *RegInfo);
236 /// isSafeToMove - Return true if it is safe to this instruction. If SawStore
237 /// true, it means there is a store (or call) between the instruction the
238 /// localtion and its intended destination.
239 bool isSafeToMove(const TargetInstrInfo *TII, bool &SawStore);
244 void print(std::ostream *OS, const TargetMachine *TM) const {
245 if (OS) print(*OS, TM);
247 void print(std::ostream &OS, const TargetMachine *TM = 0) const;
248 void print(std::ostream *OS) const { if (OS) print(*OS); }
251 //===--------------------------------------------------------------------===//
252 // Accessors used to build up machine instructions.
254 /// addOperand - Add the specified operand to the instruction. If it is an
255 /// implicit operand, it is added to the end of the operand list. If it is
256 /// an explicit operand it is added at the end of the explicit operand list
257 /// (before the first implicit operand).
258 void addOperand(const MachineOperand &Op);
260 /// setDesc - Replace the instruction descriptor (thus opcode) of
261 /// the current instruction with a new one.
263 void setDesc(const TargetInstrDesc &tid) { TID = &tid; }
265 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
266 /// fewer operand than it started with.
268 void RemoveOperand(unsigned i);
270 /// addMemOperand - Add a MachineMemOperand to the machine instruction,
271 /// referencing arbitrary storage.
272 void addMemOperand(const MachineMemOperand &MO) {
273 MemOperands.push_back(MO);
277 /// getRegInfo - If this instruction is embedded into a MachineFunction,
278 /// return the MachineRegisterInfo object for the current function, otherwise
280 MachineRegisterInfo *getRegInfo();
282 /// addImplicitDefUseOperands - Add all implicit def and use operands to
283 /// this instruction.
284 void addImplicitDefUseOperands();
286 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
287 /// this instruction from their respective use lists. This requires that the
288 /// operands already be on their use lists.
289 void RemoveRegOperandsFromUseLists();
291 /// AddRegOperandsToUseLists - Add all of the register operands in
292 /// this instruction from their respective use lists. This requires that the
293 /// operands not be on their use lists yet.
294 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
297 //===----------------------------------------------------------------------===//
300 inline std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI) {
305 } // End llvm namespace