1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/Target/TargetInstrDesc.h"
21 #include "llvm/Target/TargetOpcodes.h"
22 #include "llvm/ADT/ilist.h"
23 #include "llvm/ADT/ilist_node.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/DenseMapInfo.h"
26 #include "llvm/Support/DebugLoc.h"
31 template <typename T> class SmallVectorImpl;
33 class TargetInstrDesc;
34 class TargetInstrInfo;
35 class TargetRegisterInfo;
36 class MachineFunction;
37 class MachineMemOperand;
39 //===----------------------------------------------------------------------===//
40 /// MachineInstr - Representation of each machine instruction.
42 class MachineInstr : public ilist_node<MachineInstr> {
44 typedef MachineMemOperand **mmo_iterator;
46 /// Flags to specify different kinds of comments to output in
47 /// assembly code. These flags carry semantic information not
48 /// otherwise easily derivable from the IR text.
55 const TargetInstrDesc *TID; // Instruction descriptor.
56 unsigned short NumImplicitOps; // Number of implicit operands (which
57 // are determined at construction time).
59 unsigned short AsmPrinterFlags; // Various bits of information used by
60 // the AsmPrinter to emit helpful
61 // comments. This is *not* semantic
62 // information. Do not use this for
63 // anything other than to convey comment
64 // information to AsmPrinter.
66 std::vector<MachineOperand> Operands; // the operands
67 mmo_iterator MemRefs; // information on memory references
68 mmo_iterator MemRefsEnd;
69 MachineBasicBlock *Parent; // Pointer to the owning basic block.
70 DebugLoc debugLoc; // Source line information.
72 // OperandComplete - Return true if it's illegal to add a new operand
73 bool OperandsComplete() const;
75 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
76 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
78 // Intrusive list support
79 friend struct ilist_traits<MachineInstr>;
80 friend struct ilist_traits<MachineBasicBlock>;
81 void setParent(MachineBasicBlock *P) { Parent = P; }
83 /// MachineInstr ctor - This constructor creates a copy of the given
84 /// MachineInstr in the given MachineFunction.
85 MachineInstr(MachineFunction &, const MachineInstr &);
87 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
88 /// TID NULL and no operands.
91 // The next two constructors have DebugLoc and non-DebugLoc versions;
92 // over time, the non-DebugLoc versions should be phased out and eventually
95 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
96 /// implicit operands. It reserves space for the number of operands specified
97 /// by the TargetInstrDesc. The version with a DebugLoc should be preferred.
98 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
100 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
101 /// the MachineInstr is created and added to the end of the specified basic
102 /// block. The version with a DebugLoc should be preferred.
103 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
105 /// MachineInstr ctor - This constructor create a MachineInstr and add the
106 /// implicit operands. It reserves space for number of operands specified by
107 /// TargetInstrDesc. An explicit DebugLoc is supplied.
108 explicit MachineInstr(const TargetInstrDesc &TID, const DebugLoc dl,
111 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
112 /// the MachineInstr is created and added to the end of the specified basic
114 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
115 const TargetInstrDesc &TID);
119 // MachineInstrs are pool-allocated and owned by MachineFunction.
120 friend class MachineFunction;
123 const MachineBasicBlock* getParent() const { return Parent; }
124 MachineBasicBlock* getParent() { return Parent; }
126 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
128 unsigned short getAsmPrinterFlags() const { return AsmPrinterFlags; }
130 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
132 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
134 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
136 bool getAsmPrinterFlag(CommentFlag Flag) const {
137 return AsmPrinterFlags & Flag;
140 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
142 void setAsmPrinterFlag(CommentFlag Flag) {
143 AsmPrinterFlags |= (unsigned short)Flag;
146 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
148 void clearAsmPrinterFlag(CommentFlag Flag) {
149 AsmPrinterFlags &= ~Flag;
152 /// getDebugLoc - Returns the debug location id of this MachineInstr.
154 DebugLoc getDebugLoc() const { return debugLoc; }
156 /// getDesc - Returns the target instruction descriptor of this
158 const TargetInstrDesc &getDesc() const { return *TID; }
160 /// getOpcode - Returns the opcode of this MachineInstr.
162 int getOpcode() const { return TID->Opcode; }
164 /// Access to explicit operands of the instruction.
166 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
168 const MachineOperand& getOperand(unsigned i) const {
169 assert(i < getNumOperands() && "getOperand() out of range!");
172 MachineOperand& getOperand(unsigned i) {
173 assert(i < getNumOperands() && "getOperand() out of range!");
177 /// getNumExplicitOperands - Returns the number of non-implicit operands.
179 unsigned getNumExplicitOperands() const;
181 /// iterator/begin/end - Iterate over all operands of a machine instruction.
182 typedef std::vector<MachineOperand>::iterator mop_iterator;
183 typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;
185 mop_iterator operands_begin() { return Operands.begin(); }
186 mop_iterator operands_end() { return Operands.end(); }
188 const_mop_iterator operands_begin() const { return Operands.begin(); }
189 const_mop_iterator operands_end() const { return Operands.end(); }
191 /// Access to memory operands of the instruction
192 mmo_iterator memoperands_begin() const { return MemRefs; }
193 mmo_iterator memoperands_end() const { return MemRefsEnd; }
194 bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
196 /// hasOneMemOperand - Return true if this instruction has exactly one
197 /// MachineMemOperand.
198 bool hasOneMemOperand() const {
199 return MemRefsEnd - MemRefs == 1;
203 CheckDefs, // Check all operands for equality
204 IgnoreDefs, // Ignore all definitions
205 IgnoreVRegDefs // Ignore virtual register definitions
208 /// isIdenticalTo - Return true if this instruction is identical to (same
209 /// opcode and same operands as) the specified instruction.
210 bool isIdenticalTo(const MachineInstr *Other,
211 MICheckType Check = CheckDefs) const;
213 /// removeFromParent - This method unlinks 'this' from the containing basic
214 /// block, and returns it, but does not delete it.
215 MachineInstr *removeFromParent();
217 /// eraseFromParent - This method unlinks 'this' from the containing basic
218 /// block and deletes it.
219 void eraseFromParent();
221 /// isLabel - Returns true if the MachineInstr represents a label.
223 bool isLabel() const {
224 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
225 getOpcode() == TargetOpcode::EH_LABEL ||
226 getOpcode() == TargetOpcode::GC_LABEL;
229 bool isPrologLabel() const {
230 return getOpcode() == TargetOpcode::PROLOG_LABEL;
232 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
233 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
234 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
236 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
237 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
238 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
239 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
240 bool isInsertSubreg() const {
241 return getOpcode() == TargetOpcode::INSERT_SUBREG;
243 bool isSubregToReg() const {
244 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
246 bool isRegSequence() const {
247 return getOpcode() == TargetOpcode::REG_SEQUENCE;
249 bool isCopy() const {
250 return getOpcode() == TargetOpcode::COPY;
253 /// isCopyLike - Return true if the instruction behaves like a copy.
254 /// This does not include native copy instructions.
255 bool isCopyLike() const {
256 return isCopy() || isSubregToReg();
259 /// isIdentityCopy - Return true is the instruction is an identity copy.
260 bool isIdentityCopy() const {
261 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
262 getOperand(0).getSubReg() == getOperand(1).getSubReg();
265 /// readsRegister - Return true if the MachineInstr reads the specified
266 /// register. If TargetRegisterInfo is passed, then it also checks if there
267 /// is a read of a super-register.
268 /// This does not count partial redefines of virtual registers as reads:
270 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
271 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
274 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
275 /// virtual register. Take into account that a partial define is a
276 /// read-modify-write operation.
277 bool readsVirtualRegister(unsigned Reg) const {
278 return readsWritesVirtualRegister(Reg).first;
281 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
282 /// indicating if this instruction reads or writes Reg. This also considers
284 /// If Ops is not null, all operand indices for Reg are added.
285 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
286 SmallVectorImpl<unsigned> *Ops = 0) const;
288 /// killsRegister - Return true if the MachineInstr kills the specified
289 /// register. If TargetRegisterInfo is passed, then it also checks if there is
290 /// a kill of a super-register.
291 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
292 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
295 /// definesRegister - Return true if the MachineInstr fully defines the
296 /// specified register. If TargetRegisterInfo is passed, then it also checks
297 /// if there is a def of a super-register.
298 /// NOTE: It's ignoring subreg indices on virtual registers.
299 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
300 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
303 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
304 /// or partially define) the specified register.
305 /// NOTE: It's ignoring subreg indices on virtual registers.
306 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
307 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
310 /// registerDefIsDead - Returns true if the register is dead in this machine
311 /// instruction. If TargetRegisterInfo is passed, then it also checks
312 /// if there is a dead def of a super-register.
313 bool registerDefIsDead(unsigned Reg,
314 const TargetRegisterInfo *TRI = NULL) const {
315 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
318 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
319 /// the specific register or -1 if it is not found. It further tightens
320 /// the search criteria to a use that kills the register if isKill is true.
321 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
322 const TargetRegisterInfo *TRI = NULL) const;
324 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
325 /// a pointer to the MachineOperand rather than an index.
326 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
327 const TargetRegisterInfo *TRI = NULL) {
328 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
329 return (Idx == -1) ? NULL : &getOperand(Idx);
332 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
333 /// the specified register or -1 if it is not found. If isDead is true, defs
334 /// that are not dead are skipped. If Overlap is true, then it also looks for
335 /// defs that merely overlap the specified register. If TargetRegisterInfo is
336 /// non-null, then it also checks if there is a def of a super-register.
337 int findRegisterDefOperandIdx(unsigned Reg,
338 bool isDead = false, bool Overlap = false,
339 const TargetRegisterInfo *TRI = NULL) const;
341 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
342 /// a pointer to the MachineOperand rather than an index.
343 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
344 const TargetRegisterInfo *TRI = NULL) {
345 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
346 return (Idx == -1) ? NULL : &getOperand(Idx);
349 /// findFirstPredOperandIdx() - Find the index of the first operand in the
350 /// operand list that is used to represent the predicate. It returns -1 if
352 int findFirstPredOperandIdx() const;
354 /// isRegTiedToUseOperand - Given the index of a register def operand,
355 /// check if the register def is tied to a source operand, due to either
356 /// two-address elimination or inline assembly constraints. Returns the
357 /// first tied use operand index by reference is UseOpIdx is not null.
358 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
360 /// isRegTiedToDefOperand - Return true if the use operand of the specified
361 /// index is tied to an def operand. It also returns the def operand index by
362 /// reference if DefOpIdx is not null.
363 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
365 /// clearKillInfo - Clears kill flags on all operands.
367 void clearKillInfo();
369 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
371 void copyKillDeadInfo(const MachineInstr *MI);
373 /// copyPredicates - Copies predicate operand(s) from MI.
374 void copyPredicates(const MachineInstr *MI);
376 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
377 /// properly composing subreg indices where necessary.
378 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
379 const TargetRegisterInfo &RegInfo);
381 /// addRegisterKilled - We have determined MI kills a register. Look for the
382 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
383 /// add a implicit operand if it's not found. Returns true if the operand
384 /// exists / is added.
385 bool addRegisterKilled(unsigned IncomingReg,
386 const TargetRegisterInfo *RegInfo,
387 bool AddIfNotFound = false);
389 /// addRegisterDead - We have determined MI defined a register without a use.
390 /// Look for the operand that defines it and mark it as IsDead. If
391 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
392 /// true if the operand exists / is added.
393 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
394 bool AddIfNotFound = false);
396 /// addRegisterDefined - We have determined MI defines a register. Make sure
397 /// there is an operand defining Reg.
398 void addRegisterDefined(unsigned IncomingReg,
399 const TargetRegisterInfo *RegInfo = 0);
401 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as dead
402 /// except those in the UsedRegs list.
403 void setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
404 const TargetRegisterInfo &TRI);
406 /// isSafeToMove - Return true if it is safe to move this instruction. If
407 /// SawStore is set to true, it means that there is a store (or call) between
408 /// the instruction's location and its intended destination.
409 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
410 bool &SawStore) const;
412 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
413 /// instruction which defined the specified register instead of copying it.
414 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
415 unsigned DstReg) const;
417 /// hasVolatileMemoryRef - Return true if this instruction may have a
418 /// volatile memory reference, or if the information describing the
419 /// memory reference is not available. Return false if it is known to
420 /// have no volatile memory references.
421 bool hasVolatileMemoryRef() const;
423 /// isInvariantLoad - Return true if this instruction is loading from a
424 /// location whose value is invariant across the function. For example,
425 /// loading a value from the constant pool or from the argument area of
426 /// a function if it does not change. This should only return true of *all*
427 /// loads the instruction does are invariant (if it does multiple loads).
428 bool isInvariantLoad(AliasAnalysis *AA) const;
430 /// isConstantValuePHI - If the specified instruction is a PHI that always
431 /// merges together the same virtual register, return the register, otherwise
433 unsigned isConstantValuePHI() const;
435 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
437 bool allDefsAreDead() const;
439 /// copyImplicitOps - Copy implicit register operands from specified
440 /// instruction to this instruction.
441 void copyImplicitOps(const MachineInstr *MI);
446 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
449 //===--------------------------------------------------------------------===//
450 // Accessors used to build up machine instructions.
452 /// addOperand - Add the specified operand to the instruction. If it is an
453 /// implicit operand, it is added to the end of the operand list. If it is
454 /// an explicit operand it is added at the end of the explicit operand list
455 /// (before the first implicit operand).
456 void addOperand(const MachineOperand &Op);
458 /// setDesc - Replace the instruction descriptor (thus opcode) of
459 /// the current instruction with a new one.
461 void setDesc(const TargetInstrDesc &tid) { TID = &tid; }
463 /// setDebugLoc - Replace current source information with new such.
464 /// Avoid using this, the constructor argument is preferable.
466 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
468 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
469 /// fewer operand than it started with.
471 void RemoveOperand(unsigned i);
473 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
474 /// This function should be used only occasionally. The setMemRefs function
475 /// is the primary method for setting up a MachineInstr's MemRefs list.
476 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
478 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
479 /// list. This does not transfer ownership.
480 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
481 MemRefs = NewMemRefs;
482 MemRefsEnd = NewMemRefsEnd;
486 /// getRegInfo - If this instruction is embedded into a MachineFunction,
487 /// return the MachineRegisterInfo object for the current function, otherwise
489 MachineRegisterInfo *getRegInfo();
491 /// addImplicitDefUseOperands - Add all implicit def and use operands to
492 /// this instruction.
493 void addImplicitDefUseOperands();
495 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
496 /// this instruction from their respective use lists. This requires that the
497 /// operands already be on their use lists.
498 void RemoveRegOperandsFromUseLists();
500 /// AddRegOperandsToUseLists - Add all of the register operands in
501 /// this instruction from their respective use lists. This requires that the
502 /// operands not be on their use lists yet.
503 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
506 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
507 /// MachineInstr* by *value* of the instruction rather than by pointer value.
508 /// The hashing and equality testing functions ignore definitions so this is
509 /// useful for CSE, etc.
510 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
511 static inline MachineInstr *getEmptyKey() {
515 static inline MachineInstr *getTombstoneKey() {
516 return reinterpret_cast<MachineInstr*>(-1);
519 static unsigned getHashValue(const MachineInstr* const &MI);
521 static bool isEqual(const MachineInstr* const &LHS,
522 const MachineInstr* const &RHS) {
523 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
524 LHS == getEmptyKey() || LHS == getTombstoneKey())
526 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
530 //===----------------------------------------------------------------------===//
533 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
538 } // End llvm namespace