1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependent machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Target/MRegisterInfo.h"
13 #include "Support/Annotation.h"
14 #include "Support/iterator"
18 class MachineBasicBlock;
22 typedef int MachineOpCode;
24 //===----------------------------------------------------------------------===//
25 /// Special flags on instructions that modify the opcode.
26 /// These flags are unused for now, but having them enforces that some
27 /// changes will be needed if they are used.
29 enum MachineOpCodeFlags {
30 AnnulFlag, /// 1 if annul bit is set on a branch
31 PredTakenFlag, /// 1 if branch should be predicted taken
32 PredNotTakenFlag /// 1 if branch should be predicted not taken
35 //===----------------------------------------------------------------------===//
36 /// MOTy - MachineOperandType - This namespace contains an enum that describes
37 /// how the machine operand is used by the instruction: is it read, defined, or
38 /// both? Note that the MachineInstr/Operator class currently uses bool
39 /// arguments to represent this information instead of an enum. Eventually this
40 /// should change over to use this _easier to read_ representation instead.
44 Use, /// This machine operand is only read by the instruction
45 Def, /// This machine operand is only written by the instruction
46 UseAndDef /// This machine operand is read AND written
50 //===----------------------------------------------------------------------===//
51 // class MachineOperand
54 // Representation of each machine instruction operand.
55 // This class is designed so that you can allocate a vector of operands
56 // first and initialize each one later.
58 // E.g, for this VM instruction:
59 // ptr = alloca type, numElements
60 // we generate 2 machine instructions on the SPARC:
62 // mul Constant, Numelements -> Reg
63 // add %sp, Reg -> Ptr
65 // Each instruction has 3 operands, listed above. Of those:
66 // - Reg, NumElements, and Ptr are of operand type MO_Register.
67 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
69 // For the register operands, the virtual register type is as follows:
71 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
72 // MachineInstr* minstr will point to the instruction that computes reg.
74 // - %sp will be of virtual register type MO_MachineReg.
75 // The field regNum identifies the machine register.
77 // - NumElements will be of virtual register type MO_VirtualReg.
78 // The field Value* value identifies the value.
80 // - Ptr will also be of virtual register type MO_VirtualReg.
81 // Again, the field Value* value identifies the value.
83 //===----------------------------------------------------------------------===//
85 struct MachineOperand {
86 enum MachineOperandType {
87 MO_VirtualRegister, // virtual register for *value
88 MO_MachineRegister, // pre-assigned machine register `regNum'
93 MO_MachineBasicBlock, // MachineBasicBlock reference
94 MO_FrameIndex, // Abstract Stack Frame Index
95 MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
96 MO_ExternalSymbol, // Name of external global symbol
97 MO_GlobalAddress, // Address of a global value
101 // Bit fields of the flags variable used for different operand properties
103 DEFONLYFLAG = 0x01, // this is a def but not a use of the operand
104 DEFUSEFLAG = 0x02, // this is both a def and a use
105 HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal)
106 LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal)
107 HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal)
108 LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal)
109 PCRELATIVE = 0x40, // Operand is relative to PC, not a global address
116 Value* value; // BasicBlockVal for a label operand.
117 // ConstantVal for a non-address immediate.
118 // Virtual register for an SSA operand,
119 // including hidden operands required for
120 // the generated machine code.
121 // LLVM global for MO_GlobalAddress.
123 int64_t immedVal; // Constant value for an explicit constant
125 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
126 std::string *SymbolName; // For MO_ExternalSymbol type
129 char flags; // see bit field definitions above
130 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
131 int regNum; // register number for an explicit register
132 // will be set for a value after reg allocation
137 opType(MO_VirtualRegister),
140 MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
146 MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
151 case MOTy::Use: flags = 0; break;
152 case MOTy::Def: flags = DEFONLYFLAG; break;
153 case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
154 default: assert(0 && "Invalid value for UseTy!");
158 MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy,
159 bool isPCRelative = false)
160 : value(V), opType(OpTy), regNum(-1) {
162 case MOTy::Use: flags = 0; break;
163 case MOTy::Def: flags = DEFONLYFLAG; break;
164 case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
165 default: assert(0 && "Invalid value for UseTy!");
167 if (isPCRelative) flags |= PCRELATIVE;
170 MachineOperand(MachineBasicBlock *mbb)
171 : MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) {}
173 MachineOperand(const std::string &SymName, bool isPCRelative)
174 : SymbolName(new std::string(SymName)), flags(isPCRelative ? PCRELATIVE :0),
175 opType(MO_ExternalSymbol), regNum(-1) {}
178 MachineOperand(const MachineOperand &M) : immedVal(M.immedVal),
182 if (isExternalSymbol())
183 SymbolName = new std::string(M.getSymbolName());
187 if (isExternalSymbol())
191 const MachineOperand &operator=(const MachineOperand &MO) {
192 if (isExternalSymbol()) // if old operand had a symbol name,
193 delete SymbolName; // release old memory
194 immedVal = MO.immedVal;
198 if (isExternalSymbol())
199 SymbolName = new std::string(MO.getSymbolName());
203 // Accessor methods. Caller is responsible for checking the
204 // operand type before invoking the corresponding accessor.
206 MachineOperandType getType() const { return opType; }
208 /// isPCRelative - This returns the value of the PCRELATIVE flag, which
209 /// indicates whether this operand should be emitted as a PC relative value
210 /// instead of a global address. This is used for operands of the forms:
211 /// MachineBasicBlock, GlobalAddress, ExternalSymbol
213 bool isPCRelative() const { return (flags & PCRELATIVE) != 0; }
216 // This is to finally stop caring whether we have a virtual or machine
217 // register -- an easier interface is to simply call both virtual and machine
218 // registers essentially the same, yet be able to distinguish when
219 // necessary. Thus the instruction selector can just add registers without
220 // abandon, and the register allocator won't be confused.
221 bool isVirtualRegister() const {
222 return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
223 && regNum >= MRegisterInfo::FirstVirtualRegister;
225 bool isPhysicalRegister() const {
226 return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
227 && (unsigned)regNum < MRegisterInfo::FirstVirtualRegister;
229 bool isRegister() const { return isVirtualRegister() || isPhysicalRegister();}
230 bool isMachineRegister() const { return !isVirtualRegister(); }
231 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
232 bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; }
233 bool isImmediate() const {
234 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed;
236 bool isFrameIndex() const { return opType == MO_FrameIndex; }
237 bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; }
238 bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
239 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
241 Value* getVRegValue() const {
242 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
246 Value* getVRegValueOrNull() const {
247 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
248 isPCRelativeDisp()) ? value : NULL;
250 int getMachineRegNum() const {
251 assert(opType == MO_MachineRegister);
254 int64_t getImmedValue() const { assert(isImmediate()); return immedVal; }
255 MachineBasicBlock *getMachineBasicBlock() const {
256 assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
259 int getFrameIndex() const { assert(isFrameIndex()); return immedVal; }
260 unsigned getConstantPoolIndex() const {
261 assert(isConstantPoolIndex());
265 GlobalValue *getGlobal() const {
266 assert(isGlobalAddress());
267 return (GlobalValue*)value;
270 const std::string &getSymbolName() const {
271 assert(isExternalSymbol());
275 bool opIsUse () const { return (flags & USEDEFMASK) == 0; }
276 bool opIsDefOnly () const { return flags & DEFONLYFLAG; }
277 bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
278 bool opHiBits32 () const { return flags & HIFLAG32; }
279 bool opLoBits32 () const { return flags & LOFLAG32; }
280 bool opHiBits64 () const { return flags & HIFLAG64; }
281 bool opLoBits64 () const { return flags & LOFLAG64; }
283 // used to check if a machine register has been allocated to this operand
284 bool hasAllocatedReg() const {
285 return (regNum >= 0 &&
286 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
287 opType == MO_MachineRegister));
290 // used to get the reg number if when one is allocated
291 int getAllocatedRegNum() const {
292 assert(hasAllocatedReg());
296 // ********** TODO: get rid of this duplicate code! ***********
297 unsigned getReg() const {
298 return getAllocatedRegNum();
301 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
305 // Construction methods needed for fine-grain control.
306 // These must be accessed via coresponding methods in MachineInstr.
307 void markHi32() { flags |= HIFLAG32; }
308 void markLo32() { flags |= LOFLAG32; }
309 void markHi64() { flags |= HIFLAG64; }
310 void markLo64() { flags |= LOFLAG64; }
312 // Replaces the Value with its corresponding physical register after
313 // register allocation is complete
314 void setRegForValue(int reg) {
315 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
316 opType == MO_MachineRegister);
320 friend class MachineInstr;
324 //===----------------------------------------------------------------------===//
325 // class MachineInstr
328 // Representation of each machine instruction.
330 // MachineOpCode must be an enum, defined separately for each target.
331 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
333 // There are 2 kinds of operands:
335 // (1) Explicit operands of the machine instruction in vector operands[]
337 // (2) "Implicit operands" are values implicitly used or defined by the
338 // machine instruction, such as arguments to a CALL, return value of
339 // a CALL (if any), and return value of a RETURN.
340 //===----------------------------------------------------------------------===//
343 int opCode; // the opcode
344 unsigned opCodeFlags; // flags modifying instrn behavior
345 std::vector<MachineOperand> operands; // the operands
346 unsigned numImplicitRefs; // number of implicit operands
348 // OperandComplete - Return true if it's illegal to add a new operand
349 bool OperandsComplete() const;
351 MachineInstr(const MachineInstr &); // DO NOT IMPLEMENT
352 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
354 MachineInstr(int Opcode, unsigned numOperands);
356 /// MachineInstr ctor - This constructor only does a _reserve_ of the
357 /// operands, not a resize for them. It is expected that if you use this that
358 /// you call add* methods below to fill up the operands, instead of the Set
359 /// methods. Eventually, the "resizing" ctors will be phased out.
361 MachineInstr(int Opcode, unsigned numOperands, bool XX, bool YY);
363 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
364 /// the MachineInstr is created and added to the end of the specified basic
367 MachineInstr(MachineBasicBlock *MBB, int Opcode, unsigned numOps);
372 const int getOpcode() const { return opCode; }
373 const int getOpCode() const { return opCode; }
377 unsigned getOpCodeFlags() const { return opCodeFlags; }
380 // Access to explicit operands of the instruction
382 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
384 const MachineOperand& getOperand(unsigned i) const {
385 assert(i < getNumOperands() && "getOperand() out of range!");
388 MachineOperand& getOperand(unsigned i) {
389 assert(i < getNumOperands() && "getOperand() out of range!");
394 // Access to explicit or implicit operands of the instruction
395 // This returns the i'th entry in the operand vector.
396 // That represents the i'th explicit operand or the (i-N)'th implicit operand,
397 // depending on whether i < N or i >= N.
399 const MachineOperand& getExplOrImplOperand(unsigned i) const {
400 assert(i < operands.size() && "getExplOrImplOperand() out of range!");
401 return (i < getNumOperands()? getOperand(i)
402 : getImplicitOp(i - getNumOperands()));
406 // Access to implicit operands of the instruction
408 unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
410 MachineOperand& getImplicitOp(unsigned i) {
411 assert(i < numImplicitRefs && "implicit ref# out of range!");
412 return operands[i + operands.size() - numImplicitRefs];
414 const MachineOperand& getImplicitOp(unsigned i) const {
415 assert(i < numImplicitRefs && "implicit ref# out of range!");
416 return operands[i + operands.size() - numImplicitRefs];
419 Value* getImplicitRef(unsigned i) {
420 return getImplicitOp(i).getVRegValue();
422 const Value* getImplicitRef(unsigned i) const {
423 return getImplicitOp(i).getVRegValue();
426 void addImplicitRef(Value* V, bool isDef = false, bool isDefAndUse = false) {
428 addRegOperand(V, isDef, isDefAndUse);
430 void setImplicitRef(unsigned i, Value* V) {
431 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
432 SetMachineOperandVal(i + getNumOperands(),
433 MachineOperand::MO_VirtualRegister, V);
439 void print(std::ostream &OS, const TargetMachine &TM) const;
441 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
444 // Define iterators to access the Value operands of the Machine Instruction.
445 // Note that these iterators only enumerate the explicit operands.
446 // begin() and end() are defined to produce these iterators...
448 template<class _MI, class _V> class ValOpIterator;
449 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
450 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
453 //===--------------------------------------------------------------------===//
454 // Accessors to add operands when building up machine instructions
457 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
460 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
461 assert(!OperandsComplete() &&
462 "Trying to add an operand to a machine instr that is already done!");
463 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
464 !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def)));
467 void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use,
468 bool isPCRelative = false) {
469 assert(!OperandsComplete() &&
470 "Trying to add an operand to a machine instr that is already done!");
471 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
475 void addCCRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) {
476 assert(!OperandsComplete() &&
477 "Trying to add an operand to a machine instr that is already done!");
478 operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy,
483 /// addRegOperand - Add a symbolic virtual register reference...
485 void addRegOperand(int reg, bool isDef) {
486 assert(!OperandsComplete() &&
487 "Trying to add an operand to a machine instr that is already done!");
488 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
489 isDef ? MOTy::Def : MOTy::Use));
492 /// addRegOperand - Add a symbolic virtual register reference...
494 void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
495 assert(!OperandsComplete() &&
496 "Trying to add an operand to a machine instr that is already done!");
497 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
501 /// addPCDispOperand - Add a PC relative displacement operand to the MI
503 void addPCDispOperand(Value *V) {
504 assert(!OperandsComplete() &&
505 "Trying to add an operand to a machine instr that is already done!");
506 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp,
510 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
512 void addMachineRegOperand(int reg, bool isDef) {
513 assert(!OperandsComplete() &&
514 "Trying to add an operand to a machine instr that is already done!");
515 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
516 isDef ? MOTy::Def : MOTy::Use));
519 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
521 void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
522 assert(!OperandsComplete() &&
523 "Trying to add an operand to a machine instr that is already done!");
524 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
528 /// addZeroExtImmOperand - Add a zero extended constant argument to the
529 /// machine instruction.
531 void addZeroExtImmOperand(int64_t intValue) {
532 assert(!OperandsComplete() &&
533 "Trying to add an operand to a machine instr that is already done!");
534 operands.push_back(MachineOperand(intValue,
535 MachineOperand::MO_UnextendedImmed));
538 /// addSignExtImmOperand - Add a zero extended constant argument to the
539 /// machine instruction.
541 void addSignExtImmOperand(int64_t intValue) {
542 assert(!OperandsComplete() &&
543 "Trying to add an operand to a machine instr that is already done!");
544 operands.push_back(MachineOperand(intValue,
545 MachineOperand::MO_SignExtendedImmed));
548 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
549 assert(!OperandsComplete() &&
550 "Trying to add an operand to a machine instr that is already done!");
551 operands.push_back(MachineOperand(MBB));
554 /// addFrameIndexOperand - Add an abstract frame index to the instruction
556 void addFrameIndexOperand(unsigned Idx) {
557 assert(!OperandsComplete() &&
558 "Trying to add an operand to a machine instr that is already done!");
559 operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex));
562 /// addConstantPoolndexOperand - Add a constant pool object index to the
565 void addConstantPoolIndexOperand(unsigned I) {
566 assert(!OperandsComplete() &&
567 "Trying to add an operand to a machine instr that is already done!");
568 operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex));
571 void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative) {
572 assert(!OperandsComplete() &&
573 "Trying to add an operand to a machine instr that is already done!");
574 operands.push_back(MachineOperand((Value*)GV,
575 MachineOperand::MO_GlobalAddress,
576 MOTy::Use, isPCRelative));
579 /// addExternalSymbolOperand - Add an external symbol operand to this instr
581 void addExternalSymbolOperand(const std::string &SymName, bool isPCRelative) {
582 operands.push_back(MachineOperand(SymName, isPCRelative));
585 //===--------------------------------------------------------------------===//
586 // Accessors used to modify instructions in place.
588 // FIXME: Move this stuff to MachineOperand itself!
590 /// replace - Support to rewrite a machine instruction in place: for now,
591 /// simply replace() and then set new operands with Set.*Operand methods
594 void replace(int Opcode, unsigned numOperands);
596 /// setOpcode - Replace the opcode of the current instruction with a new one.
598 void setOpcode(unsigned Op) { opCode = Op; }
600 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
601 /// fewer operand than it started with.
603 void RemoveOperand(unsigned i) {
604 operands.erase(operands.begin()+i);
607 // Access to set the operands when building the machine instruction
609 void SetMachineOperandVal (unsigned i,
610 MachineOperand::MachineOperandType operandType,
613 void SetMachineOperandConst (unsigned i,
614 MachineOperand::MachineOperandType operandType,
617 void SetMachineOperandReg(unsigned i, int regNum);
620 unsigned substituteValue(const Value* oldVal, Value* newVal,
621 bool defsOnly, bool notDefsAndUses,
622 bool& someArgsWereIgnored);
624 void setOperandHi32(unsigned i) { operands[i].markHi32(); }
625 void setOperandLo32(unsigned i) { operands[i].markLo32(); }
626 void setOperandHi64(unsigned i) { operands[i].markHi64(); }
627 void setOperandLo64(unsigned i) { operands[i].markLo64(); }
630 // SetRegForOperand -
631 // SetRegForImplicitRef -
632 // Mark an explicit or implicit operand with its allocated physical register.
634 void SetRegForOperand(unsigned i, int regNum);
635 void SetRegForImplicitRef(unsigned i, int regNum);
638 // Iterator to enumerate machine operands.
640 template<class MITy, class VTy>
641 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
645 void skipToNextVal() {
646 while (i < MI->getNumOperands() &&
647 !( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister ||
648 MI->getOperand(i).getType() == MachineOperand::MO_CCRegister)
649 && MI->getOperand(i).getVRegValue() != 0))
653 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
658 typedef ValOpIterator<MITy, VTy> _Self;
660 inline VTy operator*() const {
661 return MI->getOperand(i).getVRegValue();
664 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
665 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
667 inline VTy operator->() const { return operator*(); }
669 inline bool isUseOnly() const { return MI->getOperand(i).opIsUse(); }
670 inline bool isDefOnly() const { return MI->getOperand(i).opIsDefOnly(); }
671 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
673 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
674 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
676 inline bool operator==(const _Self &y) const {
679 inline bool operator!=(const _Self &y) const {
680 return !operator==(y);
683 static _Self begin(MITy MI) {
686 static _Self end(MITy MI) {
687 return _Self(MI, MI->getNumOperands());
691 // define begin() and end()
692 val_op_iterator begin() { return val_op_iterator::begin(this); }
693 val_op_iterator end() { return val_op_iterator::end(this); }
695 const_val_op_iterator begin() const {
696 return const_val_op_iterator::begin(this);
698 const_val_op_iterator end() const {
699 return const_val_op_iterator::end(this);
704 //===----------------------------------------------------------------------===//
707 std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI);
708 std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO);
709 void PrintMachineInstructions(const Function *F);