1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/DenseMapInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/ilist.h"
24 #include "llvm/ADT/ilist_node.h"
25 #include "llvm/ADT/iterator_range.h"
26 #include "llvm/CodeGen/MachineOperand.h"
27 #include "llvm/IR/DebugInfo.h"
28 #include "llvm/IR/DebugLoc.h"
29 #include "llvm/IR/InlineAsm.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/Support/ArrayRecycler.h"
32 #include "llvm/Target/TargetOpcodes.h"
36 template <typename T> class SmallVectorImpl;
38 class TargetInstrInfo;
39 class TargetRegisterClass;
40 class TargetRegisterInfo;
41 class MachineFunction;
42 class MachineMemOperand;
44 //===----------------------------------------------------------------------===//
45 /// Representation of each machine instruction.
47 /// This class isn't a POD type, but it must have a trivial destructor. When a
48 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
49 /// without having their destructor called.
51 class MachineInstr : public ilist_node<MachineInstr> {
53 typedef MachineMemOperand **mmo_iterator;
55 /// Flags to specify different kinds of comments to output in
56 /// assembly code. These flags carry semantic information not
57 /// otherwise easily derivable from the IR text.
65 FrameSetup = 1 << 0, // Instruction is used as a part of
66 // function frame setup code.
67 BundledPred = 1 << 1, // Instruction has bundled predecessors.
68 BundledSucc = 1 << 2 // Instruction has bundled successors.
71 const MCInstrDesc *MCID; // Instruction descriptor.
72 MachineBasicBlock *Parent; // Pointer to the owning basic block.
74 // Operands are allocated by an ArrayRecycler.
75 MachineOperand *Operands; // Pointer to the first operand.
76 unsigned NumOperands; // Number of operands on instruction.
77 typedef ArrayRecycler<MachineOperand>::Capacity OperandCapacity;
78 OperandCapacity CapOperands; // Capacity of the Operands array.
80 uint8_t Flags; // Various bits of additional
81 // information about machine
84 uint8_t AsmPrinterFlags; // Various bits of information used by
85 // the AsmPrinter to emit helpful
86 // comments. This is *not* semantic
87 // information. Do not use this for
88 // anything other than to convey comment
89 // information to AsmPrinter.
91 uint8_t NumMemRefs; // Information on memory references.
94 DebugLoc debugLoc; // Source line information.
96 MachineInstr(const MachineInstr&) = delete;
97 void operator=(const MachineInstr&) = delete;
98 // Use MachineFunction::DeleteMachineInstr() instead.
99 ~MachineInstr() = delete;
101 // Intrusive list support
102 friend struct ilist_traits<MachineInstr>;
103 friend struct ilist_traits<MachineBasicBlock>;
104 void setParent(MachineBasicBlock *P) { Parent = P; }
106 /// This constructor creates a copy of the given
107 /// MachineInstr in the given MachineFunction.
108 MachineInstr(MachineFunction &, const MachineInstr &);
110 /// This constructor create a MachineInstr and add the implicit operands.
111 /// It reserves space for number of operands specified by
112 /// MCInstrDesc. An explicit DebugLoc is supplied.
113 MachineInstr(MachineFunction &, const MCInstrDesc &MCID, DebugLoc dl,
116 // MachineInstrs are pool-allocated and owned by MachineFunction.
117 friend class MachineFunction;
120 const MachineBasicBlock* getParent() const { return Parent; }
121 MachineBasicBlock* getParent() { return Parent; }
123 /// Return the asm printer flags bitvector.
124 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
126 /// Clear the AsmPrinter bitvector.
127 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
129 /// Return whether an AsmPrinter flag is set.
130 bool getAsmPrinterFlag(CommentFlag Flag) const {
131 return AsmPrinterFlags & Flag;
134 /// Set a flag for the AsmPrinter.
135 void setAsmPrinterFlag(CommentFlag Flag) {
136 AsmPrinterFlags |= (uint8_t)Flag;
139 /// Clear specific AsmPrinter flags.
140 void clearAsmPrinterFlag(CommentFlag Flag) {
141 AsmPrinterFlags &= ~Flag;
144 /// Return the MI flags bitvector.
145 uint8_t getFlags() const {
149 /// Return whether an MI flag is set.
150 bool getFlag(MIFlag Flag) const {
155 void setFlag(MIFlag Flag) {
156 Flags |= (uint8_t)Flag;
159 void setFlags(unsigned flags) {
160 // Filter out the automatically maintained flags.
161 unsigned Mask = BundledPred | BundledSucc;
162 Flags = (Flags & Mask) | (flags & ~Mask);
165 /// clearFlag - Clear a MI flag.
166 void clearFlag(MIFlag Flag) {
167 Flags &= ~((uint8_t)Flag);
170 /// Return true if MI is in a bundle (but not the first MI in a bundle).
172 /// A bundle looks like this before it's finalized:
184 /// In this case, the first MI starts a bundle but is not inside a bundle, the
185 /// next 2 MIs are considered "inside" the bundle.
187 /// After a bundle is finalized, it looks like this:
203 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
204 /// a bundle, but the next three MIs are.
205 bool isInsideBundle() const {
206 return getFlag(BundledPred);
209 /// Return true if this instruction part of a bundle. This is true
210 /// if either itself or its following instruction is marked "InsideBundle".
211 bool isBundled() const {
212 return isBundledWithPred() || isBundledWithSucc();
215 /// Return true if this instruction is part of a bundle, and it is not the
216 /// first instruction in the bundle.
217 bool isBundledWithPred() const { return getFlag(BundledPred); }
219 /// Return true if this instruction is part of a bundle, and it is not the
220 /// last instruction in the bundle.
221 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
223 /// Bundle this instruction with its predecessor. This can be an unbundled
224 /// instruction, or it can be the first instruction in a bundle.
225 void bundleWithPred();
227 /// Bundle this instruction with its successor. This can be an unbundled
228 /// instruction, or it can be the last instruction in a bundle.
229 void bundleWithSucc();
231 /// Break bundle above this instruction.
232 void unbundleFromPred();
234 /// Break bundle below this instruction.
235 void unbundleFromSucc();
237 /// Returns the debug location id of this MachineInstr.
238 const DebugLoc &getDebugLoc() const { return debugLoc; }
240 /// Return the debug variable referenced by
241 /// this DBG_VALUE instruction.
242 const DILocalVariable *getDebugVariable() const {
243 assert(isDebugValue() && "not a DBG_VALUE");
244 return cast<DILocalVariable>(getOperand(2).getMetadata());
247 /// Return the complex address expression referenced by
248 /// this DBG_VALUE instruction.
249 const DIExpression *getDebugExpression() const {
250 assert(isDebugValue() && "not a DBG_VALUE");
251 return cast<DIExpression>(getOperand(3).getMetadata());
254 /// Emit an error referring to the source location of this instruction.
255 /// This should only be used for inline assembly that is somehow
256 /// impossible to compile. Other errors should have been handled much
259 /// If this method returns, the caller should try to recover from the error.
261 void emitError(StringRef Msg) const;
263 /// Returns the target instruction descriptor of this MachineInstr.
264 const MCInstrDesc &getDesc() const { return *MCID; }
266 /// Returns the opcode of this MachineInstr.
267 unsigned getOpcode() const { return MCID->Opcode; }
269 /// Access to explicit operands of the instruction.
271 unsigned getNumOperands() const { return NumOperands; }
273 const MachineOperand& getOperand(unsigned i) const {
274 assert(i < getNumOperands() && "getOperand() out of range!");
277 MachineOperand& getOperand(unsigned i) {
278 assert(i < getNumOperands() && "getOperand() out of range!");
282 /// Returns the number of non-implicit operands.
283 unsigned getNumExplicitOperands() const;
285 /// iterator/begin/end - Iterate over all operands of a machine instruction.
286 typedef MachineOperand *mop_iterator;
287 typedef const MachineOperand *const_mop_iterator;
289 mop_iterator operands_begin() { return Operands; }
290 mop_iterator operands_end() { return Operands + NumOperands; }
292 const_mop_iterator operands_begin() const { return Operands; }
293 const_mop_iterator operands_end() const { return Operands + NumOperands; }
295 iterator_range<mop_iterator> operands() {
296 return iterator_range<mop_iterator>(operands_begin(), operands_end());
298 iterator_range<const_mop_iterator> operands() const {
299 return iterator_range<const_mop_iterator>(operands_begin(), operands_end());
301 iterator_range<mop_iterator> explicit_operands() {
302 return iterator_range<mop_iterator>(
303 operands_begin(), operands_begin() + getNumExplicitOperands());
305 iterator_range<const_mop_iterator> explicit_operands() const {
306 return iterator_range<const_mop_iterator>(
307 operands_begin(), operands_begin() + getNumExplicitOperands());
309 iterator_range<mop_iterator> implicit_operands() {
310 return iterator_range<mop_iterator>(explicit_operands().end(),
313 iterator_range<const_mop_iterator> implicit_operands() const {
314 return iterator_range<const_mop_iterator>(explicit_operands().end(),
317 iterator_range<mop_iterator> defs() {
318 return iterator_range<mop_iterator>(
319 operands_begin(), operands_begin() + getDesc().getNumDefs());
321 iterator_range<const_mop_iterator> defs() const {
322 return iterator_range<const_mop_iterator>(
323 operands_begin(), operands_begin() + getDesc().getNumDefs());
325 iterator_range<mop_iterator> uses() {
326 return iterator_range<mop_iterator>(
327 operands_begin() + getDesc().getNumDefs(), operands_end());
329 iterator_range<const_mop_iterator> uses() const {
330 return iterator_range<const_mop_iterator>(
331 operands_begin() + getDesc().getNumDefs(), operands_end());
334 /// Access to memory operands of the instruction
335 mmo_iterator memoperands_begin() const { return MemRefs; }
336 mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
337 bool memoperands_empty() const { return NumMemRefs == 0; }
339 iterator_range<mmo_iterator> memoperands() {
340 return iterator_range<mmo_iterator>(memoperands_begin(), memoperands_end());
342 iterator_range<mmo_iterator> memoperands() const {
343 return iterator_range<mmo_iterator>(memoperands_begin(), memoperands_end());
346 /// Return true if this instruction has exactly one MachineMemOperand.
347 bool hasOneMemOperand() const {
348 return NumMemRefs == 1;
351 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
352 /// queries but they are bundle aware.
355 IgnoreBundle, // Ignore bundles
356 AnyInBundle, // Return true if any instruction in bundle has property
357 AllInBundle // Return true if all instructions in bundle have property
360 /// Return true if the instruction (or in the case of a bundle,
361 /// the instructions inside the bundle) has the specified property.
362 /// The first argument is the property being queried.
363 /// The second argument indicates whether the query should look inside
364 /// instruction bundles.
365 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
366 // Inline the fast path for unbundled or bundle-internal instructions.
367 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
368 return getDesc().getFlags() & (1 << MCFlag);
370 // If this is the first instruction in a bundle, take the slow path.
371 return hasPropertyInBundle(1 << MCFlag, Type);
374 /// Return true if this instruction can have a variable number of operands.
375 /// In this case, the variable operands will be after the normal
376 /// operands but before the implicit definitions and uses (if any are
378 bool isVariadic(QueryType Type = IgnoreBundle) const {
379 return hasProperty(MCID::Variadic, Type);
382 /// Set if this instruction has an optional definition, e.g.
383 /// ARM instructions which can set condition code if 's' bit is set.
384 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
385 return hasProperty(MCID::HasOptionalDef, Type);
388 /// Return true if this is a pseudo instruction that doesn't
389 /// correspond to a real machine instruction.
390 bool isPseudo(QueryType Type = IgnoreBundle) const {
391 return hasProperty(MCID::Pseudo, Type);
394 bool isReturn(QueryType Type = AnyInBundle) const {
395 return hasProperty(MCID::Return, Type);
398 bool isCall(QueryType Type = AnyInBundle) const {
399 return hasProperty(MCID::Call, Type);
402 /// Returns true if the specified instruction stops control flow
403 /// from executing the instruction immediately following it. Examples include
404 /// unconditional branches and return instructions.
405 bool isBarrier(QueryType Type = AnyInBundle) const {
406 return hasProperty(MCID::Barrier, Type);
409 /// Returns true if this instruction part of the terminator for a basic block.
410 /// Typically this is things like return and branch instructions.
412 /// Various passes use this to insert code into the bottom of a basic block,
413 /// but before control flow occurs.
414 bool isTerminator(QueryType Type = AnyInBundle) const {
415 return hasProperty(MCID::Terminator, Type);
418 /// Returns true if this is a conditional, unconditional, or indirect branch.
419 /// Predicates below can be used to discriminate between
420 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
421 /// get more information.
422 bool isBranch(QueryType Type = AnyInBundle) const {
423 return hasProperty(MCID::Branch, Type);
426 /// Return true if this is an indirect branch, such as a
427 /// branch through a register.
428 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
429 return hasProperty(MCID::IndirectBranch, Type);
432 /// Return true if this is a branch which may fall
433 /// through to the next instruction or may transfer control flow to some other
434 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
435 /// information about this branch.
436 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
437 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
440 /// Return true if this is a branch which always
441 /// transfers control flow to some other block. The
442 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
443 /// about this branch.
444 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
445 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
448 /// Return true if this instruction has a predicate operand that
449 /// controls execution. It may be set to 'always', or may be set to other
450 /// values. There are various methods in TargetInstrInfo that can be used to
451 /// control and modify the predicate in this instruction.
452 bool isPredicable(QueryType Type = AllInBundle) const {
453 // If it's a bundle than all bundled instructions must be predicable for this
455 return hasProperty(MCID::Predicable, Type);
458 /// Return true if this instruction is a comparison.
459 bool isCompare(QueryType Type = IgnoreBundle) const {
460 return hasProperty(MCID::Compare, Type);
463 /// Return true if this instruction is a move immediate
464 /// (including conditional moves) instruction.
465 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
466 return hasProperty(MCID::MoveImm, Type);
469 /// Return true if this instruction is a bitcast instruction.
470 bool isBitcast(QueryType Type = IgnoreBundle) const {
471 return hasProperty(MCID::Bitcast, Type);
474 /// Return true if this instruction is a select instruction.
475 bool isSelect(QueryType Type = IgnoreBundle) const {
476 return hasProperty(MCID::Select, Type);
479 /// Return true if this instruction cannot be safely duplicated.
480 /// For example, if the instruction has a unique labels attached
481 /// to it, duplicating it would cause multiple definition errors.
482 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
483 return hasProperty(MCID::NotDuplicable, Type);
486 /// Returns true if the specified instruction has a delay slot
487 /// which must be filled by the code generator.
488 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
489 return hasProperty(MCID::DelaySlot, Type);
492 /// Return true for instructions that can be folded as
493 /// memory operands in other instructions. The most common use for this
494 /// is instructions that are simple loads from memory that don't modify
495 /// the loaded value in any way, but it can also be used for instructions
496 /// that can be expressed as constant-pool loads, such as V_SETALLONES
497 /// on x86, to allow them to be folded when it is beneficial.
498 /// This should only be set on instructions that return a value in their
499 /// only virtual register definition.
500 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
501 return hasProperty(MCID::FoldableAsLoad, Type);
504 /// \brief Return true if this instruction behaves
505 /// the same way as the generic REG_SEQUENCE instructions.
507 /// dX VMOVDRR rY, rZ
509 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
511 /// Note that for the optimizers to be able to take advantage of
512 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
513 /// override accordingly.
514 bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
515 return hasProperty(MCID::RegSequence, Type);
518 /// \brief Return true if this instruction behaves
519 /// the same way as the generic EXTRACT_SUBREG instructions.
521 /// rX, rY VMOVRRD dZ
522 /// is equivalent to two EXTRACT_SUBREG:
523 /// rX = EXTRACT_SUBREG dZ, ssub_0
524 /// rY = EXTRACT_SUBREG dZ, ssub_1
526 /// Note that for the optimizers to be able to take advantage of
527 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
528 /// override accordingly.
529 bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
530 return hasProperty(MCID::ExtractSubreg, Type);
533 /// \brief Return true if this instruction behaves
534 /// the same way as the generic INSERT_SUBREG instructions.
536 /// dX = VSETLNi32 dY, rZ, Imm
537 /// is equivalent to a INSERT_SUBREG:
538 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
540 /// Note that for the optimizers to be able to take advantage of
541 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
542 /// override accordingly.
543 bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
544 return hasProperty(MCID::InsertSubreg, Type);
547 //===--------------------------------------------------------------------===//
548 // Side Effect Analysis
549 //===--------------------------------------------------------------------===//
551 /// Return true if this instruction could possibly read memory.
552 /// Instructions with this flag set are not necessarily simple load
553 /// instructions, they may load a value and modify it, for example.
554 bool mayLoad(QueryType Type = AnyInBundle) const {
556 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
557 if (ExtraInfo & InlineAsm::Extra_MayLoad)
560 return hasProperty(MCID::MayLoad, Type);
563 /// Return true if this instruction could possibly modify memory.
564 /// Instructions with this flag set are not necessarily simple store
565 /// instructions, they may store a modified value based on their operands, or
566 /// may not actually modify anything, for example.
567 bool mayStore(QueryType Type = AnyInBundle) const {
569 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
570 if (ExtraInfo & InlineAsm::Extra_MayStore)
573 return hasProperty(MCID::MayStore, Type);
576 /// Return true if this instruction could possibly read or modify memory.
577 bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
578 return mayLoad(Type) || mayStore(Type);
581 //===--------------------------------------------------------------------===//
582 // Flags that indicate whether an instruction can be modified by a method.
583 //===--------------------------------------------------------------------===//
585 /// Return true if this may be a 2- or 3-address
586 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
587 /// result if Y and Z are exchanged. If this flag is set, then the
588 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
591 /// Note that this flag may be set on instructions that are only commutable
592 /// sometimes. In these cases, the call to commuteInstruction will fail.
593 /// Also note that some instructions require non-trivial modification to
595 bool isCommutable(QueryType Type = IgnoreBundle) const {
596 return hasProperty(MCID::Commutable, Type);
599 /// Return true if this is a 2-address instruction
600 /// which can be changed into a 3-address instruction if needed. Doing this
601 /// transformation can be profitable in the register allocator, because it
602 /// means that the instruction can use a 2-address form if possible, but
603 /// degrade into a less efficient form if the source and dest register cannot
604 /// be assigned to the same register. For example, this allows the x86
605 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
606 /// is the same speed as the shift but has bigger code size.
608 /// If this returns true, then the target must implement the
609 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
610 /// is allowed to fail if the transformation isn't valid for this specific
611 /// instruction (e.g. shl reg, 4 on x86).
613 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
614 return hasProperty(MCID::ConvertibleTo3Addr, Type);
617 /// Return true if this instruction requires
618 /// custom insertion support when the DAG scheduler is inserting it into a
619 /// machine basic block. If this is true for the instruction, it basically
620 /// means that it is a pseudo instruction used at SelectionDAG time that is
621 /// expanded out into magic code by the target when MachineInstrs are formed.
623 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
624 /// is used to insert this into the MachineBasicBlock.
625 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
626 return hasProperty(MCID::UsesCustomInserter, Type);
629 /// Return true if this instruction requires *adjustment*
630 /// after instruction selection by calling a target hook. For example, this
631 /// can be used to fill in ARM 's' optional operand depending on whether
632 /// the conditional flag register is used.
633 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
634 return hasProperty(MCID::HasPostISelHook, Type);
637 /// Returns true if this instruction is a candidate for remat.
638 /// This flag is deprecated, please don't use it anymore. If this
639 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
640 /// verify the instruction is really rematable.
641 bool isRematerializable(QueryType Type = AllInBundle) const {
642 // It's only possible to re-mat a bundle if all bundled instructions are
643 // re-materializable.
644 return hasProperty(MCID::Rematerializable, Type);
647 /// Returns true if this instruction has the same cost (or less) than a move
648 /// instruction. This is useful during certain types of optimizations
649 /// (e.g., remat during two-address conversion or machine licm)
650 /// where we would like to remat or hoist the instruction, but not if it costs
651 /// more than moving the instruction into the appropriate register. Note, we
652 /// are not marking copies from and to the same register class with this flag.
653 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
654 // Only returns true for a bundle if all bundled instructions are cheap.
655 return hasProperty(MCID::CheapAsAMove, Type);
658 /// Returns true if this instruction source operands
659 /// have special register allocation requirements that are not captured by the
660 /// operand register classes. e.g. ARM::STRD's two source registers must be an
661 /// even / odd pair, ARM::STM registers have to be in ascending order.
662 /// Post-register allocation passes should not attempt to change allocations
663 /// for sources of instructions with this flag.
664 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
665 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
668 /// Returns true if this instruction def operands
669 /// have special register allocation requirements that are not captured by the
670 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
671 /// even / odd pair, ARM::LDM registers have to be in ascending order.
672 /// Post-register allocation passes should not attempt to change allocations
673 /// for definitions of instructions with this flag.
674 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
675 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
680 CheckDefs, // Check all operands for equality
681 CheckKillDead, // Check all operands including kill / dead markers
682 IgnoreDefs, // Ignore all definitions
683 IgnoreVRegDefs // Ignore virtual register definitions
686 /// Return true if this instruction is identical to (same
687 /// opcode and same operands as) the specified instruction.
688 bool isIdenticalTo(const MachineInstr *Other,
689 MICheckType Check = CheckDefs) const;
691 /// Unlink 'this' from the containing basic block, and return it without
694 /// This function can not be used on bundled instructions, use
695 /// removeFromBundle() to remove individual instructions from a bundle.
696 MachineInstr *removeFromParent();
698 /// Unlink this instruction from its basic block and return it without
701 /// If the instruction is part of a bundle, the other instructions in the
702 /// bundle remain bundled.
703 MachineInstr *removeFromBundle();
705 /// Unlink 'this' from the containing basic block and delete it.
707 /// If this instruction is the header of a bundle, the whole bundle is erased.
708 /// This function can not be used for instructions inside a bundle, use
709 /// eraseFromBundle() to erase individual bundled instructions.
710 void eraseFromParent();
712 /// Unlink 'this' from the containing basic block and delete it.
714 /// For all definitions mark their uses in DBG_VALUE nodes
715 /// as undefined. Otherwise like eraseFromParent().
716 void eraseFromParentAndMarkDBGValuesForRemoval();
718 /// Unlink 'this' form its basic block and delete it.
720 /// If the instruction is part of a bundle, the other instructions in the
721 /// bundle remain bundled.
722 void eraseFromBundle();
724 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
725 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
727 /// Returns true if the MachineInstr represents a label.
728 bool isLabel() const { return isEHLabel() || isGCLabel(); }
729 bool isCFIInstruction() const {
730 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
733 // True if the instruction represents a position in the function.
734 bool isPosition() const { return isLabel() || isCFIInstruction(); }
736 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
737 /// A DBG_VALUE is indirect iff the first operand is a register and
738 /// the second operand is an immediate.
739 bool isIndirectDebugValue() const {
740 return isDebugValue()
741 && getOperand(0).isReg()
742 && getOperand(1).isImm();
745 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
746 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
747 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
748 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
749 bool isMSInlineAsm() const {
750 return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();
752 bool isStackAligningInlineAsm() const;
753 InlineAsm::AsmDialect getInlineAsmDialect() const;
754 bool isInsertSubreg() const {
755 return getOpcode() == TargetOpcode::INSERT_SUBREG;
757 bool isSubregToReg() const {
758 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
760 bool isRegSequence() const {
761 return getOpcode() == TargetOpcode::REG_SEQUENCE;
763 bool isBundle() const {
764 return getOpcode() == TargetOpcode::BUNDLE;
766 bool isCopy() const {
767 return getOpcode() == TargetOpcode::COPY;
769 bool isFullCopy() const {
770 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
772 bool isExtractSubreg() const {
773 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
776 /// Return true if the instruction behaves like a copy.
777 /// This does not include native copy instructions.
778 bool isCopyLike() const {
779 return isCopy() || isSubregToReg();
782 /// Return true is the instruction is an identity copy.
783 bool isIdentityCopy() const {
784 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
785 getOperand(0).getSubReg() == getOperand(1).getSubReg();
788 /// Return true if this is a transient instruction that is
789 /// either very likely to be eliminated during register allocation (such as
790 /// copy-like instructions), or if this instruction doesn't have an
791 /// execution-time cost.
792 bool isTransient() const {
793 switch(getOpcode()) {
794 default: return false;
795 // Copy-like instructions are usually eliminated during register allocation.
796 case TargetOpcode::PHI:
797 case TargetOpcode::COPY:
798 case TargetOpcode::INSERT_SUBREG:
799 case TargetOpcode::SUBREG_TO_REG:
800 case TargetOpcode::REG_SEQUENCE:
801 // Pseudo-instructions that don't produce any real output.
802 case TargetOpcode::IMPLICIT_DEF:
803 case TargetOpcode::KILL:
804 case TargetOpcode::CFI_INSTRUCTION:
805 case TargetOpcode::EH_LABEL:
806 case TargetOpcode::GC_LABEL:
807 case TargetOpcode::DBG_VALUE:
812 /// Return the number of instructions inside the MI bundle, excluding the
815 /// This is the number of instructions that MachineBasicBlock::iterator
816 /// skips, 0 for unbundled instructions.
817 unsigned getBundleSize() const;
819 /// Return true if the MachineInstr reads the specified register.
820 /// If TargetRegisterInfo is passed, then it also checks if there
821 /// is a read of a super-register.
822 /// This does not count partial redefines of virtual registers as reads:
824 bool readsRegister(unsigned Reg,
825 const TargetRegisterInfo *TRI = nullptr) const {
826 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
829 /// Return true if the MachineInstr reads the specified virtual register.
830 /// Take into account that a partial define is a
831 /// read-modify-write operation.
832 bool readsVirtualRegister(unsigned Reg) const {
833 return readsWritesVirtualRegister(Reg).first;
836 /// Return a pair of bools (reads, writes) indicating if this instruction
837 /// reads or writes Reg. This also considers partial defines.
838 /// If Ops is not null, all operand indices for Reg are added.
839 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
840 SmallVectorImpl<unsigned> *Ops = nullptr) const;
842 /// Return true if the MachineInstr kills the specified register.
843 /// If TargetRegisterInfo is passed, then it also checks if there is
844 /// a kill of a super-register.
845 bool killsRegister(unsigned Reg,
846 const TargetRegisterInfo *TRI = nullptr) const {
847 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
850 /// Return true if the MachineInstr fully defines the specified register.
851 /// If TargetRegisterInfo is passed, then it also checks
852 /// if there is a def of a super-register.
853 /// NOTE: It's ignoring subreg indices on virtual registers.
854 bool definesRegister(unsigned Reg,
855 const TargetRegisterInfo *TRI = nullptr) const {
856 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
859 /// Return true if the MachineInstr modifies (fully define or partially
860 /// define) the specified register.
861 /// NOTE: It's ignoring subreg indices on virtual registers.
862 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
863 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
866 /// Returns true if the register is dead in this machine instruction.
867 /// If TargetRegisterInfo is passed, then it also checks
868 /// if there is a dead def of a super-register.
869 bool registerDefIsDead(unsigned Reg,
870 const TargetRegisterInfo *TRI = nullptr) const {
871 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
874 /// Returns the operand index that is a use of the specific register or -1
875 /// if it is not found. It further tightens the search criteria to a use
876 /// that kills the register if isKill is true.
877 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
878 const TargetRegisterInfo *TRI = nullptr) const;
880 /// Wrapper for findRegisterUseOperandIdx, it returns
881 /// a pointer to the MachineOperand rather than an index.
882 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
883 const TargetRegisterInfo *TRI = nullptr) {
884 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
885 return (Idx == -1) ? nullptr : &getOperand(Idx);
888 /// Returns the operand index that is a def of the specified register or
889 /// -1 if it is not found. If isDead is true, defs that are not dead are
890 /// skipped. If Overlap is true, then it also looks for defs that merely
891 /// overlap the specified register. If TargetRegisterInfo is non-null,
892 /// then it also checks if there is a def of a super-register.
893 /// This may also return a register mask operand when Overlap is true.
894 int findRegisterDefOperandIdx(unsigned Reg,
895 bool isDead = false, bool Overlap = false,
896 const TargetRegisterInfo *TRI = nullptr) const;
898 /// Wrapper for findRegisterDefOperandIdx, it returns
899 /// a pointer to the MachineOperand rather than an index.
900 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
901 const TargetRegisterInfo *TRI = nullptr) {
902 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
903 return (Idx == -1) ? nullptr : &getOperand(Idx);
906 /// Find the index of the first operand in the
907 /// operand list that is used to represent the predicate. It returns -1 if
909 int findFirstPredOperandIdx() const;
911 /// Find the index of the flag word operand that
912 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
913 /// getOperand(OpIdx) does not belong to an inline asm operand group.
915 /// If GroupNo is not NULL, it will receive the number of the operand group
916 /// containing OpIdx.
918 /// The flag operand is an immediate that can be decoded with methods like
919 /// InlineAsm::hasRegClassConstraint().
921 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
923 /// Compute the static register class constraint for operand OpIdx.
924 /// For normal instructions, this is derived from the MCInstrDesc.
925 /// For inline assembly it is derived from the flag words.
927 /// Returns NULL if the static register classs constraint cannot be
930 const TargetRegisterClass*
931 getRegClassConstraint(unsigned OpIdx,
932 const TargetInstrInfo *TII,
933 const TargetRegisterInfo *TRI) const;
935 /// \brief Applies the constraints (def/use) implied by this MI on \p Reg to
936 /// the given \p CurRC.
937 /// If \p ExploreBundle is set and MI is part of a bundle, all the
938 /// instructions inside the bundle will be taken into account. In other words,
939 /// this method accumulates all the constrains of the operand of this MI and
940 /// the related bundle if MI is a bundle or inside a bundle.
942 /// Returns the register class that statisfies both \p CurRC and the
943 /// constraints set by MI. Returns NULL if such a register class does not
946 /// \pre CurRC must not be NULL.
947 const TargetRegisterClass *getRegClassConstraintEffectForVReg(
948 unsigned Reg, const TargetRegisterClass *CurRC,
949 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
950 bool ExploreBundle = false) const;
952 /// \brief Applies the constraints (def/use) implied by the \p OpIdx operand
953 /// to the given \p CurRC.
955 /// Returns the register class that statisfies both \p CurRC and the
956 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
959 /// \pre CurRC must not be NULL.
960 /// \pre The operand at \p OpIdx must be a register.
961 const TargetRegisterClass *
962 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
963 const TargetInstrInfo *TII,
964 const TargetRegisterInfo *TRI) const;
966 /// Add a tie between the register operands at DefIdx and UseIdx.
967 /// The tie will cause the register allocator to ensure that the two
968 /// operands are assigned the same physical register.
970 /// Tied operands are managed automatically for explicit operands in the
971 /// MCInstrDesc. This method is for exceptional cases like inline asm.
972 void tieOperands(unsigned DefIdx, unsigned UseIdx);
974 /// Given the index of a tied register operand, find the
975 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
976 /// index of the tied operand which must exist.
977 unsigned findTiedOperandIdx(unsigned OpIdx) const;
979 /// Given the index of a register def operand,
980 /// check if the register def is tied to a source operand, due to either
981 /// two-address elimination or inline assembly constraints. Returns the
982 /// first tied use operand index by reference if UseOpIdx is not null.
983 bool isRegTiedToUseOperand(unsigned DefOpIdx,
984 unsigned *UseOpIdx = nullptr) const {
985 const MachineOperand &MO = getOperand(DefOpIdx);
986 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
989 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
993 /// Return true if the use operand of the specified index is tied to a def
994 /// operand. It also returns the def operand index by reference if DefOpIdx
996 bool isRegTiedToDefOperand(unsigned UseOpIdx,
997 unsigned *DefOpIdx = nullptr) const {
998 const MachineOperand &MO = getOperand(UseOpIdx);
999 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1002 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1006 /// Clears kill flags on all operands.
1007 void clearKillInfo();
1009 /// Replace all occurrences of FromReg with ToReg:SubIdx,
1010 /// properly composing subreg indices where necessary.
1011 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
1012 const TargetRegisterInfo &RegInfo);
1014 /// We have determined MI kills a register. Look for the
1015 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1016 /// add a implicit operand if it's not found. Returns true if the operand
1017 /// exists / is added.
1018 bool addRegisterKilled(unsigned IncomingReg,
1019 const TargetRegisterInfo *RegInfo,
1020 bool AddIfNotFound = false);
1022 /// Clear all kill flags affecting Reg. If RegInfo is
1023 /// provided, this includes super-register kills.
1024 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
1026 /// We have determined MI defined a register without a use.
1027 /// Look for the operand that defines it and mark it as IsDead. If
1028 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1029 /// true if the operand exists / is added.
1030 bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
1031 bool AddIfNotFound = false);
1033 /// Clear all dead flags on operands defining register @p Reg.
1034 void clearRegisterDeads(unsigned Reg);
1036 /// Mark all subregister defs of register @p Reg with the undef flag.
1037 /// This function is used when we determined to have a subregister def in an
1038 /// otherwise undefined super register.
1039 void addRegisterDefReadUndef(unsigned Reg);
1041 /// We have determined MI defines a register. Make sure there is an operand
1043 void addRegisterDefined(unsigned Reg,
1044 const TargetRegisterInfo *RegInfo = nullptr);
1046 /// Mark every physreg used by this instruction as
1047 /// dead except those in the UsedRegs list.
1049 /// On instructions with register mask operands, also add implicit-def
1050 /// operands for all registers in UsedRegs.
1051 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1052 const TargetRegisterInfo &TRI);
1054 /// Return true if it is safe to move this instruction. If
1055 /// SawStore is set to true, it means that there is a store (or call) between
1056 /// the instruction's location and its intended destination.
1057 bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const;
1059 /// Return true if this instruction may have an ordered
1060 /// or volatile memory reference, or if the information describing the memory
1061 /// reference is not available. Return false if it is known to have no
1062 /// ordered or volatile memory references.
1063 bool hasOrderedMemoryRef() const;
1065 /// Return true if this instruction is loading from a
1066 /// location whose value is invariant across the function. For example,
1067 /// loading a value from the constant pool or from the argument area of
1068 /// a function if it does not change. This should only return true of *all*
1069 /// loads the instruction does are invariant (if it does multiple loads).
1070 bool isInvariantLoad(AliasAnalysis *AA) const;
1072 /// If the specified instruction is a PHI that always merges together the
1073 /// same virtual register, return the register, otherwise return 0.
1074 unsigned isConstantValuePHI() const;
1076 /// Return true if this instruction has side effects that are not modeled
1077 /// by mayLoad / mayStore, etc.
1078 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1079 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1080 /// INLINEASM instruction, in which case the side effect property is encoded
1081 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1083 bool hasUnmodeledSideEffects() const;
1085 /// Return true if all the defs of this instruction are dead.
1086 bool allDefsAreDead() const;
1088 /// Copy implicit register operands from specified
1089 /// instruction to this instruction.
1090 void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI);
1093 // Debugging support
1095 void print(raw_ostream &OS, bool SkipOpers = false) const;
1098 //===--------------------------------------------------------------------===//
1099 // Accessors used to build up machine instructions.
1101 /// Add the specified operand to the instruction. If it is an implicit
1102 /// operand, it is added to the end of the operand list. If it is an
1103 /// explicit operand it is added at the end of the explicit operand list
1104 /// (before the first implicit operand).
1106 /// MF must be the machine function that was used to allocate this
1109 /// MachineInstrBuilder provides a more convenient interface for creating
1110 /// instructions and adding operands.
1111 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1113 /// Add an operand without providing an MF reference. This only works for
1114 /// instructions that are inserted in a basic block.
1116 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1118 void addOperand(const MachineOperand &Op);
1120 /// Replace the instruction descriptor (thus opcode) of
1121 /// the current instruction with a new one.
1122 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1124 /// Replace current source information with new such.
1125 /// Avoid using this, the constructor argument is preferable.
1126 void setDebugLoc(DebugLoc dl) {
1127 debugLoc = std::move(dl);
1128 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
1131 /// Erase an operand from an instruction, leaving it with one
1132 /// fewer operand than it started with.
1133 void RemoveOperand(unsigned i);
1135 /// Add a MachineMemOperand to the machine instruction.
1136 /// This function should be used only occasionally. The setMemRefs function
1137 /// is the primary method for setting up a MachineInstr's MemRefs list.
1138 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1140 /// Assign this MachineInstr's memory reference descriptor list.
1141 /// This does not transfer ownership.
1142 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
1143 MemRefs = NewMemRefs;
1144 NumMemRefs = uint8_t(NewMemRefsEnd - NewMemRefs);
1145 assert(NumMemRefs == NewMemRefsEnd - NewMemRefs && "Too many memrefs");
1148 /// Clear this MachineInstr's memory reference descriptor list.
1149 void clearMemRefs() {
1154 /// Break any tie involving OpIdx.
1155 void untieRegOperand(unsigned OpIdx) {
1156 MachineOperand &MO = getOperand(OpIdx);
1157 if (MO.isReg() && MO.isTied()) {
1158 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1165 /// If this instruction is embedded into a MachineFunction, return the
1166 /// MachineRegisterInfo object for the current function, otherwise
1168 MachineRegisterInfo *getRegInfo();
1170 /// Add all implicit def and use operands to this instruction.
1171 void addImplicitDefUseOperands(MachineFunction &MF);
1173 /// Unlink all of the register operands in this instruction from their
1174 /// respective use lists. This requires that the operands already be on their
1176 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1178 /// Add all of the register operands in this instruction from their
1179 /// respective use lists. This requires that the operands not be on their
1181 void AddRegOperandsToUseLists(MachineRegisterInfo&);
1183 /// Slow path for hasProperty when we're dealing with a bundle.
1184 bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
1186 /// \brief Implements the logic of getRegClassConstraintEffectForVReg for the
1187 /// this MI and the given operand index \p OpIdx.
1188 /// If the related operand does not constrained Reg, this returns CurRC.
1189 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1190 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1191 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1194 /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1195 /// instruction rather than by pointer value.
1196 /// The hashing and equality testing functions ignore definitions so this is
1197 /// useful for CSE, etc.
1198 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1199 static inline MachineInstr *getEmptyKey() {
1203 static inline MachineInstr *getTombstoneKey() {
1204 return reinterpret_cast<MachineInstr*>(-1);
1207 static unsigned getHashValue(const MachineInstr* const &MI);
1209 static bool isEqual(const MachineInstr* const &LHS,
1210 const MachineInstr* const &RHS) {
1211 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1212 LHS == getEmptyKey() || LHS == getTombstoneKey())
1214 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
1218 //===----------------------------------------------------------------------===//
1219 // Debugging Support
1221 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1226 } // End llvm namespace