2 //***************************************************************************
12 // 7/2/01 - Vikram Adve - Created
13 //**************************************************************************/
15 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
16 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/InstrForest.h"
20 #include "llvm/Support/DataTypes.h"
21 #include "llvm/Support/NonCopyable.h"
22 #include "llvm/Target/MachineInstrInfo.h"
24 template<class _MI, class _V> class ValOpIterator;
27 //---------------------------------------------------------------------------
28 // class MachineOperand
31 // Representation of each machine instruction operand.
32 // This class is designed so that you can allocate a vector of operands
33 // first and initialize each one later.
35 // E.g, for this VM instruction:
36 // ptr = alloca type, numElements
37 // we generate 2 machine instructions on the SPARC:
39 // mul Constant, Numelements -> Reg
40 // add %sp, Reg -> Ptr
42 // Each instruction has 3 operands, listed above. Of those:
43 // - Reg, NumElements, and Ptr are of operand type MO_Register.
44 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
46 // For the register operands, the virtual register type is as follows:
48 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
49 // MachineInstr* minstr will point to the instruction that computes reg.
51 // - %sp will be of virtual register type MO_MachineReg.
52 // The field regNum identifies the machine register.
54 // - NumElements will be of virtual register type MO_VirtualReg.
55 // The field Value* value identifies the value.
57 // - Ptr will also be of virtual register type MO_VirtualReg.
58 // Again, the field Value* value identifies the value.
60 //---------------------------------------------------------------------------
63 class MachineOperand {
65 enum MachineOperandType {
66 MO_VirtualRegister, // virtual register for *value
67 MO_MachineRegister, // pre-assigned machine register `regNum'
75 MachineOperandType opType;
78 Value* value; // BasicBlockVal for a label operand.
79 // ConstantVal for a non-address immediate.
80 // Virtual register for an SSA operand,
81 // including hidden operands required for
82 // the generated machine code.
83 int64_t immedVal; // constant value for an explicit constant
86 int regNum; // register number for an explicit register
87 // will be set for a value after reg allocation
88 bool isDef; // is this a defition for the value
91 /*ctor*/ MachineOperand ();
92 /*ctor*/ MachineOperand (MachineOperandType operandType,
94 /*copy ctor*/ MachineOperand (const MachineOperand&);
95 /*dtor*/ ~MachineOperand () {}
97 // Accessor methods. Caller is responsible for checking the
98 // operand type before invoking the corresponding accessor.
100 inline MachineOperandType getOperandType () const {
103 inline Value* getVRegValue () const {
104 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
105 opType == MO_PCRelativeDisp);
108 inline unsigned int getMachineRegNum() const {
109 assert(opType == MO_MachineRegister);
110 return (unsigned) regNum;
112 inline int64_t getImmedValue () const {
113 assert(opType >= MO_SignExtendedImmed || opType <= MO_PCRelativeDisp);
116 inline bool opIsDef () const {
121 friend ostream& operator<<(ostream& os, const MachineOperand& mop);
125 // These functions are provided so that a vector of operands can be
126 // statically allocated and individual ones can be initialized later.
127 // Give class MachineInstr gets access to these functions.
129 void Initialize (MachineOperandType operandType,
131 void InitializeConst (MachineOperandType operandType,
133 void InitializeReg (unsigned int regNum);
135 friend class MachineInstr;
136 friend class ValOpIterator<const MachineInstr, const Value>;
137 friend class ValOpIterator< MachineInstr, Value>;
142 // replaces the Value with its corresponding physical register afeter
143 // register allocation is complete
144 void setRegForValue(int reg) {
145 assert(opType == MO_VirtualRegister || opType == MO_CCRegister);
149 // used to get the reg number if when one is allocted (must be
150 // called only after reg alloc)
151 inline int getAllocatedRegNum() const {
152 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
153 opType == MO_MachineRegister);
162 MachineOperand::MachineOperand()
163 : opType(MO_VirtualRegister),
170 MachineOperand::MachineOperand(MachineOperandType operandType,
172 : opType(operandType),
179 MachineOperand::MachineOperand(const MachineOperand& mo)
184 case MO_VirtualRegister:
185 case MO_CCRegister: value = mo.value; break;
186 case MO_MachineRegister: regNum = mo.regNum; break;
187 case MO_SignExtendedImmed:
188 case MO_UnextendedImmed:
189 case MO_PCRelativeDisp: immedVal = mo.immedVal; break;
195 MachineOperand::Initialize(MachineOperandType operandType,
198 opType = operandType;
203 MachineOperand::InitializeConst(MachineOperandType operandType,
206 opType = operandType;
212 MachineOperand::InitializeReg(unsigned int _regNum)
214 opType = MO_MachineRegister;
216 regNum = (int) _regNum;
220 //---------------------------------------------------------------------------
221 // class MachineInstr
224 // Representation of each machine instruction.
226 // MachineOpCode must be an enum, defined separately for each target.
227 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
229 // opCodeMask is used to record variants of an instruction.
230 // E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
231 // ANNUL: if 1: Annul delay slot instruction.
232 // PREDICT-NOT-TAKEN: if 1: predict branch not taken.
233 // Instead of creating 4 different opcodes for BNZ, we create a single
234 // opcode and set bits in opCodeMask for each of these flags.
236 // There are 2 kinds of operands:
238 // (1) Explicit operands of the machine instruction in vector operands[]
240 // (2) "Implicit operands" are values implicitly used or defined by the
241 // machine instruction, such as arguments to a CALL, return value of
242 // a CALL (if any), and return value of a RETURN.
243 //---------------------------------------------------------------------------
245 class MachineInstr : public NonCopyable {
247 MachineOpCode opCode;
248 OpCodeMask opCodeMask; // extra bits for variants of an opcode
249 vector<MachineOperand> operands;
250 vector<Value*> implicitRefs; // values implicitly referenced by this
251 vector<bool> implicitIsDef; // machine instruction (eg, call args)
254 typedef ValOpIterator<const MachineInstr, const Value> val_op_const_iterator;
255 typedef ValOpIterator<const MachineInstr, Value> val_op_iterator;
258 /*ctor*/ MachineInstr (MachineOpCode _opCode,
259 OpCodeMask _opCodeMask = 0x0);
260 /*ctor*/ MachineInstr (MachineOpCode _opCode,
261 unsigned numOperands,
262 OpCodeMask _opCodeMask = 0x0);
263 inline ~MachineInstr () {}
264 const MachineOpCode getOpCode () const { return opCode; }
267 // Information about explicit operands of the instruction
269 unsigned int getNumOperands () const { return operands.size(); }
271 bool operandIsDefined(unsigned int i) const;
273 const MachineOperand& getOperand (unsigned int i) const;
274 MachineOperand& getOperand (unsigned int i);
277 // Information about implicit operands of the instruction
279 unsigned int getNumImplicitRefs() const{return implicitRefs.size();}
281 bool implicitRefIsDefined(unsigned int i) const;
283 const Value* getImplicitRef (unsigned int i) const;
284 Value* getImplicitRef (unsigned int i);
289 void dump (unsigned int indent = 0) const;
293 friend ostream& operator<<(ostream& os, const MachineInstr& minstr);
294 friend val_op_const_iterator;
295 friend val_op_iterator;
298 // Access to set the operands when building the machine instruction
299 void SetMachineOperand(unsigned int i,
300 MachineOperand::MachineOperandType operandType,
301 Value* _val, bool isDef=false);
302 void SetMachineOperand(unsigned int i,
303 MachineOperand::MachineOperandType operandType,
304 int64_t intValue, bool isDef=false);
305 void SetMachineOperand(unsigned int i,
309 void addImplicitRef (Value* val,
312 void setImplicitRef (unsigned int i,
318 inline MachineOperand&
319 MachineInstr::getOperand(unsigned int i)
321 assert(i < operands.size() && "getOperand() out of range!");
325 inline const MachineOperand&
326 MachineInstr::getOperand(unsigned int i) const
328 assert(i < operands.size() && "getOperand() out of range!");
333 MachineInstr::operandIsDefined(unsigned int i) const
335 return getOperand(i).opIsDef();
339 MachineInstr::implicitRefIsDefined(unsigned int i) const
341 assert(i < implicitIsDef.size() && "operand out of range!");
342 return implicitIsDef[i];
346 MachineInstr::getImplicitRef(unsigned int i) const
348 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
349 return implicitRefs[i];
353 MachineInstr::getImplicitRef(unsigned int i)
355 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
356 return implicitRefs[i];
360 MachineInstr::addImplicitRef(Value* val,
363 implicitRefs.push_back(val);
364 implicitIsDef.push_back(isDef);
368 MachineInstr::setImplicitRef(unsigned int i,
372 assert(i < implicitRefs.size() && "setImplicitRef() out of range!");
373 implicitRefs[i] = val;
374 implicitIsDef[i] = isDef;
378 template<class _MI, class _V>
379 class ValOpIterator : public std::forward_iterator<_V, ptrdiff_t> {
385 inline void skipToNextVal() {
386 while (i < minstr->getNumOperands() &&
387 ! ((minstr->operands[i].opType == MachineOperand::MO_VirtualRegister
388 || minstr->operands[i].opType == MachineOperand::MO_CCRegister)
389 && minstr->operands[i].value != NULL))
394 typedef ValOpIterator<_MI, _V> _Self;
396 inline ValOpIterator(_MI* _minstr) : i(0), minstr(_minstr) {
397 resultPos = TargetInstrDescriptors[minstr->opCode].resultPos;
401 inline _V* operator*() const { return minstr->getOperand(i).getVRegValue();}
403 const MachineOperand & getMachineOperand() const { return minstr->getOperand(i); }
405 inline _V* operator->() const { return operator*(); }
406 // inline bool isDef () const { return (((int) i) == resultPos); }
408 inline bool isDef () const { return minstr->getOperand(i).isDef; }
409 inline bool done () const { return (i == minstr->getNumOperands()); }
411 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
412 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
416 //---------------------------------------------------------------------------
417 // class MachineCodeForVMInstr
420 // Representation of the sequence of machine instructions created
421 // for a single VM instruction. Additionally records information
422 // about hidden and implicit values used by the machine instructions:
423 // about hidden values used by the machine instructions:
425 // "Temporary values" are intermediate values used in the machine
426 // instruction sequence, but not in the VM instruction
427 // Note that such values should be treated as pure SSA values with
428 // no interpretation of their operands (i.e., as a TmpInstruction
429 // object which actually represents such a value).
431 // (2) "Implicit uses" are values used in the VM instruction but not in
432 // the machine instruction sequence
434 //---------------------------------------------------------------------------
436 class MachineCodeForVMInstr: public vector<MachineInstr*>
439 vector<Value*> tempVec; // used by m/c instr but not VM instr
442 /*ctor*/ MachineCodeForVMInstr () {}
443 /*ctor*/ ~MachineCodeForVMInstr ();
445 const vector<Value*>& getTempValues () const { return tempVec; }
446 vector<Value*>& getTempValues () { return tempVec; }
448 void addTempValue (Value* val) { tempVec.push_back(val); }
450 // dropAllReferences() - This function drops all references within
451 // temporary (hidden) instructions created in implementing the original
452 // VM intruction. This ensures there are no remaining "uses" within
453 // these hidden instructions, before the values of a method are freed.
455 // Make this inline because it has to be called from class Instruction
456 // and inlining it avoids a serious circurality in link order.
457 inline void dropAllReferences() {
458 for (unsigned i=0, N=tempVec.size(); i < N; i++)
459 if (Instruction *I = dyn_cast<Instruction>(tempVec[i]))
460 I->dropAllReferences();
465 MachineCodeForVMInstr::~MachineCodeForVMInstr()
467 // Free the Value objects created to hold intermediate values
468 for (unsigned i=0, N=tempVec.size(); i < N; i++)
471 // Free the MachineInstr objects allocated, if any.
472 for (unsigned i=0, N=this->size(); i < N; i++)
477 //---------------------------------------------------------------------------
478 // class MachineCodeForBasicBlock
481 // Representation of the sequence of machine instructions created
482 // for a basic block.
483 //---------------------------------------------------------------------------
486 class MachineCodeForBasicBlock: public vector<MachineInstr*> {
488 typedef vector<MachineInstr*>::iterator iterator;
489 typedef vector<const MachineInstr*>::const_iterator const_iterator;
493 //---------------------------------------------------------------------------
495 //---------------------------------------------------------------------------
498 ostream& operator<< (ostream& os, const MachineInstr& minstr);
501 ostream& operator<< (ostream& os, const MachineOperand& mop);
504 void PrintMachineInstructions(const Method *method);
507 //**************************************************************************/