1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Annotation.h"
13 #include "Support/iterator"
14 #include "Support/NonCopyable.h"
19 typedef int MachineOpCode;
20 typedef int OpCodeMask;
21 typedef int InstrSchedClass;
23 //---------------------------------------------------------------------------
24 // class MachineOperand
27 // Representation of each machine instruction operand.
28 // This class is designed so that you can allocate a vector of operands
29 // first and initialize each one later.
31 // E.g, for this VM instruction:
32 // ptr = alloca type, numElements
33 // we generate 2 machine instructions on the SPARC:
35 // mul Constant, Numelements -> Reg
36 // add %sp, Reg -> Ptr
38 // Each instruction has 3 operands, listed above. Of those:
39 // - Reg, NumElements, and Ptr are of operand type MO_Register.
40 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
42 // For the register operands, the virtual register type is as follows:
44 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
45 // MachineInstr* minstr will point to the instruction that computes reg.
47 // - %sp will be of virtual register type MO_MachineReg.
48 // The field regNum identifies the machine register.
50 // - NumElements will be of virtual register type MO_VirtualReg.
51 // The field Value* value identifies the value.
53 // - Ptr will also be of virtual register type MO_VirtualReg.
54 // Again, the field Value* value identifies the value.
56 //---------------------------------------------------------------------------
59 class MachineOperand {
61 enum MachineOperandType {
62 MO_VirtualRegister, // virtual register for *value
63 MO_MachineRegister, // pre-assigned machine register `regNum'
71 // Bit fields of the flags variable used for different operand properties
72 static const char DEFFLAG = 0x1; // this is a def of the operand
73 static const char DEFUSEFLAG = 0x2; // this is both a def and a use
74 static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal)
75 static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal)
76 static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
77 static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
81 Value* value; // BasicBlockVal for a label operand.
82 // ConstantVal for a non-address immediate.
83 // Virtual register for an SSA operand,
84 // including hidden operands required for
85 // the generated machine code.
86 int64_t immedVal; // constant value for an explicit constant
89 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
90 char flags; // see bit field definitions above
91 int regNum; // register number for an explicit register
92 // will be set for a value after reg allocation
94 MachineOperand() : immedVal(0), opType(MO_VirtualRegister),
95 flags(0), regNum(-1) {}
96 MachineOperand(const MachineOperand &M)
97 : immedVal(M.immedVal), opType(M.opType), flags(M.flags), regNum(M.regNum) {
101 // Accessor methods. Caller is responsible for checking the
102 // operand type before invoking the corresponding accessor.
104 MachineOperandType getOperandType() const { return opType; }
106 inline Value* getVRegValue () const {
107 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
108 opType == MO_PCRelativeDisp);
111 inline Value* getVRegValueOrNull() const {
112 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
113 opType == MO_PCRelativeDisp)? value : NULL;
115 inline int getMachineRegNum() const {
116 assert(opType == MO_MachineRegister);
119 inline int64_t getImmedValue () const {
120 assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
123 bool opIsDef () const { return flags & DEFFLAG; }
124 bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
125 bool opHiBits32 () const { return flags & HIFLAG32; }
126 bool opLoBits32 () const { return flags & LOFLAG32; }
127 bool opHiBits64 () const { return flags & HIFLAG64; }
128 bool opLoBits64 () const { return flags & LOFLAG64; }
130 // used to check if a machine register has been allocated to this operand
131 inline bool hasAllocatedReg() const {
132 return (regNum >= 0 &&
133 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
134 opType == MO_MachineRegister));
137 // used to get the reg number if when one is allocated
138 inline int getAllocatedRegNum() const {
139 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
140 opType == MO_MachineRegister);
145 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
149 // Construction methods needed for fine-grain control.
150 // These must be accessed via coresponding methods in MachineInstr.
151 void markDef() { flags |= DEFFLAG; }
152 void markDefAndUse() { flags |= DEFUSEFLAG; }
153 void markHi32() { flags |= HIFLAG32; }
154 void markLo32() { flags |= LOFLAG32; }
155 void markHi64() { flags |= HIFLAG64; }
156 void markLo64() { flags |= LOFLAG64; }
158 // Replaces the Value with its corresponding physical register after
159 // register allocation is complete
160 void setRegForValue(int reg) {
161 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
162 opType == MO_MachineRegister);
166 friend class MachineInstr;
170 //---------------------------------------------------------------------------
171 // class MachineInstr
174 // Representation of each machine instruction.
176 // MachineOpCode must be an enum, defined separately for each target.
177 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
179 // opCodeMask is used to record variants of an instruction.
180 // E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
181 // ANNUL: if 1: Annul delay slot instruction.
182 // PREDICT-NOT-TAKEN: if 1: predict branch not taken.
183 // Instead of creating 4 different opcodes for BNZ, we create a single
184 // opcode and set bits in opCodeMask for each of these flags.
186 // There are 2 kinds of operands:
188 // (1) Explicit operands of the machine instruction in vector operands[]
190 // (2) "Implicit operands" are values implicitly used or defined by the
191 // machine instruction, such as arguments to a CALL, return value of
192 // a CALL (if any), and return value of a RETURN.
193 //---------------------------------------------------------------------------
195 class MachineInstr : public Annotable, // MachineInstrs are annotable
196 public NonCopyable { // Disable copy operations
197 MachineOpCode opCode; // the opcode
198 OpCodeMask opCodeMask; // extra bits for variants of an opcode
199 std::vector<MachineOperand> operands; // the operands
203 bool isDef, isDefAndUse;
205 ImplicitRef(Value *V, bool D, bool DU) : Val(V), isDef(D), isDefAndUse(DU){}
208 // implicitRefs - Values implicitly referenced by this machine instruction
210 std::vector<ImplicitRef> implicitRefs;
212 // regsUsed - all machine registers used for this instruction, including regs
213 // used to save values across the instruction. This is a bitset of registers.
214 std::vector<bool> regsUsed;
216 /*ctor*/ MachineInstr (MachineOpCode _opCode,
217 OpCodeMask _opCodeMask = 0);
218 /*ctor*/ MachineInstr (MachineOpCode _opCode,
219 unsigned numOperands,
220 OpCodeMask _opCodeMask = 0);
221 inline ~MachineInstr () {}
224 // Support to rewrite a machine instruction in place: for now, simply
225 // replace() and then set new operands with Set.*Operand methods below.
227 void replace (MachineOpCode _opCode,
228 unsigned numOperands,
229 OpCodeMask _opCodeMask = 0x0);
234 const MachineOpCode getOpCode() const { return opCode; }
237 // Information about explicit operands of the instruction
239 unsigned getNumOperands() const { return operands.size(); }
241 const MachineOperand& getOperand(unsigned i) const {
242 assert(i < operands.size() && "getOperand() out of range!");
245 MachineOperand& getOperand(unsigned i) {
246 assert(i < operands.size() && "getOperand() out of range!");
250 MachineOperand::MachineOperandType getOperandType(unsigned i) const {
251 return getOperand(i).getOperandType();
254 bool operandIsDefined(unsigned i) const {
255 return getOperand(i).opIsDef();
258 bool operandIsDefinedAndUsed(unsigned i) const {
259 return getOperand(i).opIsDefAndUse();
263 // Information about implicit operands of the instruction
265 unsigned getNumImplicitRefs() const{ return implicitRefs.size();}
267 const Value* getImplicitRef(unsigned i) const {
268 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
269 return implicitRefs[i].Val;
271 Value* getImplicitRef(unsigned i) {
272 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
273 return implicitRefs[i].Val;
276 bool implicitRefIsDefined(unsigned i) const {
277 assert(i < implicitRefs.size() && "implicitRefIsDefined() out of range!");
278 return implicitRefs[i].isDef;
280 bool implicitRefIsDefinedAndUsed(unsigned i) const {
281 assert(i < implicitRefs.size() && "implicitRefIsDef&Used() out of range!");
282 return implicitRefs[i].isDefAndUse;
285 void addImplicitRef(Value* V, bool isDef=false, bool isDefAndUse=false) {
286 implicitRefs.push_back(ImplicitRef(V, isDef, isDefAndUse));
289 void setImplicitRef(unsigned i, Value* V, bool isDef=false,
290 bool isDefAndUse=false) {
291 assert(i < implicitRefs.size() && "setImplicitRef() out of range!");
292 implicitRefs[i] = ImplicitRef(V, isDef, isDefAndUse);
296 // Information about registers used in this instruction
298 const std::vector<bool> &getRegsUsed() const { return regsUsed; }
300 // insertUsedReg - Add a register to the Used registers set...
301 void insertUsedReg(unsigned Reg) {
302 if (Reg >= regsUsed.size())
303 regsUsed.resize(Reg+1);
304 regsUsed[Reg] = true;
311 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
314 // Define iterators to access the Value operands of the Machine Instruction.
315 // begin() and end() are defined to produce these iterators...
317 template<class _MI, class _V> class ValOpIterator;
318 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
319 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
322 // Access to set the operands when building the machine instruction
324 void SetMachineOperandVal(unsigned i,
325 MachineOperand::MachineOperandType operandType,
326 Value* V, bool isDef=false, bool isDefAndUse=false);
327 void SetMachineOperandConst(unsigned i,
328 MachineOperand::MachineOperandType operandType,
330 void SetMachineOperandReg(unsigned i, int regNum, bool isDef=false,
331 bool isDefAndUse=false, bool isCCReg=false);
333 unsigned substituteValue(const Value* oldVal, Value* newVal,
334 bool defsOnly = true);
336 void setOperandHi32(unsigned i) { operands[i].markHi32(); }
337 void setOperandLo32(unsigned i) { operands[i].markLo32(); }
338 void setOperandHi64(unsigned i) { operands[i].markHi64(); }
339 void setOperandLo64(unsigned i) { operands[i].markLo64(); }
342 // SetRegForOperand - Replaces the Value for the operand with its allocated
343 // physical register after register allocation is complete.
345 void SetRegForOperand(unsigned i, int regNum);
348 // Iterator to enumerate machine operands.
350 template<class MITy, class VTy>
351 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
355 void skipToNextVal() {
356 while (i < MI->getNumOperands() &&
357 !((MI->getOperandType(i) == MachineOperand::MO_VirtualRegister ||
358 MI->getOperandType(i) == MachineOperand::MO_CCRegister)
359 && MI->getOperand(i).getVRegValue() != 0))
363 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
368 typedef ValOpIterator<MITy, VTy> _Self;
370 inline VTy operator*() const {
371 return MI->getOperand(i).getVRegValue();
374 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
375 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
377 inline VTy operator->() const { return operator*(); }
379 inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
380 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
382 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
383 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
385 inline bool operator==(const _Self &y) const {
388 inline bool operator!=(const _Self &y) const {
389 return !operator==(y);
392 static _Self begin(MITy MI) {
395 static _Self end(MITy MI) {
396 return _Self(MI, MI->getNumOperands());
400 // define begin() and end()
401 val_op_iterator begin() { return val_op_iterator::begin(this); }
402 val_op_iterator end() { return val_op_iterator::end(this); }
404 const_val_op_iterator begin() const {
405 return const_val_op_iterator::begin(this);
407 const_val_op_iterator end() const {
408 return const_val_op_iterator::end(this);
412 //---------------------------------------------------------------------------
414 //---------------------------------------------------------------------------
416 std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
418 std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
420 void PrintMachineInstructions(const Function *F);