2 //***************************************************************************
12 // 7/2/01 - Vikram Adve - Created
13 //**************************************************************************/
15 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
16 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/InstrForest.h"
20 #include "llvm/Support/DataTypes.h"
21 #include "llvm/Support/NonCopyable.h"
22 #include "llvm/CodeGen/TargetMachine.h"
24 template<class _MI, class _V> class ValOpIterator;
27 //---------------------------------------------------------------------------
28 // class MachineOperand
31 // Representation of each machine instruction operand.
32 // This class is designed so that you can allocate a vector of operands
33 // first and initialize each one later.
35 // E.g, for this VM instruction:
36 // ptr = alloca type, numElements
37 // we generate 2 machine instructions on the SPARC:
39 // mul Constant, Numelements -> Reg
40 // add %sp, Reg -> Ptr
42 // Each instruction has 3 operands, listed above. Of those:
43 // - Reg, NumElements, and Ptr are of operand type MO_Register.
44 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
46 // For the register operands, the virtual register type is as follows:
48 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
49 // MachineInstr* minstr will point to the instruction that computes reg.
51 // - %sp will be of virtual register type MO_MachineReg.
52 // The field regNum identifies the machine register.
54 // - NumElements will be of virtual register type MO_VirtualReg.
55 // The field Value* value identifies the value.
57 // - Ptr will also be of virtual register type MO_VirtualReg.
58 // Again, the field Value* value identifies the value.
60 //---------------------------------------------------------------------------
62 class MachineOperand {
64 enum MachineOperandType {
65 MO_VirtualRegister, // virtual register for *value
66 MO_MachineRegister, // pre-assigned machine register `regNum'
74 MachineOperandType opType;
77 Value* value; // BasicBlockVal for a label operand.
78 // ConstantVal for a non-address immediate.
79 // Virtual register for an SSA operand,
80 // including hidden operands required for
81 // the generated machine code.
83 unsigned int regNum; // register number for an explicit register
85 int64_t immedVal; // constant value for an explicit constant
88 bool isDef; // is this a defition for the value
89 // made public for faster access
92 /*ctor*/ MachineOperand ();
93 /*ctor*/ MachineOperand (MachineOperandType operandType,
95 /*copy ctor*/ MachineOperand (const MachineOperand&);
96 /*dtor*/ ~MachineOperand () {}
98 // Accessor methods. Caller is responsible for checking the
99 // operand type before invoking the corresponding accessor.
101 inline MachineOperandType getOperandType () const {
104 inline Value* getVRegValue () const {
105 assert(opType == MO_VirtualRegister || opType == MO_CCRegister);
108 inline unsigned int getMachineRegNum() const {
109 assert(opType == MO_MachineRegister);
112 inline int64_t getImmedValue () const {
113 assert(opType >= MO_SignExtendedImmed || opType <= MO_PCRelativeDisp);
116 inline bool opIsDef () const {
121 friend ostream& operator<<(ostream& os, const MachineOperand& mop);
125 // These functions are provided so that a vector of operands can be
126 // statically allocated and individual ones can be initialized later.
127 // Give class MachineInstr gets access to these functions.
129 void Initialize (MachineOperandType operandType,
131 void InitializeConst (MachineOperandType operandType,
133 void InitializeReg (unsigned int regNum);
135 friend class MachineInstr;
136 friend class ValOpIterator<const MachineInstr, const Value>;
137 friend class ValOpIterator< MachineInstr, Value>;
147 MachineOperand::MachineOperand()
148 : opType(MO_VirtualRegister),
156 MachineOperand::MachineOperand(MachineOperandType operandType,
158 : opType(operandType),
166 MachineOperand::MachineOperand(const MachineOperand& mo)
171 case MO_VirtualRegister:
172 case MO_CCRegister: value = mo.value; break;
173 case MO_MachineRegister: regNum = mo.regNum; break;
174 case MO_SignExtendedImmed:
175 case MO_UnextendedImmed:
176 case MO_PCRelativeDisp: immedVal = mo.immedVal; break;
182 MachineOperand::Initialize(MachineOperandType operandType,
185 opType = operandType;
190 MachineOperand::InitializeConst(MachineOperandType operandType,
193 opType = operandType;
199 MachineOperand::InitializeReg(unsigned int _regNum)
201 opType = MO_MachineRegister;
207 //---------------------------------------------------------------------------
208 // class MachineInstr
211 // Representation of each machine instruction.
213 // MachineOpCode must be an enum, defined separately for each target.
214 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
216 // opCodeMask is used to record variants of an instruction.
217 // E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
218 // ANNUL: if 1: Annul delay slot instruction.
219 // PREDICT-NOT-TAKEN: if 1: predict branch not taken.
220 // Instead of creating 4 different opcodes for BNZ, we create a single
221 // opcode and set bits in opCodeMask for each of these flags.
222 //---------------------------------------------------------------------------
224 class MachineInstr : public NonCopyable {
226 MachineOpCode opCode;
227 OpCodeMask opCodeMask; // extra bits for variants of an opcode
228 vector<MachineOperand> operands;
231 typedef ValOpIterator<const MachineInstr, const Value> val_op_const_iterator;
232 typedef ValOpIterator<const MachineInstr, Value> val_op_iterator;
235 /*ctor*/ MachineInstr (MachineOpCode _opCode,
236 OpCodeMask _opCodeMask = 0x0);
237 /*ctor*/ MachineInstr (MachineOpCode _opCode,
238 unsigned numOperands,
239 OpCodeMask _opCodeMask = 0x0);
240 inline ~MachineInstr () {}
242 const MachineOpCode getOpCode () const;
244 unsigned int getNumOperands () const;
246 const MachineOperand& getOperand (unsigned int i) const;
247 MachineOperand& getOperand (unsigned int i);
249 bool operandIsDefined(unsigned int i) const;
251 void dump (unsigned int indent = 0) const;
258 friend ostream& operator<<(ostream& os, const MachineInstr& minstr);
259 friend val_op_const_iterator;
260 friend val_op_iterator;
263 // Access to set the operands when building the machine instruction
264 void SetMachineOperand(unsigned int i,
265 MachineOperand::MachineOperandType operandType,
266 Value* _val, bool isDef=false);
267 void SetMachineOperand(unsigned int i,
268 MachineOperand::MachineOperandType operandType,
269 int64_t intValue, bool isDef=false);
270 void SetMachineOperand(unsigned int i,
275 inline const MachineOpCode
276 MachineInstr::getOpCode() const
282 MachineInstr::getNumOperands() const
284 return operands.size();
287 inline MachineOperand&
288 MachineInstr::getOperand(unsigned int i)
290 assert(i < operands.size() && "getOperand() out of range!");
294 inline const MachineOperand&
295 MachineInstr::getOperand(unsigned int i) const
297 assert(i < operands.size() && "getOperand() out of range!");
302 MachineInstr::operandIsDefined(unsigned int i) const
304 return getOperand(i).opIsDef();
308 template<class _MI, class _V>
309 class ValOpIterator : public std::forward_iterator<_V, ptrdiff_t> {
315 inline void skipToNextVal() {
316 while (i < minstr->getNumOperands() &&
317 ! ((minstr->operands[i].opType == MachineOperand::MO_VirtualRegister
318 || minstr->operands[i].opType == MachineOperand::MO_CCRegister)
319 && minstr->operands[i].value != NULL))
324 typedef ValOpIterator<_MI, _V> _Self;
326 inline ValOpIterator(_MI* _minstr) : i(0), minstr(_minstr) {
327 resultPos = TargetInstrDescriptors[minstr->opCode].resultPos;
331 inline _V* operator*() const { return minstr->getOperand(i).getVRegValue();}
332 inline _V* operator->() const { return operator*(); }
333 // inline bool isDef () const { return (((int) i) == resultPos); }
335 inline bool isDef () const { return minstr->getOperand(i).isDef; }
336 inline bool done () const { return (i == minstr->getNumOperands()); }
338 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
339 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
343 //---------------------------------------------------------------------------
344 // class MachineCodeForVMInstr
347 // Representation of the sequence of machine instructions created
348 // for a single VM instruction. Additionally records any temporary
349 // "values" used as intermediate values in this sequence.
350 // Note that such values should be treated as pure SSA values with
351 // no interpretation of their operands (i.e., as a TmpInstruction object
352 // which actually represents such a value).
354 //---------------------------------------------------------------------------
356 class MachineCodeForVMInstr: public vector<MachineInstr*>
359 vector<Value*> tempVec;
362 /*ctor*/ MachineCodeForVMInstr () {}
363 /*ctor*/ ~MachineCodeForVMInstr ();
365 const vector<Value*>&
366 getTempValues () const { return tempVec; }
368 void addTempValue (Value* val)
369 { tempVec.push_back(val); }
371 // dropAllReferences() - This function drops all references within
372 // temporary (hidden) instructions created in implementing the original
373 // VM intruction. This ensures there are no remaining "uses" within
374 // these hidden instructions, before the values of a method are freed.
376 // Make this inline because it has to be called from class Instruction
377 // and inlining it avoids a serious circurality in link order.
378 inline void dropAllReferences() {
379 for (unsigned i=0, N=tempVec.size(); i < N; i++)
380 if (tempVec[i]->getValueType() == Value::InstructionVal)
381 ((Instruction*) tempVec[i])->dropAllReferences();
386 MachineCodeForVMInstr::~MachineCodeForVMInstr()
388 // Free the Value objects created to hold intermediate values
389 for (unsigned i=0, N=tempVec.size(); i < N; i++)
392 // Free the MachineInstr objects allocated, if any.
393 for (unsigned i=0, N=this->size(); i < N; i++)
398 //---------------------------------------------------------------------------
399 // class MachineCodeForBasicBlock
402 // Representation of the sequence of machine instructions created
403 // for a basic block.
404 //---------------------------------------------------------------------------
407 class MachineCodeForBasicBlock: public vector<MachineInstr*> {
409 typedef vector<MachineInstr*>::iterator iterator;
410 typedef vector<const MachineInstr*>::const_iterator const_iterator;
414 //---------------------------------------------------------------------------
415 // Target-independent utility routines for creating machine instructions
416 //---------------------------------------------------------------------------
419 //------------------------------------------------------------------------
420 // Function Set2OperandsFromInstr
421 // Function Set3OperandsFromInstr
423 // For the common case of 2- and 3-operand arithmetic/logical instructions,
424 // set the m/c instr. operands directly from the VM instruction's operands.
425 // Check whether the first or second operand is 0 and can use a dedicated
427 // Check whether the second operand should use an immediate field or register.
428 // (First and third operands are never immediates for such instructions.)
431 // canDiscardResult: Specifies that the result operand can be discarded
432 // by using the dedicated "0"
434 // op1position, op2position and resultPosition: Specify in which position
435 // in the machine instruction the 3 operands (arg1, arg2
436 // and result) should go.
438 // RETURN VALUE: unsigned int flags, where
439 // flags & 0x01 => operand 1 is constant and needs a register
440 // flags & 0x02 => operand 2 is constant and needs a register
441 //------------------------------------------------------------------------
443 void Set2OperandsFromInstr (MachineInstr* minstr,
444 InstructionNode* vmInstrNode,
445 const TargetMachine& targetMachine,
446 bool canDiscardResult = false,
448 int resultPosition = 1);
450 void Set3OperandsFromInstr (MachineInstr* minstr,
451 InstructionNode* vmInstrNode,
452 const TargetMachine& targetMachine,
453 bool canDiscardResult = false,
456 int resultPosition = 2);
458 MachineOperand::MachineOperandType
459 ChooseRegOrImmed(Value* val,
460 MachineOpCode opCode,
461 const TargetMachine& targetMachine,
463 unsigned int& getMachineRegNum,
464 int64_t& getImmedValue);
467 ostream& operator<<(ostream& os, const MachineInstr& minstr);
470 ostream& operator<<(ostream& os, const MachineOperand& mop);
473 void PrintMachineInstructions (const Method *method);
476 //**************************************************************************/