1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Annotation.h"
13 #include "llvm/Target/MRegisterInfo.h"
14 #include "Support/iterator"
15 #include "Support/NonCopyable.h"
19 class MachineBasicBlock;
22 typedef int MachineOpCode;
24 /// MOTy - MachineOperandType - This namespace contains an enum that describes
25 /// how the machine operand is used by the instruction: is it read, defined, or
26 /// both? Note that the MachineInstr/Operator class currently uses bool
27 /// arguments to represent this information instead of an enum. Eventually this
28 /// should change over to use this _easier to read_ representation instead.
32 Use, /// This machine operand is only read by the instruction
33 Def, /// This machine operand is only written by the instruction
34 UseAndDef /// This machine operand is read AND written
38 //---------------------------------------------------------------------------
39 // class MachineOperand
42 // Representation of each machine instruction operand.
43 // This class is designed so that you can allocate a vector of operands
44 // first and initialize each one later.
46 // E.g, for this VM instruction:
47 // ptr = alloca type, numElements
48 // we generate 2 machine instructions on the SPARC:
50 // mul Constant, Numelements -> Reg
51 // add %sp, Reg -> Ptr
53 // Each instruction has 3 operands, listed above. Of those:
54 // - Reg, NumElements, and Ptr are of operand type MO_Register.
55 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
57 // For the register operands, the virtual register type is as follows:
59 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
60 // MachineInstr* minstr will point to the instruction that computes reg.
62 // - %sp will be of virtual register type MO_MachineReg.
63 // The field regNum identifies the machine register.
65 // - NumElements will be of virtual register type MO_VirtualReg.
66 // The field Value* value identifies the value.
68 // - Ptr will also be of virtual register type MO_VirtualReg.
69 // Again, the field Value* value identifies the value.
71 //---------------------------------------------------------------------------
73 class MachineOperand {
75 enum MachineOperandType {
76 MO_VirtualRegister, // virtual register for *value
77 MO_MachineRegister, // pre-assigned machine register `regNum'
82 MO_MachineBasicBlock, // MachineBasicBlock reference
83 MO_FrameIndex, // Abstract Stack Frame Index
87 // Bit fields of the flags variable used for different operand properties
88 static const char DEFFLAG = 0x01; // this is a def of the operand
89 static const char DEFUSEFLAG = 0x02; // this is both a def and a use
90 static const char HIFLAG32 = 0x04; // operand is %hi32(value_or_immedVal)
91 static const char LOFLAG32 = 0x08; // operand is %lo32(value_or_immedVal)
92 static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
93 static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
95 static const char USEDEFMASK = 0x03;
99 Value* value; // BasicBlockVal for a label operand.
100 // ConstantVal for a non-address immediate.
101 // Virtual register for an SSA operand,
102 // including hidden operands required for
103 // the generated machine code.
104 int64_t immedVal; // constant value for an explicit constant
106 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
109 char flags; // see bit field definitions above
110 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
111 int regNum; // register number for an explicit register
112 // will be set for a value after reg allocation
117 opType(MO_VirtualRegister),
120 MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
126 MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
131 case MOTy::Use: flags = 0; break;
132 case MOTy::Def: flags = DEFFLAG; break;
133 case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
134 default: assert(0 && "Invalid value for UseTy!");
138 MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy)
139 : value(V), opType(OpTy), regNum(-1) {
141 case MOTy::Use: flags = 0; break;
142 case MOTy::Def: flags = DEFFLAG; break;
143 case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
144 default: assert(0 && "Invalid value for UseTy!");
148 MachineOperand(MachineBasicBlock *mbb)
149 : MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) {}
152 MachineOperand(const MachineOperand &M)
153 : immedVal(M.immedVal),
160 // Accessor methods. Caller is responsible for checking the
161 // operand type before invoking the corresponding accessor.
163 MachineOperandType getType() const { return opType; }
166 // This is to finally stop caring whether we have a virtual or machine
167 // register -- an easier interface is to simply call both virtual and machine
168 // registers essentially the same, yet be able to distinguish when
169 // necessary. Thus the instruction selector can just add registers without
170 // abandon, and the register allocator won't be confused.
171 bool isVirtualRegister() const {
172 return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
173 && regNum >= MRegisterInfo::FirstVirtualRegister;
175 bool isPhysicalRegister() const {
176 return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
177 && regNum < MRegisterInfo::FirstVirtualRegister;
179 bool isRegister() const { return isVirtualRegister() || isPhysicalRegister();}
180 bool isMachineRegister() const { return !isVirtualRegister(); }
181 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
182 bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; }
183 bool isImmediate() const {
184 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed;
186 bool isFrameIndex() const { return opType == MO_FrameIndex; }
188 Value* getVRegValue() const {
189 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
193 Value* getVRegValueOrNull() const {
194 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
195 isPCRelativeDisp()) ? value : NULL;
197 int getMachineRegNum() const {
198 assert(opType == MO_MachineRegister);
201 int64_t getImmedValue() const { assert(isImmediate()); return immedVal; }
202 MachineBasicBlock *getMachineBasicBlock() const {
203 assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
206 int getFrameIndex() const { assert(isFrameIndex()); return immedVal; }
208 bool opIsUse () const { return (flags & USEDEFMASK) == 0; }
209 bool opIsDef () const { return flags & DEFFLAG; }
210 bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
211 bool opHiBits32 () const { return flags & HIFLAG32; }
212 bool opLoBits32 () const { return flags & LOFLAG32; }
213 bool opHiBits64 () const { return flags & HIFLAG64; }
214 bool opLoBits64 () const { return flags & LOFLAG64; }
216 // used to check if a machine register has been allocated to this operand
217 bool hasAllocatedReg() const {
218 return (regNum >= 0 &&
219 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
220 opType == MO_MachineRegister));
223 // used to get the reg number if when one is allocated
224 int getAllocatedRegNum() const {
225 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
226 opType == MO_MachineRegister);
230 unsigned getReg() const {
231 assert(hasAllocatedReg() && "Cannot call MachineOperand::getReg()!");
235 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
239 // Construction methods needed for fine-grain control.
240 // These must be accessed via coresponding methods in MachineInstr.
241 void markHi32() { flags |= HIFLAG32; }
242 void markLo32() { flags |= LOFLAG32; }
243 void markHi64() { flags |= HIFLAG64; }
244 void markLo64() { flags |= LOFLAG64; }
246 // Replaces the Value with its corresponding physical register after
247 // register allocation is complete
248 void setRegForValue(int reg) {
249 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
250 opType == MO_MachineRegister);
254 friend class MachineInstr;
258 //---------------------------------------------------------------------------
259 // class MachineInstr
262 // Representation of each machine instruction.
264 // MachineOpCode must be an enum, defined separately for each target.
265 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
267 // There are 2 kinds of operands:
269 // (1) Explicit operands of the machine instruction in vector operands[]
271 // (2) "Implicit operands" are values implicitly used or defined by the
272 // machine instruction, such as arguments to a CALL, return value of
273 // a CALL (if any), and return value of a RETURN.
274 //---------------------------------------------------------------------------
276 class MachineInstr: public NonCopyable { // Disable copy operations
278 MachineOpCode opCode; // the opcode
279 std::vector<MachineOperand> operands; // the operands
280 unsigned numImplicitRefs; // number of implicit operands
282 MachineOperand& getImplicitOp(unsigned i) {
283 assert(i < numImplicitRefs && "implicit ref# out of range!");
284 return operands[i + operands.size() - numImplicitRefs];
286 const MachineOperand& getImplicitOp(unsigned i) const {
287 assert(i < numImplicitRefs && "implicit ref# out of range!");
288 return operands[i + operands.size() - numImplicitRefs];
291 // regsUsed - all machine registers used for this instruction, including regs
292 // used to save values across the instruction. This is a bitset of registers.
293 std::vector<bool> regsUsed;
295 // OperandComplete - Return true if it's illegal to add a new operand
296 bool OperandsComplete() const;
299 MachineInstr(MachineOpCode Opcode);
300 MachineInstr(MachineOpCode Opcode, unsigned numOperands);
302 /// MachineInstr ctor - This constructor only does a _reserve_ of the
303 /// operands, not a resize for them. It is expected that if you use this that
304 /// you call add* methods below to fill up the operands, instead of the Set
305 /// methods. Eventually, the "resizing" ctors will be phased out.
307 MachineInstr(MachineOpCode Opcode, unsigned numOperands, bool XX, bool YY);
309 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
310 /// the MachineInstr is created and added to the end of the specified basic
313 MachineInstr(MachineBasicBlock *MBB, MachineOpCode Opcode, unsigned numOps);
318 const MachineOpCode getOpcode() const { return opCode; }
319 const MachineOpCode getOpCode() const { return opCode; }
322 // Information about explicit operands of the instruction
324 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
326 const MachineOperand& getOperand(unsigned i) const {
327 assert(i < getNumOperands() && "getOperand() out of range!");
330 MachineOperand& getOperand(unsigned i) {
331 assert(i < getNumOperands() && "getOperand() out of range!");
336 MachineOperand::MachineOperandType getOperandType(unsigned i) const {
337 return getOperand(i).getType();
340 // FIXME: ELIMINATE: Misleading name: Definition not defined.
341 bool operandIsDefined(unsigned i) const {
342 return getOperand(i).opIsDef();
345 bool operandIsDefinedAndUsed(unsigned i) const {
346 return getOperand(i).opIsDefAndUse();
350 // Information about implicit operands of the instruction
352 unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
354 const Value* getImplicitRef(unsigned i) const {
355 return getImplicitOp(i).getVRegValue();
357 Value* getImplicitRef(unsigned i) {
358 return getImplicitOp(i).getVRegValue();
361 bool implicitRefIsDefined(unsigned i) const {
362 return getImplicitOp(i).opIsDef();
364 bool implicitRefIsDefinedAndUsed(unsigned i) const {
365 return getImplicitOp(i).opIsDefAndUse();
367 inline void addImplicitRef (Value* V,
368 bool isDef=false,bool isDefAndUse=false);
369 inline void setImplicitRef (unsigned i, Value* V,
370 bool isDef=false, bool isDefAndUse=false);
373 // Information about registers used in this instruction
375 const std::vector<bool> &getRegsUsed() const { return regsUsed; }
377 // insertUsedReg - Add a register to the Used registers set...
378 void insertUsedReg(unsigned Reg) {
379 if (Reg >= regsUsed.size())
380 regsUsed.resize(Reg+1);
381 regsUsed[Reg] = true;
387 void print(std::ostream &OS, const TargetMachine &TM) const;
389 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
392 // Define iterators to access the Value operands of the Machine Instruction.
393 // Note that these iterators only enumerate the explicit operands.
394 // begin() and end() are defined to produce these iterators...
396 template<class _MI, class _V> class ValOpIterator;
397 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
398 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
401 //===--------------------------------------------------------------------===//
402 // Accessors to add operands when building up machine instructions
405 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
408 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
409 assert(!OperandsComplete() &&
410 "Trying to add an operand to a machine instr that is already done!");
411 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
412 !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def)));
415 void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) {
416 assert(!OperandsComplete() &&
417 "Trying to add an operand to a machine instr that is already done!");
418 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
422 /// addRegOperand - Add a symbolic virtual register reference...
424 void addRegOperand(int reg, bool isDef) {
425 assert(!OperandsComplete() &&
426 "Trying to add an operand to a machine instr that is already done!");
427 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
428 isDef ? MOTy::Def : MOTy::Use));
431 /// addRegOperand - Add a symbolic virtual register reference...
433 void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
434 assert(!OperandsComplete() &&
435 "Trying to add an operand to a machine instr that is already done!");
436 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
440 /// addPCDispOperand - Add a PC relative displacement operand to the MI
442 void addPCDispOperand(Value *V) {
443 assert(!OperandsComplete() &&
444 "Trying to add an operand to a machine instr that is already done!");
445 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp,
449 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
451 void addMachineRegOperand(int reg, bool isDef) {
452 assert(!OperandsComplete() &&
453 "Trying to add an operand to a machine instr that is already done!");
454 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
455 isDef ? MOTy::Def : MOTy::Use));
459 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
461 void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
462 assert(!OperandsComplete() &&
463 "Trying to add an operand to a machine instr that is already done!");
464 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
469 /// addZeroExtImmOperand - Add a zero extended constant argument to the
470 /// machine instruction.
472 void addZeroExtImmOperand(int64_t intValue) {
473 assert(!OperandsComplete() &&
474 "Trying to add an operand to a machine instr that is already done!");
475 operands.push_back(MachineOperand(intValue,
476 MachineOperand::MO_UnextendedImmed));
479 /// addSignExtImmOperand - Add a zero extended constant argument to the
480 /// machine instruction.
482 void addSignExtImmOperand(int64_t intValue) {
483 assert(!OperandsComplete() &&
484 "Trying to add an operand to a machine instr that is already done!");
485 operands.push_back(MachineOperand(intValue,
486 MachineOperand::MO_SignExtendedImmed));
489 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
490 assert(!OperandsComplete() &&
491 "Trying to add an operand to a machine instr that is already done!");
492 operands.push_back(MachineOperand(MBB));
495 /// addFrameIndexOperand - Add an abstract frame index to the instruction
497 void addFrameIndexOperand(unsigned Idx) {
498 assert(!OperandsComplete() &&
499 "Trying to add an operand to a machine instr that is already done!");
500 operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex));
504 //===--------------------------------------------------------------------===//
505 // Accessors used to modify instructions in place.
507 // FIXME: Move this stuff to MachineOperand itself!
509 /// replace - Support to rewrite a machine instruction in place: for now,
510 /// simply replace() and then set new operands with Set.*Operand methods
513 void replace(MachineOpCode Opcode, unsigned numOperands);
515 // Access to set the operands when building the machine instruction
517 void SetMachineOperandVal (unsigned i,
518 MachineOperand::MachineOperandType operandType,
521 bool isDefAndUse=false);
523 void SetMachineOperandConst (unsigned i,
524 MachineOperand::MachineOperandType operandType,
527 void SetMachineOperandReg (unsigned i,
532 unsigned substituteValue(const Value* oldVal, Value* newVal,
533 bool defsOnly = true);
535 void setOperandHi32(unsigned i) { operands[i].markHi32(); }
536 void setOperandLo32(unsigned i) { operands[i].markLo32(); }
537 void setOperandHi64(unsigned i) { operands[i].markHi64(); }
538 void setOperandLo64(unsigned i) { operands[i].markLo64(); }
541 // SetRegForOperand - Replaces the Value for the operand with its allocated
542 // physical register after register allocation is complete.
544 void SetRegForOperand(unsigned i, int regNum);
547 // Iterator to enumerate machine operands.
549 template<class MITy, class VTy>
550 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
554 void skipToNextVal() {
555 while (i < MI->getNumOperands() &&
556 !( (MI->getOperandType(i) == MachineOperand::MO_VirtualRegister ||
557 MI->getOperandType(i) == MachineOperand::MO_CCRegister)
558 && MI->getOperand(i).getVRegValue() != 0))
562 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
567 typedef ValOpIterator<MITy, VTy> _Self;
569 inline VTy operator*() const {
570 return MI->getOperand(i).getVRegValue();
573 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
574 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
576 inline VTy operator->() const { return operator*(); }
578 inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
579 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
581 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
582 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
584 inline bool operator==(const _Self &y) const {
587 inline bool operator!=(const _Self &y) const {
588 return !operator==(y);
591 static _Self begin(MITy MI) {
594 static _Self end(MITy MI) {
595 return _Self(MI, MI->getNumOperands());
599 // define begin() and end()
600 val_op_iterator begin() { return val_op_iterator::begin(this); }
601 val_op_iterator end() { return val_op_iterator::end(this); }
603 const_val_op_iterator begin() const {
604 return const_val_op_iterator::begin(this);
606 const_val_op_iterator end() const {
607 return const_val_op_iterator::end(this);
612 // Define here to enable inlining of the functions used.
614 void MachineInstr::addImplicitRef(Value* V,
619 addRegOperand(V, isDef, isDefAndUse);
622 void MachineInstr::setImplicitRef(unsigned i,
627 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
628 SetMachineOperandVal(i + getNumOperands(),
629 MachineOperand::MO_VirtualRegister,
630 V, isDef, isDefAndUse);
634 //---------------------------------------------------------------------------
636 //---------------------------------------------------------------------------
638 std::ostream& operator<< (std::ostream& os,
639 const MachineInstr& minstr);
641 std::ostream& operator<< (std::ostream& os,
642 const MachineOperand& mop);
644 void PrintMachineInstructions (const Function *F);