1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/Target/TargetOpcodes.h"
22 #include "llvm/ADT/ilist.h"
23 #include "llvm/ADT/ilist_node.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/DenseMapInfo.h"
27 #include "llvm/Support/DebugLoc.h"
32 template <typename T> class SmallVectorImpl;
34 class TargetInstrInfo;
35 class TargetRegisterClass;
36 class TargetRegisterInfo;
37 class MachineFunction;
38 class MachineMemOperand;
40 //===----------------------------------------------------------------------===//
41 /// MachineInstr - Representation of each machine instruction.
43 class MachineInstr : public ilist_node<MachineInstr> {
45 typedef MachineMemOperand **mmo_iterator;
47 /// Flags to specify different kinds of comments to output in
48 /// assembly code. These flags carry semantic information not
49 /// otherwise easily derivable from the IR text.
57 FrameSetup = 1 << 0, // Instruction is used as a part of
58 // function frame setup code.
59 InsideBundle = 1 << 1 // Instruction is inside a bundle (not
60 // the first MI in a bundle)
63 const MCInstrDesc *MCID; // Instruction descriptor.
65 uint8_t Flags; // Various bits of additional
66 // information about machine
69 uint8_t AsmPrinterFlags; // Various bits of information used by
70 // the AsmPrinter to emit helpful
71 // comments. This is *not* semantic
72 // information. Do not use this for
73 // anything other than to convey comment
74 // information to AsmPrinter.
76 std::vector<MachineOperand> Operands; // the operands
77 mmo_iterator MemRefs; // information on memory references
78 mmo_iterator MemRefsEnd;
79 MachineBasicBlock *Parent; // Pointer to the owning basic block.
80 DebugLoc debugLoc; // Source line information.
82 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
83 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
85 // Intrusive list support
86 friend struct ilist_traits<MachineInstr>;
87 friend struct ilist_traits<MachineBasicBlock>;
88 void setParent(MachineBasicBlock *P) { Parent = P; }
90 /// MachineInstr ctor - This constructor creates a copy of the given
91 /// MachineInstr in the given MachineFunction.
92 MachineInstr(MachineFunction &, const MachineInstr &);
94 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
95 /// MCID NULL and no operands.
98 // The next two constructors have DebugLoc and non-DebugLoc versions;
99 // over time, the non-DebugLoc versions should be phased out and eventually
102 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
103 /// implicit operands. It reserves space for the number of operands specified
104 /// by the MCInstrDesc. The version with a DebugLoc should be preferred.
105 explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
107 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
108 /// the MachineInstr is created and added to the end of the specified basic
109 /// block. The version with a DebugLoc should be preferred.
110 MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
112 /// MachineInstr ctor - This constructor create a MachineInstr and add the
113 /// implicit operands. It reserves space for number of operands specified by
114 /// MCInstrDesc. An explicit DebugLoc is supplied.
115 explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
118 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
119 /// the MachineInstr is created and added to the end of the specified basic
121 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
122 const MCInstrDesc &MCID);
126 // MachineInstrs are pool-allocated and owned by MachineFunction.
127 friend class MachineFunction;
130 const MachineBasicBlock* getParent() const { return Parent; }
131 MachineBasicBlock* getParent() { return Parent; }
133 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
135 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
137 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
139 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
141 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
143 bool getAsmPrinterFlag(CommentFlag Flag) const {
144 return AsmPrinterFlags & Flag;
147 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
149 void setAsmPrinterFlag(CommentFlag Flag) {
150 AsmPrinterFlags |= (uint8_t)Flag;
153 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
155 void clearAsmPrinterFlag(CommentFlag Flag) {
156 AsmPrinterFlags &= ~Flag;
159 /// getFlags - Return the MI flags bitvector.
160 uint8_t getFlags() const {
164 /// getFlag - Return whether an MI flag is set.
165 bool getFlag(MIFlag Flag) const {
169 /// setFlag - Set a MI flag.
170 void setFlag(MIFlag Flag) {
171 Flags |= (uint8_t)Flag;
174 void setFlags(unsigned flags) {
178 /// isInsideBundle - Return true if MI is in a bundle (but not the first MI
181 /// A bundle looks like this before it's finalized:
193 /// In this case, the first MI starts a bundle but is not inside a bundle, the
194 /// next 2 MIs are considered "inside" the bundle.
196 /// After a bundle is finalized, it looks like this:
212 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
213 /// a bundle, but the next three MIs are.
214 bool isInsideBundle() const {
215 return getFlag(InsideBundle);
218 /// getDebugLoc - Returns the debug location id of this MachineInstr.
220 DebugLoc getDebugLoc() const { return debugLoc; }
222 /// emitError - Emit an error referring to the source location of this
223 /// instruction. This should only be used for inline assembly that is somehow
224 /// impossible to compile. Other errors should have been handled much
227 /// If this method returns, the caller should try to recover from the error.
229 void emitError(StringRef Msg) const;
231 /// getDesc - Returns the target instruction descriptor of this
233 const MCInstrDesc &getDesc() const { return *MCID; }
235 /// getOpcode - Returns the opcode of this MachineInstr.
237 int getOpcode() const { return MCID->Opcode; }
239 /// Access to explicit operands of the instruction.
241 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
243 const MachineOperand& getOperand(unsigned i) const {
244 assert(i < getNumOperands() && "getOperand() out of range!");
247 MachineOperand& getOperand(unsigned i) {
248 assert(i < getNumOperands() && "getOperand() out of range!");
252 /// getNumExplicitOperands - Returns the number of non-implicit operands.
254 unsigned getNumExplicitOperands() const;
256 /// iterator/begin/end - Iterate over all operands of a machine instruction.
257 typedef std::vector<MachineOperand>::iterator mop_iterator;
258 typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;
260 mop_iterator operands_begin() { return Operands.begin(); }
261 mop_iterator operands_end() { return Operands.end(); }
263 const_mop_iterator operands_begin() const { return Operands.begin(); }
264 const_mop_iterator operands_end() const { return Operands.end(); }
266 /// Access to memory operands of the instruction
267 mmo_iterator memoperands_begin() const { return MemRefs; }
268 mmo_iterator memoperands_end() const { return MemRefsEnd; }
269 bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
271 /// hasOneMemOperand - Return true if this instruction has exactly one
272 /// MachineMemOperand.
273 bool hasOneMemOperand() const {
274 return MemRefsEnd - MemRefs == 1;
277 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
278 /// queries but they are bundle aware.
281 IgnoreBundle, // Ignore bundles
282 AnyInBundle, // Return true if any instruction in bundle has property
283 AllInBundle // Return true if all instructions in bundle have property
286 /// hasProperty - Return true if the instruction (or in the case of a bundle,
287 /// the instructions inside the bundle) has the specified property.
288 /// The first argument is the property being queried.
289 /// The second argument indicates whether the query should look inside
290 /// instruction bundles.
291 /// If the third argument is true, than the query can return true when *any*
292 /// of the bundled instructions has the queried property. If it's false, then
293 /// this can return true iff *all* of the instructions have the property.
294 bool hasProperty(unsigned Flag, QueryType Type = AnyInBundle) const;
296 /// isVariadic - Return true if this instruction can have a variable number of
297 /// operands. In this case, the variable operands will be after the normal
298 /// operands but before the implicit definitions and uses (if any are
300 bool isVariadic(QueryType Type = IgnoreBundle) const {
301 return hasProperty(MCID::Variadic, Type);
304 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
305 /// ARM instructions which can set condition code if 's' bit is set.
306 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
307 return hasProperty(MCID::HasOptionalDef, Type);
310 /// isPseudo - Return true if this is a pseudo instruction that doesn't
311 /// correspond to a real machine instruction.
313 bool isPseudo(QueryType Type = IgnoreBundle) const {
314 return hasProperty(MCID::Pseudo, Type);
317 bool isReturn(QueryType Type = AnyInBundle) const {
318 return hasProperty(MCID::Return, Type);
321 bool isCall(QueryType Type = AnyInBundle) const {
322 return hasProperty(MCID::Call, Type);
325 /// isBarrier - Returns true if the specified instruction stops control flow
326 /// from executing the instruction immediately following it. Examples include
327 /// unconditional branches and return instructions.
328 bool isBarrier(QueryType Type = AnyInBundle) const {
329 return hasProperty(MCID::Barrier, Type);
332 /// isTerminator - Returns true if this instruction part of the terminator for
333 /// a basic block. Typically this is things like return and branch
336 /// Various passes use this to insert code into the bottom of a basic block,
337 /// but before control flow occurs.
338 bool isTerminator(QueryType Type = AnyInBundle) const {
339 return hasProperty(MCID::Terminator, Type);
342 /// isBranch - Returns true if this is a conditional, unconditional, or
343 /// indirect branch. Predicates below can be used to discriminate between
344 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
345 /// get more information.
346 bool isBranch(QueryType Type = AnyInBundle) const {
347 return hasProperty(MCID::Branch, Type);
350 /// isIndirectBranch - Return true if this is an indirect branch, such as a
351 /// branch through a register.
352 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
353 return hasProperty(MCID::IndirectBranch, Type);
356 /// isConditionalBranch - Return true if this is a branch which may fall
357 /// through to the next instruction or may transfer control flow to some other
358 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
359 /// information about this branch.
360 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
361 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
364 /// isUnconditionalBranch - Return true if this is a branch which always
365 /// transfers control flow to some other block. The
366 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
367 /// about this branch.
368 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
369 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
372 // isPredicable - Return true if this instruction has a predicate operand that
373 // controls execution. It may be set to 'always', or may be set to other
374 /// values. There are various methods in TargetInstrInfo that can be used to
375 /// control and modify the predicate in this instruction.
376 bool isPredicable(QueryType Type = AllInBundle) const {
377 // If it's a bundle than all bundled instructions must be predicable for this
379 return hasProperty(MCID::Predicable, Type);
382 /// isCompare - Return true if this instruction is a comparison.
383 bool isCompare(QueryType Type = IgnoreBundle) const {
384 return hasProperty(MCID::Compare, Type);
387 /// isMoveImmediate - Return true if this instruction is a move immediate
388 /// (including conditional moves) instruction.
389 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
390 return hasProperty(MCID::MoveImm, Type);
393 /// isBitcast - Return true if this instruction is a bitcast instruction.
395 bool isBitcast(QueryType Type = IgnoreBundle) const {
396 return hasProperty(MCID::Bitcast, Type);
399 /// isNotDuplicable - Return true if this instruction cannot be safely
400 /// duplicated. For example, if the instruction has a unique labels attached
401 /// to it, duplicating it would cause multiple definition errors.
402 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
403 return hasProperty(MCID::NotDuplicable, Type);
406 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
407 /// which must be filled by the code generator.
408 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
409 return hasProperty(MCID::DelaySlot, Type);
412 /// canFoldAsLoad - Return true for instructions that can be folded as
413 /// memory operands in other instructions. The most common use for this
414 /// is instructions that are simple loads from memory that don't modify
415 /// the loaded value in any way, but it can also be used for instructions
416 /// that can be expressed as constant-pool loads, such as V_SETALLONES
417 /// on x86, to allow them to be folded when it is beneficial.
418 /// This should only be set on instructions that return a value in their
419 /// only virtual register definition.
420 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
421 return hasProperty(MCID::FoldableAsLoad, Type);
424 //===--------------------------------------------------------------------===//
425 // Side Effect Analysis
426 //===--------------------------------------------------------------------===//
428 /// mayLoad - Return true if this instruction could possibly read memory.
429 /// Instructions with this flag set are not necessarily simple load
430 /// instructions, they may load a value and modify it, for example.
431 bool mayLoad(QueryType Type = AnyInBundle) const {
432 return hasProperty(MCID::MayLoad, Type);
436 /// mayStore - Return true if this instruction could possibly modify memory.
437 /// Instructions with this flag set are not necessarily simple store
438 /// instructions, they may store a modified value based on their operands, or
439 /// may not actually modify anything, for example.
440 bool mayStore(QueryType Type = AnyInBundle) const {
441 return hasProperty(MCID::MayStore, Type);
444 //===--------------------------------------------------------------------===//
445 // Flags that indicate whether an instruction can be modified by a method.
446 //===--------------------------------------------------------------------===//
448 /// isCommutable - Return true if this may be a 2- or 3-address
449 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
450 /// result if Y and Z are exchanged. If this flag is set, then the
451 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
454 /// Note that this flag may be set on instructions that are only commutable
455 /// sometimes. In these cases, the call to commuteInstruction will fail.
456 /// Also note that some instructions require non-trivial modification to
458 bool isCommutable(QueryType Type = IgnoreBundle) const {
459 return hasProperty(MCID::Commutable, Type);
462 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
463 /// which can be changed into a 3-address instruction if needed. Doing this
464 /// transformation can be profitable in the register allocator, because it
465 /// means that the instruction can use a 2-address form if possible, but
466 /// degrade into a less efficient form if the source and dest register cannot
467 /// be assigned to the same register. For example, this allows the x86
468 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
469 /// is the same speed as the shift but has bigger code size.
471 /// If this returns true, then the target must implement the
472 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
473 /// is allowed to fail if the transformation isn't valid for this specific
474 /// instruction (e.g. shl reg, 4 on x86).
476 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
477 return hasProperty(MCID::ConvertibleTo3Addr, Type);
480 /// usesCustomInsertionHook - Return true if this instruction requires
481 /// custom insertion support when the DAG scheduler is inserting it into a
482 /// machine basic block. If this is true for the instruction, it basically
483 /// means that it is a pseudo instruction used at SelectionDAG time that is
484 /// expanded out into magic code by the target when MachineInstrs are formed.
486 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
487 /// is used to insert this into the MachineBasicBlock.
488 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
489 return hasProperty(MCID::UsesCustomInserter, Type);
492 /// hasPostISelHook - Return true if this instruction requires *adjustment*
493 /// after instruction selection by calling a target hook. For example, this
494 /// can be used to fill in ARM 's' optional operand depending on whether
495 /// the conditional flag register is used.
496 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
497 return hasProperty(MCID::HasPostISelHook, Type);
500 /// isRematerializable - Returns true if this instruction is a candidate for
501 /// remat. This flag is deprecated, please don't use it anymore. If this
502 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
503 /// verify the instruction is really rematable.
504 bool isRematerializable(QueryType Type = AllInBundle) const {
505 // It's only possible to re-mat a bundle if all bundled instructions are
506 // re-materializable.
507 return hasProperty(MCID::Rematerializable, Type);
510 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
511 /// less) than a move instruction. This is useful during certain types of
512 /// optimizations (e.g., remat during two-address conversion or machine licm)
513 /// where we would like to remat or hoist the instruction, but not if it costs
514 /// more than moving the instruction into the appropriate register. Note, we
515 /// are not marking copies from and to the same register class with this flag.
516 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
517 // Only returns true for a bundle if all bundled instructions are cheap.
518 // FIXME: This probably requires a target hook.
519 return hasProperty(MCID::CheapAsAMove, Type);
522 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
523 /// have special register allocation requirements that are not captured by the
524 /// operand register classes. e.g. ARM::STRD's two source registers must be an
525 /// even / odd pair, ARM::STM registers have to be in ascending order.
526 /// Post-register allocation passes should not attempt to change allocations
527 /// for sources of instructions with this flag.
528 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
529 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
532 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
533 /// have special register allocation requirements that are not captured by the
534 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
535 /// even / odd pair, ARM::LDM registers have to be in ascending order.
536 /// Post-register allocation passes should not attempt to change allocations
537 /// for definitions of instructions with this flag.
538 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
539 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
544 CheckDefs, // Check all operands for equality
545 CheckKillDead, // Check all operands including kill / dead markers
546 IgnoreDefs, // Ignore all definitions
547 IgnoreVRegDefs // Ignore virtual register definitions
550 /// isIdenticalTo - Return true if this instruction is identical to (same
551 /// opcode and same operands as) the specified instruction.
552 bool isIdenticalTo(const MachineInstr *Other,
553 MICheckType Check = CheckDefs) const;
555 /// removeFromParent - This method unlinks 'this' from the containing basic
556 /// block, and returns it, but does not delete it.
557 MachineInstr *removeFromParent();
559 /// eraseFromParent - This method unlinks 'this' from the containing basic
560 /// block and deletes it.
561 void eraseFromParent();
563 /// isLabel - Returns true if the MachineInstr represents a label.
565 bool isLabel() const {
566 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
567 getOpcode() == TargetOpcode::EH_LABEL ||
568 getOpcode() == TargetOpcode::GC_LABEL;
571 bool isPrologLabel() const {
572 return getOpcode() == TargetOpcode::PROLOG_LABEL;
574 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
575 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
576 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
578 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
579 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
580 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
581 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
582 bool isStackAligningInlineAsm() const;
583 bool isInsertSubreg() const {
584 return getOpcode() == TargetOpcode::INSERT_SUBREG;
586 bool isSubregToReg() const {
587 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
589 bool isRegSequence() const {
590 return getOpcode() == TargetOpcode::REG_SEQUENCE;
592 bool isCopy() const {
593 return getOpcode() == TargetOpcode::COPY;
595 bool isFullCopy() const {
596 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
599 /// isCopyLike - Return true if the instruction behaves like a copy.
600 /// This does not include native copy instructions.
601 bool isCopyLike() const {
602 return isCopy() || isSubregToReg();
605 /// isIdentityCopy - Return true is the instruction is an identity copy.
606 bool isIdentityCopy() const {
607 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
608 getOperand(0).getSubReg() == getOperand(1).getSubReg();
611 /// readsRegister - Return true if the MachineInstr reads the specified
612 /// register. If TargetRegisterInfo is passed, then it also checks if there
613 /// is a read of a super-register.
614 /// This does not count partial redefines of virtual registers as reads:
616 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
617 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
620 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
621 /// virtual register. Take into account that a partial define is a
622 /// read-modify-write operation.
623 bool readsVirtualRegister(unsigned Reg) const {
624 return readsWritesVirtualRegister(Reg).first;
627 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
628 /// indicating if this instruction reads or writes Reg. This also considers
630 /// If Ops is not null, all operand indices for Reg are added.
631 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
632 SmallVectorImpl<unsigned> *Ops = 0) const;
634 /// killsRegister - Return true if the MachineInstr kills the specified
635 /// register. If TargetRegisterInfo is passed, then it also checks if there is
636 /// a kill of a super-register.
637 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
638 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
641 /// definesRegister - Return true if the MachineInstr fully defines the
642 /// specified register. If TargetRegisterInfo is passed, then it also checks
643 /// if there is a def of a super-register.
644 /// NOTE: It's ignoring subreg indices on virtual registers.
645 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
646 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
649 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
650 /// or partially define) the specified register.
651 /// NOTE: It's ignoring subreg indices on virtual registers.
652 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
653 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
656 /// registerDefIsDead - Returns true if the register is dead in this machine
657 /// instruction. If TargetRegisterInfo is passed, then it also checks
658 /// if there is a dead def of a super-register.
659 bool registerDefIsDead(unsigned Reg,
660 const TargetRegisterInfo *TRI = NULL) const {
661 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
664 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
665 /// the specific register or -1 if it is not found. It further tightens
666 /// the search criteria to a use that kills the register if isKill is true.
667 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
668 const TargetRegisterInfo *TRI = NULL) const;
670 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
671 /// a pointer to the MachineOperand rather than an index.
672 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
673 const TargetRegisterInfo *TRI = NULL) {
674 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
675 return (Idx == -1) ? NULL : &getOperand(Idx);
678 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
679 /// the specified register or -1 if it is not found. If isDead is true, defs
680 /// that are not dead are skipped. If Overlap is true, then it also looks for
681 /// defs that merely overlap the specified register. If TargetRegisterInfo is
682 /// non-null, then it also checks if there is a def of a super-register.
683 int findRegisterDefOperandIdx(unsigned Reg,
684 bool isDead = false, bool Overlap = false,
685 const TargetRegisterInfo *TRI = NULL) const;
687 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
688 /// a pointer to the MachineOperand rather than an index.
689 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
690 const TargetRegisterInfo *TRI = NULL) {
691 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
692 return (Idx == -1) ? NULL : &getOperand(Idx);
695 /// findFirstPredOperandIdx() - Find the index of the first operand in the
696 /// operand list that is used to represent the predicate. It returns -1 if
698 int findFirstPredOperandIdx() const;
700 /// findInlineAsmFlagIdx() - Find the index of the flag word operand that
701 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
702 /// getOperand(OpIdx) does not belong to an inline asm operand group.
704 /// If GroupNo is not NULL, it will receive the number of the operand group
705 /// containing OpIdx.
707 /// The flag operand is an immediate that can be decoded with methods like
708 /// InlineAsm::hasRegClassConstraint().
710 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const;
712 /// getRegClassConstraint - Compute the static register class constraint for
713 /// operand OpIdx. For normal instructions, this is derived from the
714 /// MCInstrDesc. For inline assembly it is derived from the flag words.
716 /// Returns NULL if the static register classs constraint cannot be
719 const TargetRegisterClass*
720 getRegClassConstraint(unsigned OpIdx,
721 const TargetInstrInfo *TII,
722 const TargetRegisterInfo *TRI) const;
724 /// isRegTiedToUseOperand - Given the index of a register def operand,
725 /// check if the register def is tied to a source operand, due to either
726 /// two-address elimination or inline assembly constraints. Returns the
727 /// first tied use operand index by reference is UseOpIdx is not null.
728 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
730 /// isRegTiedToDefOperand - Return true if the use operand of the specified
731 /// index is tied to an def operand. It also returns the def operand index by
732 /// reference if DefOpIdx is not null.
733 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
735 /// clearKillInfo - Clears kill flags on all operands.
737 void clearKillInfo();
739 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
741 void copyKillDeadInfo(const MachineInstr *MI);
743 /// copyPredicates - Copies predicate operand(s) from MI.
744 void copyPredicates(const MachineInstr *MI);
746 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
747 /// properly composing subreg indices where necessary.
748 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
749 const TargetRegisterInfo &RegInfo);
751 /// addRegisterKilled - We have determined MI kills a register. Look for the
752 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
753 /// add a implicit operand if it's not found. Returns true if the operand
754 /// exists / is added.
755 bool addRegisterKilled(unsigned IncomingReg,
756 const TargetRegisterInfo *RegInfo,
757 bool AddIfNotFound = false);
759 /// addRegisterDead - We have determined MI defined a register without a use.
760 /// Look for the operand that defines it and mark it as IsDead. If
761 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
762 /// true if the operand exists / is added.
763 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
764 bool AddIfNotFound = false);
766 /// addRegisterDefined - We have determined MI defines a register. Make sure
767 /// there is an operand defining Reg.
768 void addRegisterDefined(unsigned IncomingReg,
769 const TargetRegisterInfo *RegInfo = 0);
771 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
772 /// dead except those in the UsedRegs list.
773 void setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
774 const TargetRegisterInfo &TRI);
776 /// isSafeToMove - Return true if it is safe to move this instruction. If
777 /// SawStore is set to true, it means that there is a store (or call) between
778 /// the instruction's location and its intended destination.
779 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
780 bool &SawStore) const;
782 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
783 /// instruction which defined the specified register instead of copying it.
784 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
785 unsigned DstReg) const;
787 /// hasVolatileMemoryRef - Return true if this instruction may have a
788 /// volatile memory reference, or if the information describing the
789 /// memory reference is not available. Return false if it is known to
790 /// have no volatile memory references.
791 bool hasVolatileMemoryRef() const;
793 /// isInvariantLoad - Return true if this instruction is loading from a
794 /// location whose value is invariant across the function. For example,
795 /// loading a value from the constant pool or from the argument area of
796 /// a function if it does not change. This should only return true of *all*
797 /// loads the instruction does are invariant (if it does multiple loads).
798 bool isInvariantLoad(AliasAnalysis *AA) const;
800 /// isConstantValuePHI - If the specified instruction is a PHI that always
801 /// merges together the same virtual register, return the register, otherwise
803 unsigned isConstantValuePHI() const;
805 /// hasUnmodeledSideEffects - Return true if this instruction has side
806 /// effects that are not modeled by mayLoad / mayStore, etc.
807 /// For all instructions, the property is encoded in MCInstrDesc::Flags
808 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
809 /// INLINEASM instruction, in which case the side effect property is encoded
810 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
812 bool hasUnmodeledSideEffects() const;
814 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
816 bool allDefsAreDead() const;
818 /// copyImplicitOps - Copy implicit register operands from specified
819 /// instruction to this instruction.
820 void copyImplicitOps(const MachineInstr *MI);
825 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
828 //===--------------------------------------------------------------------===//
829 // Accessors used to build up machine instructions.
831 /// addOperand - Add the specified operand to the instruction. If it is an
832 /// implicit operand, it is added to the end of the operand list. If it is
833 /// an explicit operand it is added at the end of the explicit operand list
834 /// (before the first implicit operand).
835 void addOperand(const MachineOperand &Op);
837 /// setDesc - Replace the instruction descriptor (thus opcode) of
838 /// the current instruction with a new one.
840 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
842 /// setDebugLoc - Replace current source information with new such.
843 /// Avoid using this, the constructor argument is preferable.
845 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
847 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
848 /// fewer operand than it started with.
850 void RemoveOperand(unsigned i);
852 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
853 /// This function should be used only occasionally. The setMemRefs function
854 /// is the primary method for setting up a MachineInstr's MemRefs list.
855 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
857 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
858 /// list. This does not transfer ownership.
859 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
860 MemRefs = NewMemRefs;
861 MemRefsEnd = NewMemRefsEnd;
865 /// getRegInfo - If this instruction is embedded into a MachineFunction,
866 /// return the MachineRegisterInfo object for the current function, otherwise
868 MachineRegisterInfo *getRegInfo();
870 /// addImplicitDefUseOperands - Add all implicit def and use operands to
871 /// this instruction.
872 void addImplicitDefUseOperands();
874 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
875 /// this instruction from their respective use lists. This requires that the
876 /// operands already be on their use lists.
877 void RemoveRegOperandsFromUseLists();
879 /// AddRegOperandsToUseLists - Add all of the register operands in
880 /// this instruction from their respective use lists. This requires that the
881 /// operands not be on their use lists yet.
882 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
885 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
886 /// MachineInstr* by *value* of the instruction rather than by pointer value.
887 /// The hashing and equality testing functions ignore definitions so this is
888 /// useful for CSE, etc.
889 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
890 static inline MachineInstr *getEmptyKey() {
894 static inline MachineInstr *getTombstoneKey() {
895 return reinterpret_cast<MachineInstr*>(-1);
898 static unsigned getHashValue(const MachineInstr* const &MI);
900 static bool isEqual(const MachineInstr* const &LHS,
901 const MachineInstr* const &RHS) {
902 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
903 LHS == getEmptyKey() || LHS == getTombstoneKey())
905 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
909 //===----------------------------------------------------------------------===//
912 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
917 } // End llvm namespace