1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/Target/TargetInstrDesc.h"
21 #include "llvm/Target/TargetOpcodes.h"
22 #include "llvm/ADT/ilist.h"
23 #include "llvm/ADT/ilist_node.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/DenseMapInfo.h"
26 #include "llvm/Support/DebugLoc.h"
31 template <typename T> class SmallVectorImpl;
33 class TargetInstrDesc;
34 class TargetInstrInfo;
35 class TargetRegisterInfo;
36 class MachineFunction;
37 class MachineMemOperand;
39 //===----------------------------------------------------------------------===//
40 /// MachineInstr - Representation of each machine instruction.
42 class MachineInstr : public ilist_node<MachineInstr> {
44 typedef MachineMemOperand **mmo_iterator;
46 /// Flags to specify different kinds of comments to output in
47 /// assembly code. These flags carry semantic information not
48 /// otherwise easily derivable from the IR text.
55 const TargetInstrDesc *TID; // Instruction descriptor.
56 unsigned short NumImplicitOps; // Number of implicit operands (which
57 // are determined at construction time).
59 unsigned short AsmPrinterFlags; // Various bits of information used by
60 // the AsmPrinter to emit helpful
61 // comments. This is *not* semantic
62 // information. Do not use this for
63 // anything other than to convey comment
64 // information to AsmPrinter.
66 std::vector<MachineOperand> Operands; // the operands
67 mmo_iterator MemRefs; // information on memory references
68 mmo_iterator MemRefsEnd;
69 MachineBasicBlock *Parent; // Pointer to the owning basic block.
70 DebugLoc debugLoc; // Source line information.
72 // OperandComplete - Return true if it's illegal to add a new operand
73 bool OperandsComplete() const;
75 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
76 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
78 // Intrusive list support
79 friend struct ilist_traits<MachineInstr>;
80 friend struct ilist_traits<MachineBasicBlock>;
81 void setParent(MachineBasicBlock *P) { Parent = P; }
83 /// MachineInstr ctor - This constructor creates a copy of the given
84 /// MachineInstr in the given MachineFunction.
85 MachineInstr(MachineFunction &, const MachineInstr &);
87 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
88 /// TID NULL and no operands.
91 // The next two constructors have DebugLoc and non-DebugLoc versions;
92 // over time, the non-DebugLoc versions should be phased out and eventually
95 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
96 /// implicit operands. It reserves space for the number of operands specified
97 /// by the TargetInstrDesc. The version with a DebugLoc should be preferred.
98 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
100 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
101 /// the MachineInstr is created and added to the end of the specified basic
102 /// block. The version with a DebugLoc should be preferred.
103 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
105 /// MachineInstr ctor - This constructor create a MachineInstr and add the
106 /// implicit operands. It reserves space for number of operands specified by
107 /// TargetInstrDesc. An explicit DebugLoc is supplied.
108 explicit MachineInstr(const TargetInstrDesc &TID, const DebugLoc dl,
111 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
112 /// the MachineInstr is created and added to the end of the specified basic
114 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
115 const TargetInstrDesc &TID);
119 // MachineInstrs are pool-allocated and owned by MachineFunction.
120 friend class MachineFunction;
123 const MachineBasicBlock* getParent() const { return Parent; }
124 MachineBasicBlock* getParent() { return Parent; }
126 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
128 unsigned short getAsmPrinterFlags() const { return AsmPrinterFlags; }
130 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
132 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
134 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
136 bool getAsmPrinterFlag(CommentFlag Flag) const {
137 return AsmPrinterFlags & Flag;
140 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
142 void setAsmPrinterFlag(CommentFlag Flag) {
143 AsmPrinterFlags |= (unsigned short)Flag;
146 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
148 void clearAsmPrinterFlag(CommentFlag Flag) {
149 AsmPrinterFlags &= ~Flag;
152 /// getDebugLoc - Returns the debug location id of this MachineInstr.
154 DebugLoc getDebugLoc() const { return debugLoc; }
156 /// getDesc - Returns the target instruction descriptor of this
158 const TargetInstrDesc &getDesc() const { return *TID; }
160 /// getOpcode - Returns the opcode of this MachineInstr.
162 int getOpcode() const { return TID->Opcode; }
164 /// Access to explicit operands of the instruction.
166 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
168 const MachineOperand& getOperand(unsigned i) const {
169 assert(i < getNumOperands() && "getOperand() out of range!");
172 MachineOperand& getOperand(unsigned i) {
173 assert(i < getNumOperands() && "getOperand() out of range!");
177 /// getNumExplicitOperands - Returns the number of non-implicit operands.
179 unsigned getNumExplicitOperands() const;
181 /// iterator/begin/end - Iterate over all operands of a machine instruction.
182 typedef std::vector<MachineOperand>::iterator mop_iterator;
183 typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;
185 mop_iterator operands_begin() { return Operands.begin(); }
186 mop_iterator operands_end() { return Operands.end(); }
188 const_mop_iterator operands_begin() const { return Operands.begin(); }
189 const_mop_iterator operands_end() const { return Operands.end(); }
191 /// Access to memory operands of the instruction
192 mmo_iterator memoperands_begin() const { return MemRefs; }
193 mmo_iterator memoperands_end() const { return MemRefsEnd; }
194 bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
196 /// hasOneMemOperand - Return true if this instruction has exactly one
197 /// MachineMemOperand.
198 bool hasOneMemOperand() const {
199 return MemRefsEnd - MemRefs == 1;
203 CheckDefs, // Check all operands for equality
204 IgnoreDefs, // Ignore all definitions
205 IgnoreVRegDefs // Ignore virtual register definitions
208 /// isIdenticalTo - Return true if this instruction is identical to (same
209 /// opcode and same operands as) the specified instruction.
210 bool isIdenticalTo(const MachineInstr *Other,
211 MICheckType Check = CheckDefs) const;
213 /// removeFromParent - This method unlinks 'this' from the containing basic
214 /// block, and returns it, but does not delete it.
215 MachineInstr *removeFromParent();
217 /// eraseFromParent - This method unlinks 'this' from the containing basic
218 /// block and deletes it.
219 void eraseFromParent();
221 /// isLabel - Returns true if the MachineInstr represents a label.
223 bool isLabel() const {
224 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
225 getOpcode() == TargetOpcode::EH_LABEL ||
226 getOpcode() == TargetOpcode::GC_LABEL;
229 bool isPrologLabel() const {
230 return getOpcode() == TargetOpcode::PROLOG_LABEL;
232 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
233 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
234 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
236 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
237 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
238 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
239 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
240 bool isStackAligningInlineAsm() const;
241 bool isInsertSubreg() const {
242 return getOpcode() == TargetOpcode::INSERT_SUBREG;
244 bool isSubregToReg() const {
245 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
247 bool isRegSequence() const {
248 return getOpcode() == TargetOpcode::REG_SEQUENCE;
250 bool isCopy() const {
251 return getOpcode() == TargetOpcode::COPY;
254 /// isCopyLike - Return true if the instruction behaves like a copy.
255 /// This does not include native copy instructions.
256 bool isCopyLike() const {
257 return isCopy() || isSubregToReg();
260 /// isIdentityCopy - Return true is the instruction is an identity copy.
261 bool isIdentityCopy() const {
262 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
263 getOperand(0).getSubReg() == getOperand(1).getSubReg();
266 /// readsRegister - Return true if the MachineInstr reads the specified
267 /// register. If TargetRegisterInfo is passed, then it also checks if there
268 /// is a read of a super-register.
269 /// This does not count partial redefines of virtual registers as reads:
271 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
272 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
275 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
276 /// virtual register. Take into account that a partial define is a
277 /// read-modify-write operation.
278 bool readsVirtualRegister(unsigned Reg) const {
279 return readsWritesVirtualRegister(Reg).first;
282 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
283 /// indicating if this instruction reads or writes Reg. This also considers
285 /// If Ops is not null, all operand indices for Reg are added.
286 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
287 SmallVectorImpl<unsigned> *Ops = 0) const;
289 /// killsRegister - Return true if the MachineInstr kills the specified
290 /// register. If TargetRegisterInfo is passed, then it also checks if there is
291 /// a kill of a super-register.
292 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
293 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
296 /// definesRegister - Return true if the MachineInstr fully defines the
297 /// specified register. If TargetRegisterInfo is passed, then it also checks
298 /// if there is a def of a super-register.
299 /// NOTE: It's ignoring subreg indices on virtual registers.
300 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
301 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
304 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
305 /// or partially define) the specified register.
306 /// NOTE: It's ignoring subreg indices on virtual registers.
307 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
308 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
311 /// registerDefIsDead - Returns true if the register is dead in this machine
312 /// instruction. If TargetRegisterInfo is passed, then it also checks
313 /// if there is a dead def of a super-register.
314 bool registerDefIsDead(unsigned Reg,
315 const TargetRegisterInfo *TRI = NULL) const {
316 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
319 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
320 /// the specific register or -1 if it is not found. It further tightens
321 /// the search criteria to a use that kills the register if isKill is true.
322 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
323 const TargetRegisterInfo *TRI = NULL) const;
325 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
326 /// a pointer to the MachineOperand rather than an index.
327 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
328 const TargetRegisterInfo *TRI = NULL) {
329 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
330 return (Idx == -1) ? NULL : &getOperand(Idx);
333 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
334 /// the specified register or -1 if it is not found. If isDead is true, defs
335 /// that are not dead are skipped. If Overlap is true, then it also looks for
336 /// defs that merely overlap the specified register. If TargetRegisterInfo is
337 /// non-null, then it also checks if there is a def of a super-register.
338 int findRegisterDefOperandIdx(unsigned Reg,
339 bool isDead = false, bool Overlap = false,
340 const TargetRegisterInfo *TRI = NULL) const;
342 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
343 /// a pointer to the MachineOperand rather than an index.
344 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
345 const TargetRegisterInfo *TRI = NULL) {
346 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
347 return (Idx == -1) ? NULL : &getOperand(Idx);
350 /// findFirstPredOperandIdx() - Find the index of the first operand in the
351 /// operand list that is used to represent the predicate. It returns -1 if
353 int findFirstPredOperandIdx() const;
355 /// isRegTiedToUseOperand - Given the index of a register def operand,
356 /// check if the register def is tied to a source operand, due to either
357 /// two-address elimination or inline assembly constraints. Returns the
358 /// first tied use operand index by reference is UseOpIdx is not null.
359 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
361 /// isRegTiedToDefOperand - Return true if the use operand of the specified
362 /// index is tied to an def operand. It also returns the def operand index by
363 /// reference if DefOpIdx is not null.
364 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
366 /// clearKillInfo - Clears kill flags on all operands.
368 void clearKillInfo();
370 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
372 void copyKillDeadInfo(const MachineInstr *MI);
374 /// copyPredicates - Copies predicate operand(s) from MI.
375 void copyPredicates(const MachineInstr *MI);
377 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
378 /// properly composing subreg indices where necessary.
379 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
380 const TargetRegisterInfo &RegInfo);
382 /// addRegisterKilled - We have determined MI kills a register. Look for the
383 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
384 /// add a implicit operand if it's not found. Returns true if the operand
385 /// exists / is added.
386 bool addRegisterKilled(unsigned IncomingReg,
387 const TargetRegisterInfo *RegInfo,
388 bool AddIfNotFound = false);
390 /// addRegisterDead - We have determined MI defined a register without a use.
391 /// Look for the operand that defines it and mark it as IsDead. If
392 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
393 /// true if the operand exists / is added.
394 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
395 bool AddIfNotFound = false);
397 /// addRegisterDefined - We have determined MI defines a register. Make sure
398 /// there is an operand defining Reg.
399 void addRegisterDefined(unsigned IncomingReg,
400 const TargetRegisterInfo *RegInfo = 0);
402 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as dead
403 /// except those in the UsedRegs list.
404 void setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
405 const TargetRegisterInfo &TRI);
407 /// isSafeToMove - Return true if it is safe to move this instruction. If
408 /// SawStore is set to true, it means that there is a store (or call) between
409 /// the instruction's location and its intended destination.
410 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
411 bool &SawStore) const;
413 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
414 /// instruction which defined the specified register instead of copying it.
415 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
416 unsigned DstReg) const;
418 /// hasVolatileMemoryRef - Return true if this instruction may have a
419 /// volatile memory reference, or if the information describing the
420 /// memory reference is not available. Return false if it is known to
421 /// have no volatile memory references.
422 bool hasVolatileMemoryRef() const;
424 /// isInvariantLoad - Return true if this instruction is loading from a
425 /// location whose value is invariant across the function. For example,
426 /// loading a value from the constant pool or from the argument area of
427 /// a function if it does not change. This should only return true of *all*
428 /// loads the instruction does are invariant (if it does multiple loads).
429 bool isInvariantLoad(AliasAnalysis *AA) const;
431 /// isConstantValuePHI - If the specified instruction is a PHI that always
432 /// merges together the same virtual register, return the register, otherwise
434 unsigned isConstantValuePHI() const;
436 /// hasUnmodeledSideEffects - Return true if this instruction has side
437 /// effects that are not modeled by mayLoad / mayStore, etc.
438 /// For all instructions, the property is encoded in TargetInstrDesc::Flags
439 /// (see TargetInstrDesc::hasUnmodeledSideEffects(). The only exception is
440 /// INLINEASM instruction, in which case the side effect property is encoded
441 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
443 bool hasUnmodeledSideEffects() const;
445 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
447 bool allDefsAreDead() const;
449 /// copyImplicitOps - Copy implicit register operands from specified
450 /// instruction to this instruction.
451 void copyImplicitOps(const MachineInstr *MI);
456 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
459 //===--------------------------------------------------------------------===//
460 // Accessors used to build up machine instructions.
462 /// addOperand - Add the specified operand to the instruction. If it is an
463 /// implicit operand, it is added to the end of the operand list. If it is
464 /// an explicit operand it is added at the end of the explicit operand list
465 /// (before the first implicit operand).
466 void addOperand(const MachineOperand &Op);
468 /// setDesc - Replace the instruction descriptor (thus opcode) of
469 /// the current instruction with a new one.
471 void setDesc(const TargetInstrDesc &tid) { TID = &tid; }
473 /// setDebugLoc - Replace current source information with new such.
474 /// Avoid using this, the constructor argument is preferable.
476 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
478 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
479 /// fewer operand than it started with.
481 void RemoveOperand(unsigned i);
483 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
484 /// This function should be used only occasionally. The setMemRefs function
485 /// is the primary method for setting up a MachineInstr's MemRefs list.
486 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
488 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
489 /// list. This does not transfer ownership.
490 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
491 MemRefs = NewMemRefs;
492 MemRefsEnd = NewMemRefsEnd;
496 /// getRegInfo - If this instruction is embedded into a MachineFunction,
497 /// return the MachineRegisterInfo object for the current function, otherwise
499 MachineRegisterInfo *getRegInfo();
501 /// addImplicitDefUseOperands - Add all implicit def and use operands to
502 /// this instruction.
503 void addImplicitDefUseOperands();
505 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
506 /// this instruction from their respective use lists. This requires that the
507 /// operands already be on their use lists.
508 void RemoveRegOperandsFromUseLists();
510 /// AddRegOperandsToUseLists - Add all of the register operands in
511 /// this instruction from their respective use lists. This requires that the
512 /// operands not be on their use lists yet.
513 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
516 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
517 /// MachineInstr* by *value* of the instruction rather than by pointer value.
518 /// The hashing and equality testing functions ignore definitions so this is
519 /// useful for CSE, etc.
520 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
521 static inline MachineInstr *getEmptyKey() {
525 static inline MachineInstr *getTombstoneKey() {
526 return reinterpret_cast<MachineInstr*>(-1);
529 static unsigned getHashValue(const MachineInstr* const &MI);
531 static bool isEqual(const MachineInstr* const &LHS,
532 const MachineInstr* const &RHS) {
533 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
534 LHS == getEmptyKey() || LHS == getTombstoneKey())
536 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
540 //===----------------------------------------------------------------------===//
543 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
548 } // End llvm namespace