1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/ADT/ilist.h"
20 #include "llvm/ADT/ilist_node.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineOperand.h"
23 #include "llvm/Target/TargetInstrDesc.h"
24 #include "llvm/Target/TargetOpcodes.h"
25 #include "llvm/Support/DebugLoc.h"
31 class TargetInstrDesc;
32 class TargetInstrInfo;
33 class TargetRegisterInfo;
34 class MachineFunction;
35 class MachineMemOperand;
37 //===----------------------------------------------------------------------===//
38 /// MachineInstr - Representation of each machine instruction.
40 class MachineInstr : public ilist_node<MachineInstr> {
42 typedef MachineMemOperand **mmo_iterator;
44 /// Flags to specify different kinds of comments to output in
45 /// assembly code. These flags carry semantic information not
46 /// otherwise easily derivable from the IR text.
53 const TargetInstrDesc *TID; // Instruction descriptor.
54 unsigned short NumImplicitOps; // Number of implicit operands (which
55 // are determined at construction time).
57 unsigned short AsmPrinterFlags; // Various bits of information used by
58 // the AsmPrinter to emit helpful
59 // comments. This is *not* semantic
60 // information. Do not use this for
61 // anything other than to convey comment
62 // information to AsmPrinter.
64 std::vector<MachineOperand> Operands; // the operands
65 mmo_iterator MemRefs; // information on memory references
66 mmo_iterator MemRefsEnd;
67 MachineBasicBlock *Parent; // Pointer to the owning basic block.
68 DebugLoc debugLoc; // Source line information.
70 // OperandComplete - Return true if it's illegal to add a new operand
71 bool OperandsComplete() const;
73 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
74 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
76 // Intrusive list support
77 friend struct ilist_traits<MachineInstr>;
78 friend struct ilist_traits<MachineBasicBlock>;
79 void setParent(MachineBasicBlock *P) { Parent = P; }
81 /// MachineInstr ctor - This constructor creates a copy of the given
82 /// MachineInstr in the given MachineFunction.
83 MachineInstr(MachineFunction &, const MachineInstr &);
85 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
86 /// TID NULL and no operands.
89 // The next two constructors have DebugLoc and non-DebugLoc versions;
90 // over time, the non-DebugLoc versions should be phased out and eventually
93 /// MachineInstr ctor - This constructor create a MachineInstr and add the
94 /// implicit operands. It reserves space for number of operands specified by
95 /// TargetInstrDesc. The version with a DebugLoc should be preferred.
96 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
98 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
99 /// the MachineInstr is created and added to the end of the specified basic
100 /// block. The version with a DebugLoc should be preferred.
102 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
104 /// MachineInstr ctor - This constructor create a MachineInstr and add the
105 /// implicit operands. It reserves space for number of operands specified by
106 /// TargetInstrDesc. An explicit DebugLoc is supplied.
107 explicit MachineInstr(const TargetInstrDesc &TID, const DebugLoc dl,
110 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
111 /// the MachineInstr is created and added to the end of the specified basic
114 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
115 const TargetInstrDesc &TID);
119 // MachineInstrs are pool-allocated and owned by MachineFunction.
120 friend class MachineFunction;
123 const MachineBasicBlock* getParent() const { return Parent; }
124 MachineBasicBlock* getParent() { return Parent; }
126 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
128 unsigned short getAsmPrinterFlags() const { return AsmPrinterFlags; }
130 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
132 bool getAsmPrinterFlag(CommentFlag Flag) const {
133 return AsmPrinterFlags & Flag;
136 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
138 void setAsmPrinterFlag(CommentFlag Flag) {
139 AsmPrinterFlags |= (unsigned short)Flag;
142 /// getDebugLoc - Returns the debug location id of this MachineInstr.
144 DebugLoc getDebugLoc() const { return debugLoc; }
146 /// getDesc - Returns the target instruction descriptor of this
148 const TargetInstrDesc &getDesc() const { return *TID; }
150 /// getOpcode - Returns the opcode of this MachineInstr.
152 int getOpcode() const { return TID->Opcode; }
154 /// Access to explicit operands of the instruction.
156 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
158 const MachineOperand& getOperand(unsigned i) const {
159 assert(i < getNumOperands() && "getOperand() out of range!");
162 MachineOperand& getOperand(unsigned i) {
163 assert(i < getNumOperands() && "getOperand() out of range!");
167 /// getNumExplicitOperands - Returns the number of non-implicit operands.
169 unsigned getNumExplicitOperands() const;
171 /// Access to memory operands of the instruction
172 mmo_iterator memoperands_begin() const { return MemRefs; }
173 mmo_iterator memoperands_end() const { return MemRefsEnd; }
174 bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
176 /// hasOneMemOperand - Return true if this instruction has exactly one
177 /// MachineMemOperand.
178 bool hasOneMemOperand() const {
179 return MemRefsEnd - MemRefs == 1;
183 CheckDefs, // Check all operands for equality
184 IgnoreDefs, // Ignore all definitions
185 IgnoreVRegDefs // Ignore virtual register definitions
188 /// isIdenticalTo - Return true if this instruction is identical to (same
189 /// opcode and same operands as) the specified instruction.
190 bool isIdenticalTo(const MachineInstr *Other,
191 MICheckType Check = CheckDefs) const;
193 /// removeFromParent - This method unlinks 'this' from the containing basic
194 /// block, and returns it, but does not delete it.
195 MachineInstr *removeFromParent();
197 /// eraseFromParent - This method unlinks 'this' from the containing basic
198 /// block and deletes it.
199 void eraseFromParent();
201 /// isLabel - Returns true if the MachineInstr represents a label.
203 bool isLabel() const {
204 return getOpcode() == TargetOpcode::DBG_LABEL ||
205 getOpcode() == TargetOpcode::EH_LABEL ||
206 getOpcode() == TargetOpcode::GC_LABEL;
209 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
210 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
211 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
212 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
214 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
215 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
216 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
217 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
218 bool isExtractSubreg() const {
219 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
221 bool isInsertSubreg() const {
222 return getOpcode() == TargetOpcode::INSERT_SUBREG;
224 bool isSubregToReg() const {
225 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
228 /// readsRegister - Return true if the MachineInstr reads the specified
229 /// register. If TargetRegisterInfo is passed, then it also checks if there
230 /// is a read of a super-register.
231 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
232 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
235 /// killsRegister - Return true if the MachineInstr kills the specified
236 /// register. If TargetRegisterInfo is passed, then it also checks if there is
237 /// a kill of a super-register.
238 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
239 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
242 /// modifiesRegister - Return true if the MachineInstr modifies the
243 /// specified register. If TargetRegisterInfo is passed, then it also checks
244 /// if there is a def of a super-register.
245 bool modifiesRegister(unsigned Reg,
246 const TargetRegisterInfo *TRI = NULL) const {
247 return findRegisterDefOperandIdx(Reg, false, TRI) != -1;
250 /// registerDefIsDead - Returns true if the register is dead in this machine
251 /// instruction. If TargetRegisterInfo is passed, then it also checks
252 /// if there is a dead def of a super-register.
253 bool registerDefIsDead(unsigned Reg,
254 const TargetRegisterInfo *TRI = NULL) const {
255 return findRegisterDefOperandIdx(Reg, true, TRI) != -1;
258 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
259 /// the specific register or -1 if it is not found. It further tightens
260 /// the search criteria to a use that kills the register if isKill is true.
261 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
262 const TargetRegisterInfo *TRI = NULL) const;
264 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
265 /// a pointer to the MachineOperand rather than an index.
266 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
267 const TargetRegisterInfo *TRI = NULL) {
268 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
269 return (Idx == -1) ? NULL : &getOperand(Idx);
272 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
273 /// the specified register or -1 if it is not found. If isDead is true, defs
274 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
275 /// also checks if there is a def of a super-register.
276 int findRegisterDefOperandIdx(unsigned Reg, bool isDead = false,
277 const TargetRegisterInfo *TRI = NULL) const;
279 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
280 /// a pointer to the MachineOperand rather than an index.
281 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
282 const TargetRegisterInfo *TRI = NULL) {
283 int Idx = findRegisterDefOperandIdx(Reg, isDead, TRI);
284 return (Idx == -1) ? NULL : &getOperand(Idx);
287 /// findFirstPredOperandIdx() - Find the index of the first operand in the
288 /// operand list that is used to represent the predicate. It returns -1 if
290 int findFirstPredOperandIdx() const;
292 /// isRegTiedToUseOperand - Given the index of a register def operand,
293 /// check if the register def is tied to a source operand, due to either
294 /// two-address elimination or inline assembly constraints. Returns the
295 /// first tied use operand index by reference is UseOpIdx is not null.
296 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
298 /// isRegTiedToDefOperand - Return true if the use operand of the specified
299 /// index is tied to an def operand. It also returns the def operand index by
300 /// reference if DefOpIdx is not null.
301 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
303 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
305 void copyKillDeadInfo(const MachineInstr *MI);
307 /// copyPredicates - Copies predicate operand(s) from MI.
308 void copyPredicates(const MachineInstr *MI);
310 /// addRegisterKilled - We have determined MI kills a register. Look for the
311 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
312 /// add a implicit operand if it's not found. Returns true if the operand
313 /// exists / is added.
314 bool addRegisterKilled(unsigned IncomingReg,
315 const TargetRegisterInfo *RegInfo,
316 bool AddIfNotFound = false);
318 /// addRegisterDead - We have determined MI defined a register without a use.
319 /// Look for the operand that defines it and mark it as IsDead. If
320 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
321 /// true if the operand exists / is added.
322 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
323 bool AddIfNotFound = false);
325 /// addRegisterDefined - We have determined MI defines a register. Make sure
326 /// there is an operand defining Reg.
327 void addRegisterDefined(unsigned IncomingReg,
328 const TargetRegisterInfo *RegInfo);
330 /// isSafeToMove - Return true if it is safe to move this instruction. If
331 /// SawStore is set to true, it means that there is a store (or call) between
332 /// the instruction's location and its intended destination.
333 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
334 bool &SawStore) const;
336 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
337 /// instruction which defined the specified register instead of copying it.
338 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
339 unsigned DstReg) const;
341 /// hasVolatileMemoryRef - Return true if this instruction may have a
342 /// volatile memory reference, or if the information describing the
343 /// memory reference is not available. Return false if it is known to
344 /// have no volatile memory references.
345 bool hasVolatileMemoryRef() const;
347 /// isInvariantLoad - Return true if this instruction is loading from a
348 /// location whose value is invariant across the function. For example,
349 /// loading a value from the constant pool or from the argument area of
350 /// a function if it does not change. This should only return true of *all*
351 /// loads the instruction does are invariant (if it does multiple loads).
352 bool isInvariantLoad(AliasAnalysis *AA) const;
354 /// isConstantValuePHI - If the specified instruction is a PHI that always
355 /// merges together the same virtual register, return the register, otherwise
357 unsigned isConstantValuePHI() const;
362 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
365 //===--------------------------------------------------------------------===//
366 // Accessors used to build up machine instructions.
368 /// addOperand - Add the specified operand to the instruction. If it is an
369 /// implicit operand, it is added to the end of the operand list. If it is
370 /// an explicit operand it is added at the end of the explicit operand list
371 /// (before the first implicit operand).
372 void addOperand(const MachineOperand &Op);
374 /// setDesc - Replace the instruction descriptor (thus opcode) of
375 /// the current instruction with a new one.
377 void setDesc(const TargetInstrDesc &tid) { TID = &tid; }
379 /// setDebugLoc - Replace current source information with new such.
380 /// Avoid using this, the constructor argument is preferable.
382 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
384 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
385 /// fewer operand than it started with.
387 void RemoveOperand(unsigned i);
389 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
390 /// This function should be used only occasionally. The setMemRefs function
391 /// is the primary method for setting up a MachineInstr's MemRefs list.
392 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
394 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
395 /// list. This does not transfer ownership.
396 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
397 MemRefs = NewMemRefs;
398 MemRefsEnd = NewMemRefsEnd;
402 /// getRegInfo - If this instruction is embedded into a MachineFunction,
403 /// return the MachineRegisterInfo object for the current function, otherwise
405 MachineRegisterInfo *getRegInfo();
407 /// addImplicitDefUseOperands - Add all implicit def and use operands to
408 /// this instruction.
409 void addImplicitDefUseOperands();
411 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
412 /// this instruction from their respective use lists. This requires that the
413 /// operands already be on their use lists.
414 void RemoveRegOperandsFromUseLists();
416 /// AddRegOperandsToUseLists - Add all of the register operands in
417 /// this instruction from their respective use lists. This requires that the
418 /// operands not be on their use lists yet.
419 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
422 //===----------------------------------------------------------------------===//
425 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
430 } // End llvm namespace