1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "Support/Annotation.h"
20 #include "Support/iterator"
27 class MachineBasicBlock;
31 template <typename T> class ilist_traits;
33 typedef int MachineOpCode;
35 //===----------------------------------------------------------------------===//
36 /// MOTy - MachineOperandType - This namespace contains an enum that describes
37 /// how the machine operand is used by the instruction: is it read, defined, or
38 /// both? Note that the MachineInstr/Operator class currently uses bool
39 /// arguments to represent this information instead of an enum. Eventually this
40 /// should change over to use this _easier to read_ representation instead.
44 Use, /// This machine operand is only read by the instruction
45 Def, /// This machine operand is only written by the instruction
46 UseAndDef /// This machine operand is read AND written
50 //===----------------------------------------------------------------------===//
51 // class MachineOperand
54 // Representation of each machine instruction operand.
55 // This class is designed so that you can allocate a vector of operands
56 // first and initialize each one later.
58 // E.g, for this VM instruction:
59 // ptr = alloca type, numElements
60 // we generate 2 machine instructions on the SPARC:
62 // mul Constant, Numelements -> Reg
63 // add %sp, Reg -> Ptr
65 // Each instruction has 3 operands, listed above. Of those:
66 // - Reg, NumElements, and Ptr are of operand type MO_Register.
67 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
69 // For the register operands, the virtual register type is as follows:
71 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
72 // MachineInstr* minstr will point to the instruction that computes reg.
74 // - %sp will be of virtual register type MO_MachineReg.
75 // The field regNum identifies the machine register.
77 // - NumElements will be of virtual register type MO_VirtualReg.
78 // The field Value* value identifies the value.
80 // - Ptr will also be of virtual register type MO_VirtualReg.
81 // Again, the field Value* value identifies the value.
83 //===----------------------------------------------------------------------===//
85 struct MachineOperand {
86 enum MachineOperandType {
87 MO_VirtualRegister, // virtual register for *value
88 MO_MachineRegister, // pre-assigned machine register `regNum'
93 MO_MachineBasicBlock, // MachineBasicBlock reference
94 MO_FrameIndex, // Abstract Stack Frame Index
95 MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
96 MO_ExternalSymbol, // Name of external global symbol
97 MO_GlobalAddress, // Address of a global value
101 // Bit fields of the flags variable used for different operand properties
103 DEFFLAG = 0x01, // this is a def of the operand
104 USEFLAG = 0x02, // this is a use of the operand
105 HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal)
106 LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal)
107 HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal)
108 LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal)
109 PCRELATIVE = 0x40, // Operand is relative to PC, not a global address
114 Value* value; // BasicBlockVal for a label operand.
115 // ConstantVal for a non-address immediate.
116 // Virtual register for an SSA operand,
117 // including hidden operands required for
118 // the generated machine code.
119 // LLVM global for MO_GlobalAddress.
121 int64_t immedVal; // Constant value for an explicit constant
123 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
124 std::string *SymbolName; // For MO_ExternalSymbol type
127 char flags; // see bit field definitions above
128 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
129 int regNum; // register number for an explicit register
130 // will be set for a value after reg allocation
135 opType(MO_VirtualRegister),
138 MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
144 MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
149 case MOTy::Use: flags = USEFLAG; break;
150 case MOTy::Def: flags = DEFFLAG; break;
151 case MOTy::UseAndDef: flags = DEFFLAG | USEFLAG; break;
152 default: assert(0 && "Invalid value for UseTy!");
156 MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy,
157 bool isPCRelative = false)
158 : value(V), opType(OpTy), regNum(-1) {
160 case MOTy::Use: flags = USEFLAG; break;
161 case MOTy::Def: flags = DEFFLAG; break;
162 case MOTy::UseAndDef: flags = DEFFLAG | USEFLAG; break;
163 default: assert(0 && "Invalid value for UseTy!");
165 if (isPCRelative) flags |= PCRELATIVE;
168 MachineOperand(MachineBasicBlock *mbb)
169 : MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) {}
171 MachineOperand(const std::string &SymName, bool isPCRelative)
172 : SymbolName(new std::string(SymName)), flags(isPCRelative ? PCRELATIVE :0),
173 opType(MO_ExternalSymbol), regNum(-1) {}
176 MachineOperand(const MachineOperand &M) : immedVal(M.immedVal),
180 if (isExternalSymbol())
181 SymbolName = new std::string(M.getSymbolName());
185 if (isExternalSymbol())
189 const MachineOperand &operator=(const MachineOperand &MO) {
190 if (isExternalSymbol()) // if old operand had a symbol name,
191 delete SymbolName; // release old memory
192 immedVal = MO.immedVal;
196 if (isExternalSymbol())
197 SymbolName = new std::string(MO.getSymbolName());
201 // Accessor methods. Caller is responsible for checking the
202 // operand type before invoking the corresponding accessor.
204 MachineOperandType getType() const { return opType; }
206 /// isPCRelative - This returns the value of the PCRELATIVE flag, which
207 /// indicates whether this operand should be emitted as a PC relative value
208 /// instead of a global address. This is used for operands of the forms:
209 /// MachineBasicBlock, GlobalAddress, ExternalSymbol
211 bool isPCRelative() const { return (flags & PCRELATIVE) != 0; }
214 /// isRegister - Return true if this operand is a register operand. The X86
215 /// backend currently can't decide whether to use MO_MR or MO_VR to represent
216 /// them, so we accept both.
218 /// Note: The sparc backend should not use this method.
220 bool isRegister() const {
221 return opType == MO_MachineRegister || opType == MO_VirtualRegister;
224 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
225 bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; }
226 bool isImmediate() const {
227 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed;
229 bool isFrameIndex() const { return opType == MO_FrameIndex; }
230 bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; }
231 bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
232 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
234 Value* getVRegValue() const {
235 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
239 Value* getVRegValueOrNull() const {
240 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
241 isPCRelativeDisp()) ? value : NULL;
243 int getMachineRegNum() const {
244 assert(opType == MO_MachineRegister);
247 int64_t getImmedValue() const { assert(isImmediate()); return immedVal; }
248 void setImmedValue(int64_t ImmVal) { assert(isImmediate()); immedVal=ImmVal; }
250 MachineBasicBlock *getMachineBasicBlock() const {
251 assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
254 int getFrameIndex() const { assert(isFrameIndex()); return immedVal; }
255 unsigned getConstantPoolIndex() const {
256 assert(isConstantPoolIndex());
260 GlobalValue *getGlobal() const {
261 assert(isGlobalAddress());
262 return (GlobalValue*)value;
265 const std::string &getSymbolName() const {
266 assert(isExternalSymbol());
270 bool isUse () const { return flags & USEFLAG; }
271 MachineOperand& setUse () { flags |= USEFLAG; return *this; }
272 bool isDef () const { return flags & DEFFLAG; }
273 MachineOperand& setDef () { flags |= DEFFLAG; return *this; }
274 bool isHiBits32 () const { return flags & HIFLAG32; }
275 bool isLoBits32 () const { return flags & LOFLAG32; }
276 bool isHiBits64 () const { return flags & HIFLAG64; }
277 bool isLoBits64 () const { return flags & LOFLAG64; }
279 // used to check if a machine register has been allocated to this operand
280 bool hasAllocatedReg() const {
281 return (regNum >= 0 &&
282 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
283 opType == MO_MachineRegister));
286 // used to get the reg number if when one is allocated
287 int getAllocatedRegNum() const {
288 assert(hasAllocatedReg());
292 // ********** TODO: get rid of this duplicate code! ***********
293 unsigned getReg() const {
294 return getAllocatedRegNum();
296 void setReg(unsigned Reg) {
297 assert(hasAllocatedReg() && "This operand cannot have a register number!");
301 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
305 // Construction methods needed for fine-grain control.
306 // These must be accessed via coresponding methods in MachineInstr.
307 void markHi32() { flags |= HIFLAG32; }
308 void markLo32() { flags |= LOFLAG32; }
309 void markHi64() { flags |= HIFLAG64; }
310 void markLo64() { flags |= LOFLAG64; }
312 // Replaces the Value with its corresponding physical register after
313 // register allocation is complete
314 void setRegForValue(int reg) {
315 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
316 opType == MO_MachineRegister);
320 friend class MachineInstr;
324 //===----------------------------------------------------------------------===//
325 // class MachineInstr
328 // Representation of each machine instruction.
330 // MachineOpCode must be an enum, defined separately for each target.
331 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
333 // There are 2 kinds of operands:
335 // (1) Explicit operands of the machine instruction in vector operands[]
337 // (2) "Implicit operands" are values implicitly used or defined by the
338 // machine instruction, such as arguments to a CALL, return value of
339 // a CALL (if any), and return value of a RETURN.
340 //===----------------------------------------------------------------------===//
343 int opCode; // the opcode
344 unsigned opCodeFlags; // flags modifying instrn behavior
345 std::vector<MachineOperand> operands; // the operands
346 unsigned numImplicitRefs; // number of implicit operands
347 MachineInstr* prev, *next; // links for our intrusive list
348 // OperandComplete - Return true if it's illegal to add a new operand
349 bool OperandsComplete() const;
351 MachineInstr(const MachineInstr &); // DO NOT IMPLEMENT
352 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
355 // Intrusive list support
357 friend class ilist_traits<MachineInstr>;
358 MachineInstr() { /* this is for ilist use only to create the sentinel */ }
359 MachineInstr* getPrev() const { return prev; }
360 MachineInstr* getNext() const { return next; }
362 void setPrev(MachineInstr* mi) { prev = mi; }
363 void setNext(MachineInstr* mi) { next = mi; }
366 MachineInstr(int Opcode, unsigned numOperands);
368 /// MachineInstr ctor - This constructor only does a _reserve_ of the
369 /// operands, not a resize for them. It is expected that if you use this that
370 /// you call add* methods below to fill up the operands, instead of the Set
371 /// methods. Eventually, the "resizing" ctors will be phased out.
373 MachineInstr(int Opcode, unsigned numOperands, bool XX, bool YY);
375 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
376 /// the MachineInstr is created and added to the end of the specified basic
379 MachineInstr(MachineBasicBlock *MBB, int Opcode, unsigned numOps);
381 /// Accessors for opcode.
383 const int getOpcode() const { return opCode; }
385 /// Access to explicit operands of the instruction.
387 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
389 const MachineOperand& getOperand(unsigned i) const {
390 assert(i < getNumOperands() && "getOperand() out of range!");
393 MachineOperand& getOperand(unsigned i) {
394 assert(i < getNumOperands() && "getOperand() out of range!");
399 // Access to explicit or implicit operands of the instruction
400 // This returns the i'th entry in the operand vector.
401 // That represents the i'th explicit operand or the (i-N)'th implicit operand,
402 // depending on whether i < N or i >= N.
404 const MachineOperand& getExplOrImplOperand(unsigned i) const {
405 assert(i < operands.size() && "getExplOrImplOperand() out of range!");
406 return (i < getNumOperands()? getOperand(i)
407 : getImplicitOp(i - getNumOperands()));
411 // Access to implicit operands of the instruction
413 unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
415 MachineOperand& getImplicitOp(unsigned i) {
416 assert(i < numImplicitRefs && "implicit ref# out of range!");
417 return operands[i + operands.size() - numImplicitRefs];
419 const MachineOperand& getImplicitOp(unsigned i) const {
420 assert(i < numImplicitRefs && "implicit ref# out of range!");
421 return operands[i + operands.size() - numImplicitRefs];
424 Value* getImplicitRef(unsigned i) {
425 return getImplicitOp(i).getVRegValue();
427 const Value* getImplicitRef(unsigned i) const {
428 return getImplicitOp(i).getVRegValue();
431 void addImplicitRef(Value* V, bool isDef = false, bool isDefAndUse = false) {
433 addRegOperand(V, isDef, isDefAndUse);
435 void setImplicitRef(unsigned i, Value* V) {
436 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
437 SetMachineOperandVal(i + getNumOperands(),
438 MachineOperand::MO_VirtualRegister, V);
444 void print(std::ostream &OS, const TargetMachine &TM) const;
446 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
449 // Define iterators to access the Value operands of the Machine Instruction.
450 // Note that these iterators only enumerate the explicit operands.
451 // begin() and end() are defined to produce these iterators...
453 template<class _MI, class _V> class ValOpIterator;
454 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
455 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
458 //===--------------------------------------------------------------------===//
459 // Accessors to add operands when building up machine instructions
462 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
465 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
466 assert(!OperandsComplete() &&
467 "Trying to add an operand to a machine instr that is already done!");
468 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
469 !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def)));
472 void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use,
473 bool isPCRelative = false) {
474 assert(!OperandsComplete() &&
475 "Trying to add an operand to a machine instr that is already done!");
476 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
480 void addCCRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) {
481 assert(!OperandsComplete() &&
482 "Trying to add an operand to a machine instr that is already done!");
483 operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy,
488 /// addRegOperand - Add a symbolic virtual register reference...
490 void addRegOperand(int reg, bool isDef) {
491 assert(!OperandsComplete() &&
492 "Trying to add an operand to a machine instr that is already done!");
493 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
494 isDef ? MOTy::Def : MOTy::Use));
497 /// addRegOperand - Add a symbolic virtual register reference...
499 void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
500 assert(!OperandsComplete() &&
501 "Trying to add an operand to a machine instr that is already done!");
502 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
506 /// addPCDispOperand - Add a PC relative displacement operand to the MI
508 void addPCDispOperand(Value *V) {
509 assert(!OperandsComplete() &&
510 "Trying to add an operand to a machine instr that is already done!");
511 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp,
515 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
517 void addMachineRegOperand(int reg, bool isDef) {
518 assert(!OperandsComplete() &&
519 "Trying to add an operand to a machine instr that is already done!");
520 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
521 isDef ? MOTy::Def : MOTy::Use));
524 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
526 void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
527 assert(!OperandsComplete() &&
528 "Trying to add an operand to a machine instr that is already done!");
529 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
533 /// addZeroExtImmOperand - Add a zero extended constant argument to the
534 /// machine instruction.
536 void addZeroExtImmOperand(int64_t intValue) {
537 assert(!OperandsComplete() &&
538 "Trying to add an operand to a machine instr that is already done!");
539 operands.push_back(MachineOperand(intValue,
540 MachineOperand::MO_UnextendedImmed));
543 /// addSignExtImmOperand - Add a zero extended constant argument to the
544 /// machine instruction.
546 void addSignExtImmOperand(int64_t intValue) {
547 assert(!OperandsComplete() &&
548 "Trying to add an operand to a machine instr that is already done!");
549 operands.push_back(MachineOperand(intValue,
550 MachineOperand::MO_SignExtendedImmed));
553 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
554 assert(!OperandsComplete() &&
555 "Trying to add an operand to a machine instr that is already done!");
556 operands.push_back(MachineOperand(MBB));
559 /// addFrameIndexOperand - Add an abstract frame index to the instruction
561 void addFrameIndexOperand(unsigned Idx) {
562 assert(!OperandsComplete() &&
563 "Trying to add an operand to a machine instr that is already done!");
564 operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex));
567 /// addConstantPoolndexOperand - Add a constant pool object index to the
570 void addConstantPoolIndexOperand(unsigned I) {
571 assert(!OperandsComplete() &&
572 "Trying to add an operand to a machine instr that is already done!");
573 operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex));
576 void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative) {
577 assert(!OperandsComplete() &&
578 "Trying to add an operand to a machine instr that is already done!");
579 operands.push_back(MachineOperand((Value*)GV,
580 MachineOperand::MO_GlobalAddress,
581 MOTy::Use, isPCRelative));
584 /// addExternalSymbolOperand - Add an external symbol operand to this instr
586 void addExternalSymbolOperand(const std::string &SymName, bool isPCRelative) {
587 operands.push_back(MachineOperand(SymName, isPCRelative));
590 //===--------------------------------------------------------------------===//
591 // Accessors used to modify instructions in place.
593 // FIXME: Move this stuff to MachineOperand itself!
595 /// replace - Support to rewrite a machine instruction in place: for now,
596 /// simply replace() and then set new operands with Set.*Operand methods
599 void replace(int Opcode, unsigned numOperands);
601 /// setOpcode - Replace the opcode of the current instruction with a new one.
603 void setOpcode(unsigned Op) { opCode = Op; }
605 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
606 /// fewer operand than it started with.
608 void RemoveOperand(unsigned i) {
609 operands.erase(operands.begin()+i);
612 // Access to set the operands when building the machine instruction
614 void SetMachineOperandVal (unsigned i,
615 MachineOperand::MachineOperandType operandType,
618 void SetMachineOperandConst (unsigned i,
619 MachineOperand::MachineOperandType operandType,
622 void SetMachineOperandReg(unsigned i, int regNum);
625 unsigned substituteValue(const Value* oldVal, Value* newVal,
626 bool defsOnly, bool notDefsAndUses,
627 bool& someArgsWereIgnored);
629 void setOperandHi32(unsigned i) { operands[i].markHi32(); }
630 void setOperandLo32(unsigned i) { operands[i].markLo32(); }
631 void setOperandHi64(unsigned i) { operands[i].markHi64(); }
632 void setOperandLo64(unsigned i) { operands[i].markLo64(); }
635 // SetRegForOperand -
636 // SetRegForImplicitRef -
637 // Mark an explicit or implicit operand with its allocated physical register.
639 void SetRegForOperand(unsigned i, int regNum);
640 void SetRegForImplicitRef(unsigned i, int regNum);
643 // Iterator to enumerate machine operands.
645 template<class MITy, class VTy>
646 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
650 void skipToNextVal() {
651 while (i < MI->getNumOperands() &&
652 !( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister ||
653 MI->getOperand(i).getType() == MachineOperand::MO_CCRegister)
654 && MI->getOperand(i).getVRegValue() != 0))
658 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
663 typedef ValOpIterator<MITy, VTy> _Self;
665 inline VTy operator*() const {
666 return MI->getOperand(i).getVRegValue();
669 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
670 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
672 inline VTy operator->() const { return operator*(); }
674 inline bool isUse() const { return MI->getOperand(i).isUse(); }
675 inline bool isDef() const { return MI->getOperand(i).isDef(); }
677 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
678 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
680 inline bool operator==(const _Self &y) const {
683 inline bool operator!=(const _Self &y) const {
684 return !operator==(y);
687 static _Self begin(MITy MI) {
690 static _Self end(MITy MI) {
691 return _Self(MI, MI->getNumOperands());
695 // define begin() and end()
696 val_op_iterator begin() { return val_op_iterator::begin(this); }
697 val_op_iterator end() { return val_op_iterator::end(this); }
699 const_val_op_iterator begin() const {
700 return const_val_op_iterator::begin(this);
702 const_val_op_iterator end() const {
703 return const_val_op_iterator::end(this);
708 //===----------------------------------------------------------------------===//
711 std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI);
712 std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO);
713 void PrintMachineInstructions(const Function *F);
715 } // End llvm namespace