1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/ADT/ilist.h"
20 #include "llvm/ADT/ilist_node.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/CodeGen/MachineOperand.h"
23 #include "llvm/Target/TargetInstrDesc.h"
24 #include "llvm/Target/TargetOpcodes.h"
25 #include "llvm/Support/DebugLoc.h"
31 class TargetInstrDesc;
32 class TargetInstrInfo;
33 class TargetRegisterInfo;
34 class MachineFunction;
35 class MachineMemOperand;
37 //===----------------------------------------------------------------------===//
38 /// MachineInstr - Representation of each machine instruction.
40 class MachineInstr : public ilist_node<MachineInstr> {
42 typedef MachineMemOperand **mmo_iterator;
45 const TargetInstrDesc *TID; // Instruction descriptor.
46 unsigned short NumImplicitOps; // Number of implicit operands (which
47 // are determined at construction time).
49 unsigned short AsmPrinterFlags; // Various bits of information used by
50 // the AsmPrinter to emit helpful
51 // comments. This is *not* semantic
52 // information. Do not use this for
53 // anything other than to convey comment
54 // information to AsmPrinter.
56 std::vector<MachineOperand> Operands; // the operands
57 mmo_iterator MemRefs; // information on memory references
58 mmo_iterator MemRefsEnd;
59 MachineBasicBlock *Parent; // Pointer to the owning basic block.
60 DebugLoc debugLoc; // Source line information.
62 // OperandComplete - Return true if it's illegal to add a new operand
63 bool OperandsComplete() const;
65 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
66 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
68 // Intrusive list support
69 friend struct ilist_traits<MachineInstr>;
70 friend struct ilist_traits<MachineBasicBlock>;
71 void setParent(MachineBasicBlock *P) { Parent = P; }
73 /// MachineInstr ctor - This constructor creates a copy of the given
74 /// MachineInstr in the given MachineFunction.
75 MachineInstr(MachineFunction &, const MachineInstr &);
77 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
78 /// TID NULL and no operands.
81 // The next two constructors have DebugLoc and non-DebugLoc versions;
82 // over time, the non-DebugLoc versions should be phased out and eventually
85 /// MachineInstr ctor - This constructor create a MachineInstr and add the
86 /// implicit operands. It reserves space for number of operands specified by
87 /// TargetInstrDesc. The version with a DebugLoc should be preferred.
88 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
90 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
91 /// the MachineInstr is created and added to the end of the specified basic
92 /// block. The version with a DebugLoc should be preferred.
94 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
96 /// MachineInstr ctor - This constructor create a MachineInstr and add the
97 /// implicit operands. It reserves space for number of operands specified by
98 /// TargetInstrDesc. An explicit DebugLoc is supplied.
99 explicit MachineInstr(const TargetInstrDesc &TID, const DebugLoc dl,
102 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
103 /// the MachineInstr is created and added to the end of the specified basic
106 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
107 const TargetInstrDesc &TID);
111 // MachineInstrs are pool-allocated and owned by MachineFunction.
112 friend class MachineFunction;
115 const MachineBasicBlock* getParent() const { return Parent; }
116 MachineBasicBlock* getParent() { return Parent; }
118 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
120 unsigned short getAsmPrinterFlags() const { return AsmPrinterFlags; }
122 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
124 bool getAsmPrinterFlag(unsigned Flag) const {
125 return AsmPrinterFlags & Flag;
128 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
130 void setAsmPrinterFlag(unsigned short Flag) {
131 AsmPrinterFlags |= Flag;
134 /// getDebugLoc - Returns the debug location id of this MachineInstr.
136 DebugLoc getDebugLoc() const { return debugLoc; }
138 /// getDesc - Returns the target instruction descriptor of this
140 const TargetInstrDesc &getDesc() const { return *TID; }
142 /// getOpcode - Returns the opcode of this MachineInstr.
144 int getOpcode() const { return TID->Opcode; }
146 /// Access to explicit operands of the instruction.
148 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
150 const MachineOperand& getOperand(unsigned i) const {
151 assert(i < getNumOperands() && "getOperand() out of range!");
154 MachineOperand& getOperand(unsigned i) {
155 assert(i < getNumOperands() && "getOperand() out of range!");
159 /// getNumExplicitOperands - Returns the number of non-implicit operands.
161 unsigned getNumExplicitOperands() const;
163 /// Access to memory operands of the instruction
164 mmo_iterator memoperands_begin() const { return MemRefs; }
165 mmo_iterator memoperands_end() const { return MemRefsEnd; }
166 bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
168 /// hasOneMemOperand - Return true if this instruction has exactly one
169 /// MachineMemOperand.
170 bool hasOneMemOperand() const {
171 return MemRefsEnd - MemRefs == 1;
174 /// isIdenticalTo - Return true if this instruction is identical to (same
175 /// opcode and same operands as) the specified instruction.
176 bool isIdenticalTo(const MachineInstr *Other) const {
177 if (Other->getOpcode() != getOpcode() ||
178 Other->getNumOperands() != getNumOperands())
180 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
181 if (!getOperand(i).isIdenticalTo(Other->getOperand(i)))
186 /// removeFromParent - This method unlinks 'this' from the containing basic
187 /// block, and returns it, but does not delete it.
188 MachineInstr *removeFromParent();
190 /// eraseFromParent - This method unlinks 'this' from the containing basic
191 /// block and deletes it.
192 void eraseFromParent();
194 /// isLabel - Returns true if the MachineInstr represents a label.
196 bool isLabel() const {
197 return getOpcode() == TargetOpcode::DBG_LABEL ||
198 getOpcode() == TargetOpcode::EH_LABEL ||
199 getOpcode() == TargetOpcode::GC_LABEL;
202 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
203 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
204 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
205 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
207 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
208 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
209 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
210 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
211 bool isExtractSubreg() const {
212 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
214 bool isInsertSubreg() const {
215 return getOpcode() == TargetOpcode::INSERT_SUBREG;
217 bool isSubregToReg() const {
218 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
221 /// readsRegister - Return true if the MachineInstr reads the specified
222 /// register. If TargetRegisterInfo is passed, then it also checks if there
223 /// is a read of a super-register.
224 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
225 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
228 /// killsRegister - Return true if the MachineInstr kills the specified
229 /// register. If TargetRegisterInfo is passed, then it also checks if there is
230 /// a kill of a super-register.
231 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
232 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
235 /// modifiesRegister - Return true if the MachineInstr modifies the
236 /// specified register. If TargetRegisterInfo is passed, then it also checks
237 /// if there is a def of a super-register.
238 bool modifiesRegister(unsigned Reg,
239 const TargetRegisterInfo *TRI = NULL) const {
240 return findRegisterDefOperandIdx(Reg, false, TRI) != -1;
243 /// registerDefIsDead - Returns true if the register is dead in this machine
244 /// instruction. If TargetRegisterInfo is passed, then it also checks
245 /// if there is a dead def of a super-register.
246 bool registerDefIsDead(unsigned Reg,
247 const TargetRegisterInfo *TRI = NULL) const {
248 return findRegisterDefOperandIdx(Reg, true, TRI) != -1;
251 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
252 /// the specific register or -1 if it is not found. It further tightens
253 /// the search criteria to a use that kills the register if isKill is true.
254 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
255 const TargetRegisterInfo *TRI = NULL) const;
257 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
258 /// a pointer to the MachineOperand rather than an index.
259 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
260 const TargetRegisterInfo *TRI = NULL) {
261 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
262 return (Idx == -1) ? NULL : &getOperand(Idx);
265 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
266 /// the specified register or -1 if it is not found. If isDead is true, defs
267 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
268 /// also checks if there is a def of a super-register.
269 int findRegisterDefOperandIdx(unsigned Reg, bool isDead = false,
270 const TargetRegisterInfo *TRI = NULL) const;
272 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
273 /// a pointer to the MachineOperand rather than an index.
274 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
275 const TargetRegisterInfo *TRI = NULL) {
276 int Idx = findRegisterDefOperandIdx(Reg, isDead, TRI);
277 return (Idx == -1) ? NULL : &getOperand(Idx);
280 /// findFirstPredOperandIdx() - Find the index of the first operand in the
281 /// operand list that is used to represent the predicate. It returns -1 if
283 int findFirstPredOperandIdx() const;
285 /// isRegTiedToUseOperand - Given the index of a register def operand,
286 /// check if the register def is tied to a source operand, due to either
287 /// two-address elimination or inline assembly constraints. Returns the
288 /// first tied use operand index by reference is UseOpIdx is not null.
289 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
291 /// isRegTiedToDefOperand - Return true if the use operand of the specified
292 /// index is tied to an def operand. It also returns the def operand index by
293 /// reference if DefOpIdx is not null.
294 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
296 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
298 void copyKillDeadInfo(const MachineInstr *MI);
300 /// copyPredicates - Copies predicate operand(s) from MI.
301 void copyPredicates(const MachineInstr *MI);
303 /// addRegisterKilled - We have determined MI kills a register. Look for the
304 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
305 /// add a implicit operand if it's not found. Returns true if the operand
306 /// exists / is added.
307 bool addRegisterKilled(unsigned IncomingReg,
308 const TargetRegisterInfo *RegInfo,
309 bool AddIfNotFound = false);
311 /// addRegisterDead - We have determined MI defined a register without a use.
312 /// Look for the operand that defines it and mark it as IsDead. If
313 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
314 /// true if the operand exists / is added.
315 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
316 bool AddIfNotFound = false);
318 /// addRegisterDefined - We have determined MI defines a register. Make sure
319 /// there is an operand defining Reg.
320 void addRegisterDefined(unsigned IncomingReg,
321 const TargetRegisterInfo *RegInfo);
323 /// isSafeToMove - Return true if it is safe to move this instruction. If
324 /// SawStore is set to true, it means that there is a store (or call) between
325 /// the instruction's location and its intended destination.
326 bool isSafeToMove(const TargetInstrInfo *TII, bool &SawStore,
327 AliasAnalysis *AA) const;
329 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
330 /// instruction which defined the specified register instead of copying it.
331 bool isSafeToReMat(const TargetInstrInfo *TII, unsigned DstReg,
332 AliasAnalysis *AA) const;
334 /// hasVolatileMemoryRef - Return true if this instruction may have a
335 /// volatile memory reference, or if the information describing the
336 /// memory reference is not available. Return false if it is known to
337 /// have no volatile memory references.
338 bool hasVolatileMemoryRef() const;
340 /// isInvariantLoad - Return true if this instruction is loading from a
341 /// location whose value is invariant across the function. For example,
342 /// loading a value from the constant pool or from from the argument area of
343 /// a function if it does not change. This should only return true of *all*
344 /// loads the instruction does are invariant (if it does multiple loads).
345 bool isInvariantLoad(AliasAnalysis *AA) const;
347 /// isConstantValuePHI - If the specified instruction is a PHI that always
348 /// merges together the same virtual register, return the register, otherwise
350 unsigned isConstantValuePHI() const;
355 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
358 //===--------------------------------------------------------------------===//
359 // Accessors used to build up machine instructions.
361 /// addOperand - Add the specified operand to the instruction. If it is an
362 /// implicit operand, it is added to the end of the operand list. If it is
363 /// an explicit operand it is added at the end of the explicit operand list
364 /// (before the first implicit operand).
365 void addOperand(const MachineOperand &Op);
367 /// setDesc - Replace the instruction descriptor (thus opcode) of
368 /// the current instruction with a new one.
370 void setDesc(const TargetInstrDesc &tid) { TID = &tid; }
372 /// setDebugLoc - Replace current source information with new such.
373 /// Avoid using this, the constructor argument is preferable.
375 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
377 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
378 /// fewer operand than it started with.
380 void RemoveOperand(unsigned i);
382 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
383 /// This function should be used only occasionally. The setMemRefs function
384 /// is the primary method for setting up a MachineInstr's MemRefs list.
385 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
387 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
388 /// list. This does not transfer ownership.
389 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
390 MemRefs = NewMemRefs;
391 MemRefsEnd = NewMemRefsEnd;
395 /// getRegInfo - If this instruction is embedded into a MachineFunction,
396 /// return the MachineRegisterInfo object for the current function, otherwise
398 MachineRegisterInfo *getRegInfo();
400 /// addImplicitDefUseOperands - Add all implicit def and use operands to
401 /// this instruction.
402 void addImplicitDefUseOperands();
404 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
405 /// this instruction from their respective use lists. This requires that the
406 /// operands already be on their use lists.
407 void RemoveRegOperandsFromUseLists();
409 /// AddRegOperandsToUseLists - Add all of the register operands in
410 /// this instruction from their respective use lists. This requires that the
411 /// operands not be on their use lists yet.
412 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
415 //===----------------------------------------------------------------------===//
418 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
423 } // End llvm namespace