1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/DenseMapInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/ilist.h"
24 #include "llvm/ADT/ilist_node.h"
25 #include "llvm/CodeGen/MachineOperand.h"
26 #include "llvm/IR/InlineAsm.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/Support/DebugLoc.h"
29 #include "llvm/Target/TargetOpcodes.h"
34 template <typename T> class SmallVectorImpl;
36 class TargetInstrInfo;
37 class TargetRegisterClass;
38 class TargetRegisterInfo;
39 class MachineFunction;
40 class MachineMemOperand;
42 //===----------------------------------------------------------------------===//
43 /// MachineInstr - Representation of each machine instruction.
45 class MachineInstr : public ilist_node<MachineInstr> {
47 typedef MachineMemOperand **mmo_iterator;
49 /// Flags to specify different kinds of comments to output in
50 /// assembly code. These flags carry semantic information not
51 /// otherwise easily derivable from the IR text.
59 FrameSetup = 1 << 0, // Instruction is used as a part of
60 // function frame setup code.
61 BundledPred = 1 << 1, // Instruction has bundled predecessors.
62 BundledSucc = 1 << 2 // Instruction has bundled successors.
65 const MCInstrDesc *MCID; // Instruction descriptor.
67 uint8_t Flags; // Various bits of additional
68 // information about machine
71 uint8_t AsmPrinterFlags; // Various bits of information used by
72 // the AsmPrinter to emit helpful
73 // comments. This is *not* semantic
74 // information. Do not use this for
75 // anything other than to convey comment
76 // information to AsmPrinter.
78 uint16_t NumMemRefs; // information on memory references
81 std::vector<MachineOperand> Operands; // the operands
82 MachineBasicBlock *Parent; // Pointer to the owning basic block.
83 DebugLoc debugLoc; // Source line information.
85 MachineInstr(const MachineInstr&) LLVM_DELETED_FUNCTION;
86 void operator=(const MachineInstr&) LLVM_DELETED_FUNCTION;
88 // Intrusive list support
89 friend struct ilist_traits<MachineInstr>;
90 friend struct ilist_traits<MachineBasicBlock>;
91 void setParent(MachineBasicBlock *P) { Parent = P; }
93 /// MachineInstr ctor - This constructor creates a copy of the given
94 /// MachineInstr in the given MachineFunction.
95 MachineInstr(MachineFunction &, const MachineInstr &);
97 /// MachineInstr ctor - This constructor create a MachineInstr and add the
98 /// implicit operands. It reserves space for number of operands specified by
99 /// MCInstrDesc. An explicit DebugLoc is supplied.
100 MachineInstr(MachineFunction&, const MCInstrDesc &MCID,
101 const DebugLoc dl, bool NoImp = false);
105 // MachineInstrs are pool-allocated and owned by MachineFunction.
106 friend class MachineFunction;
109 const MachineBasicBlock* getParent() const { return Parent; }
110 MachineBasicBlock* getParent() { return Parent; }
112 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
114 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
116 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
118 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
120 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
122 bool getAsmPrinterFlag(CommentFlag Flag) const {
123 return AsmPrinterFlags & Flag;
126 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
128 void setAsmPrinterFlag(CommentFlag Flag) {
129 AsmPrinterFlags |= (uint8_t)Flag;
132 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
134 void clearAsmPrinterFlag(CommentFlag Flag) {
135 AsmPrinterFlags &= ~Flag;
138 /// getFlags - Return the MI flags bitvector.
139 uint8_t getFlags() const {
143 /// getFlag - Return whether an MI flag is set.
144 bool getFlag(MIFlag Flag) const {
148 /// setFlag - Set a MI flag.
149 void setFlag(MIFlag Flag) {
150 Flags |= (uint8_t)Flag;
153 void setFlags(unsigned flags) {
154 // Filter out the automatically maintained flags.
155 unsigned Mask = BundledPred | BundledSucc;
156 Flags = (Flags & Mask) | (flags & ~Mask);
159 /// clearFlag - Clear a MI flag.
160 void clearFlag(MIFlag Flag) {
161 Flags &= ~((uint8_t)Flag);
164 /// isInsideBundle - Return true if MI is in a bundle (but not the first MI
167 /// A bundle looks like this before it's finalized:
179 /// In this case, the first MI starts a bundle but is not inside a bundle, the
180 /// next 2 MIs are considered "inside" the bundle.
182 /// After a bundle is finalized, it looks like this:
198 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
199 /// a bundle, but the next three MIs are.
200 bool isInsideBundle() const {
201 return getFlag(BundledPred);
204 /// isBundled - Return true if this instruction part of a bundle. This is true
205 /// if either itself or its following instruction is marked "InsideBundle".
206 bool isBundled() const {
207 return isBundledWithPred() || isBundledWithSucc();
210 /// Return true if this instruction is part of a bundle, and it is not the
211 /// first instruction in the bundle.
212 bool isBundledWithPred() const { return getFlag(BundledPred); }
214 /// Return true if this instruction is part of a bundle, and it is not the
215 /// last instruction in the bundle.
216 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
218 /// Bundle this instruction with its predecessor. This can be an unbundled
219 /// instruction, or it can be the first instruction in a bundle.
220 void bundleWithPred();
222 /// Bundle this instruction with its successor. This can be an unbundled
223 /// instruction, or it can be the last instruction in a bundle.
224 void bundleWithSucc();
226 /// Break bundle above this instruction.
227 void unbundleFromPred();
229 /// Break bundle below this instruction.
230 void unbundleFromSucc();
232 /// getDebugLoc - Returns the debug location id of this MachineInstr.
234 DebugLoc getDebugLoc() const { return debugLoc; }
236 /// emitError - Emit an error referring to the source location of this
237 /// instruction. This should only be used for inline assembly that is somehow
238 /// impossible to compile. Other errors should have been handled much
241 /// If this method returns, the caller should try to recover from the error.
243 void emitError(StringRef Msg) const;
245 /// getDesc - Returns the target instruction descriptor of this
247 const MCInstrDesc &getDesc() const { return *MCID; }
249 /// getOpcode - Returns the opcode of this MachineInstr.
251 int getOpcode() const { return MCID->Opcode; }
253 /// Access to explicit operands of the instruction.
255 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
257 const MachineOperand& getOperand(unsigned i) const {
258 assert(i < getNumOperands() && "getOperand() out of range!");
261 MachineOperand& getOperand(unsigned i) {
262 assert(i < getNumOperands() && "getOperand() out of range!");
266 /// getNumExplicitOperands - Returns the number of non-implicit operands.
268 unsigned getNumExplicitOperands() const;
270 /// iterator/begin/end - Iterate over all operands of a machine instruction.
271 typedef std::vector<MachineOperand>::iterator mop_iterator;
272 typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;
274 mop_iterator operands_begin() { return Operands.begin(); }
275 mop_iterator operands_end() { return Operands.end(); }
277 const_mop_iterator operands_begin() const { return Operands.begin(); }
278 const_mop_iterator operands_end() const { return Operands.end(); }
280 /// Access to memory operands of the instruction
281 mmo_iterator memoperands_begin() const { return MemRefs; }
282 mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
283 bool memoperands_empty() const { return NumMemRefs == 0; }
285 /// hasOneMemOperand - Return true if this instruction has exactly one
286 /// MachineMemOperand.
287 bool hasOneMemOperand() const {
288 return NumMemRefs == 1;
291 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
292 /// queries but they are bundle aware.
295 IgnoreBundle, // Ignore bundles
296 AnyInBundle, // Return true if any instruction in bundle has property
297 AllInBundle // Return true if all instructions in bundle have property
300 /// hasProperty - Return true if the instruction (or in the case of a bundle,
301 /// the instructions inside the bundle) has the specified property.
302 /// The first argument is the property being queried.
303 /// The second argument indicates whether the query should look inside
304 /// instruction bundles.
305 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
306 // Inline the fast path.
307 if (Type == IgnoreBundle || !isBundle())
308 return getDesc().getFlags() & (1 << MCFlag);
310 // If we have a bundle, take the slow path.
311 return hasPropertyInBundle(1 << MCFlag, Type);
314 /// isVariadic - Return true if this instruction can have a variable number of
315 /// operands. In this case, the variable operands will be after the normal
316 /// operands but before the implicit definitions and uses (if any are
318 bool isVariadic(QueryType Type = IgnoreBundle) const {
319 return hasProperty(MCID::Variadic, Type);
322 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
323 /// ARM instructions which can set condition code if 's' bit is set.
324 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
325 return hasProperty(MCID::HasOptionalDef, Type);
328 /// isPseudo - Return true if this is a pseudo instruction that doesn't
329 /// correspond to a real machine instruction.
331 bool isPseudo(QueryType Type = IgnoreBundle) const {
332 return hasProperty(MCID::Pseudo, Type);
335 bool isReturn(QueryType Type = AnyInBundle) const {
336 return hasProperty(MCID::Return, Type);
339 bool isCall(QueryType Type = AnyInBundle) const {
340 return hasProperty(MCID::Call, Type);
343 /// isBarrier - Returns true if the specified instruction stops control flow
344 /// from executing the instruction immediately following it. Examples include
345 /// unconditional branches and return instructions.
346 bool isBarrier(QueryType Type = AnyInBundle) const {
347 return hasProperty(MCID::Barrier, Type);
350 /// isTerminator - Returns true if this instruction part of the terminator for
351 /// a basic block. Typically this is things like return and branch
354 /// Various passes use this to insert code into the bottom of a basic block,
355 /// but before control flow occurs.
356 bool isTerminator(QueryType Type = AnyInBundle) const {
357 return hasProperty(MCID::Terminator, Type);
360 /// isBranch - Returns true if this is a conditional, unconditional, or
361 /// indirect branch. Predicates below can be used to discriminate between
362 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
363 /// get more information.
364 bool isBranch(QueryType Type = AnyInBundle) const {
365 return hasProperty(MCID::Branch, Type);
368 /// isIndirectBranch - Return true if this is an indirect branch, such as a
369 /// branch through a register.
370 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
371 return hasProperty(MCID::IndirectBranch, Type);
374 /// isConditionalBranch - Return true if this is a branch which may fall
375 /// through to the next instruction or may transfer control flow to some other
376 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
377 /// information about this branch.
378 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
379 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
382 /// isUnconditionalBranch - Return true if this is a branch which always
383 /// transfers control flow to some other block. The
384 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
385 /// about this branch.
386 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
387 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
390 // isPredicable - Return true if this instruction has a predicate operand that
391 // controls execution. It may be set to 'always', or may be set to other
392 /// values. There are various methods in TargetInstrInfo that can be used to
393 /// control and modify the predicate in this instruction.
394 bool isPredicable(QueryType Type = AllInBundle) const {
395 // If it's a bundle than all bundled instructions must be predicable for this
397 return hasProperty(MCID::Predicable, Type);
400 /// isCompare - Return true if this instruction is a comparison.
401 bool isCompare(QueryType Type = IgnoreBundle) const {
402 return hasProperty(MCID::Compare, Type);
405 /// isMoveImmediate - Return true if this instruction is a move immediate
406 /// (including conditional moves) instruction.
407 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
408 return hasProperty(MCID::MoveImm, Type);
411 /// isBitcast - Return true if this instruction is a bitcast instruction.
413 bool isBitcast(QueryType Type = IgnoreBundle) const {
414 return hasProperty(MCID::Bitcast, Type);
417 /// isSelect - Return true if this instruction is a select instruction.
419 bool isSelect(QueryType Type = IgnoreBundle) const {
420 return hasProperty(MCID::Select, Type);
423 /// isNotDuplicable - Return true if this instruction cannot be safely
424 /// duplicated. For example, if the instruction has a unique labels attached
425 /// to it, duplicating it would cause multiple definition errors.
426 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
427 return hasProperty(MCID::NotDuplicable, Type);
430 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
431 /// which must be filled by the code generator.
432 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
433 return hasProperty(MCID::DelaySlot, Type);
436 /// canFoldAsLoad - Return true for instructions that can be folded as
437 /// memory operands in other instructions. The most common use for this
438 /// is instructions that are simple loads from memory that don't modify
439 /// the loaded value in any way, but it can also be used for instructions
440 /// that can be expressed as constant-pool loads, such as V_SETALLONES
441 /// on x86, to allow them to be folded when it is beneficial.
442 /// This should only be set on instructions that return a value in their
443 /// only virtual register definition.
444 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
445 return hasProperty(MCID::FoldableAsLoad, Type);
448 //===--------------------------------------------------------------------===//
449 // Side Effect Analysis
450 //===--------------------------------------------------------------------===//
452 /// mayLoad - Return true if this instruction could possibly read memory.
453 /// Instructions with this flag set are not necessarily simple load
454 /// instructions, they may load a value and modify it, for example.
455 bool mayLoad(QueryType Type = AnyInBundle) const {
457 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
458 if (ExtraInfo & InlineAsm::Extra_MayLoad)
461 return hasProperty(MCID::MayLoad, Type);
465 /// mayStore - Return true if this instruction could possibly modify memory.
466 /// Instructions with this flag set are not necessarily simple store
467 /// instructions, they may store a modified value based on their operands, or
468 /// may not actually modify anything, for example.
469 bool mayStore(QueryType Type = AnyInBundle) const {
471 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
472 if (ExtraInfo & InlineAsm::Extra_MayStore)
475 return hasProperty(MCID::MayStore, Type);
478 //===--------------------------------------------------------------------===//
479 // Flags that indicate whether an instruction can be modified by a method.
480 //===--------------------------------------------------------------------===//
482 /// isCommutable - Return true if this may be a 2- or 3-address
483 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
484 /// result if Y and Z are exchanged. If this flag is set, then the
485 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
488 /// Note that this flag may be set on instructions that are only commutable
489 /// sometimes. In these cases, the call to commuteInstruction will fail.
490 /// Also note that some instructions require non-trivial modification to
492 bool isCommutable(QueryType Type = IgnoreBundle) const {
493 return hasProperty(MCID::Commutable, Type);
496 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
497 /// which can be changed into a 3-address instruction if needed. Doing this
498 /// transformation can be profitable in the register allocator, because it
499 /// means that the instruction can use a 2-address form if possible, but
500 /// degrade into a less efficient form if the source and dest register cannot
501 /// be assigned to the same register. For example, this allows the x86
502 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
503 /// is the same speed as the shift but has bigger code size.
505 /// If this returns true, then the target must implement the
506 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
507 /// is allowed to fail if the transformation isn't valid for this specific
508 /// instruction (e.g. shl reg, 4 on x86).
510 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
511 return hasProperty(MCID::ConvertibleTo3Addr, Type);
514 /// usesCustomInsertionHook - Return true if this instruction requires
515 /// custom insertion support when the DAG scheduler is inserting it into a
516 /// machine basic block. If this is true for the instruction, it basically
517 /// means that it is a pseudo instruction used at SelectionDAG time that is
518 /// expanded out into magic code by the target when MachineInstrs are formed.
520 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
521 /// is used to insert this into the MachineBasicBlock.
522 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
523 return hasProperty(MCID::UsesCustomInserter, Type);
526 /// hasPostISelHook - Return true if this instruction requires *adjustment*
527 /// after instruction selection by calling a target hook. For example, this
528 /// can be used to fill in ARM 's' optional operand depending on whether
529 /// the conditional flag register is used.
530 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
531 return hasProperty(MCID::HasPostISelHook, Type);
534 /// isRematerializable - Returns true if this instruction is a candidate for
535 /// remat. This flag is deprecated, please don't use it anymore. If this
536 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
537 /// verify the instruction is really rematable.
538 bool isRematerializable(QueryType Type = AllInBundle) const {
539 // It's only possible to re-mat a bundle if all bundled instructions are
540 // re-materializable.
541 return hasProperty(MCID::Rematerializable, Type);
544 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
545 /// less) than a move instruction. This is useful during certain types of
546 /// optimizations (e.g., remat during two-address conversion or machine licm)
547 /// where we would like to remat or hoist the instruction, but not if it costs
548 /// more than moving the instruction into the appropriate register. Note, we
549 /// are not marking copies from and to the same register class with this flag.
550 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
551 // Only returns true for a bundle if all bundled instructions are cheap.
552 // FIXME: This probably requires a target hook.
553 return hasProperty(MCID::CheapAsAMove, Type);
556 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
557 /// have special register allocation requirements that are not captured by the
558 /// operand register classes. e.g. ARM::STRD's two source registers must be an
559 /// even / odd pair, ARM::STM registers have to be in ascending order.
560 /// Post-register allocation passes should not attempt to change allocations
561 /// for sources of instructions with this flag.
562 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
563 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
566 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
567 /// have special register allocation requirements that are not captured by the
568 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
569 /// even / odd pair, ARM::LDM registers have to be in ascending order.
570 /// Post-register allocation passes should not attempt to change allocations
571 /// for definitions of instructions with this flag.
572 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
573 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
578 CheckDefs, // Check all operands for equality
579 CheckKillDead, // Check all operands including kill / dead markers
580 IgnoreDefs, // Ignore all definitions
581 IgnoreVRegDefs // Ignore virtual register definitions
584 /// isIdenticalTo - Return true if this instruction is identical to (same
585 /// opcode and same operands as) the specified instruction.
586 bool isIdenticalTo(const MachineInstr *Other,
587 MICheckType Check = CheckDefs) const;
589 /// Unlink 'this' from the containing basic block, and return it without
592 /// This function can not be used on bundled instructions, use
593 /// removeFromBundle() to remove individual instructions from a bundle.
594 MachineInstr *removeFromParent();
596 /// Unlink this instruction from its basic block and return it without
599 /// If the instruction is part of a bundle, the other instructions in the
600 /// bundle remain bundled.
601 MachineInstr *removeFromBundle();
603 /// Unlink 'this' from the containing basic block and delete it.
605 /// If this instruction is the header of a bundle, the whole bundle is erased.
606 /// This function can not be used for instructions inside a bundle, use
607 /// eraseFromBundle() to erase individual bundled instructions.
608 void eraseFromParent();
610 /// Unlink 'this' form its basic block and delete it.
612 /// If the instruction is part of a bundle, the other instructions in the
613 /// bundle remain bundled.
614 void eraseFromBundle();
616 /// isLabel - Returns true if the MachineInstr represents a label.
618 bool isLabel() const {
619 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
620 getOpcode() == TargetOpcode::EH_LABEL ||
621 getOpcode() == TargetOpcode::GC_LABEL;
624 bool isPrologLabel() const {
625 return getOpcode() == TargetOpcode::PROLOG_LABEL;
627 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
628 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
629 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
631 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
632 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
633 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
634 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
635 bool isStackAligningInlineAsm() const;
636 InlineAsm::AsmDialect getInlineAsmDialect() const;
637 bool isInsertSubreg() const {
638 return getOpcode() == TargetOpcode::INSERT_SUBREG;
640 bool isSubregToReg() const {
641 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
643 bool isRegSequence() const {
644 return getOpcode() == TargetOpcode::REG_SEQUENCE;
646 bool isBundle() const {
647 return getOpcode() == TargetOpcode::BUNDLE;
649 bool isCopy() const {
650 return getOpcode() == TargetOpcode::COPY;
652 bool isFullCopy() const {
653 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
656 /// isCopyLike - Return true if the instruction behaves like a copy.
657 /// This does not include native copy instructions.
658 bool isCopyLike() const {
659 return isCopy() || isSubregToReg();
662 /// isIdentityCopy - Return true is the instruction is an identity copy.
663 bool isIdentityCopy() const {
664 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
665 getOperand(0).getSubReg() == getOperand(1).getSubReg();
668 /// isTransient - Return true if this is a transient instruction that is
669 /// either very likely to be eliminated during register allocation (such as
670 /// copy-like instructions), or if this instruction doesn't have an
671 /// execution-time cost.
672 bool isTransient() const {
673 switch(getOpcode()) {
674 default: return false;
675 // Copy-like instructions are usually eliminated during register allocation.
676 case TargetOpcode::PHI:
677 case TargetOpcode::COPY:
678 case TargetOpcode::INSERT_SUBREG:
679 case TargetOpcode::SUBREG_TO_REG:
680 case TargetOpcode::REG_SEQUENCE:
681 // Pseudo-instructions that don't produce any real output.
682 case TargetOpcode::IMPLICIT_DEF:
683 case TargetOpcode::KILL:
684 case TargetOpcode::PROLOG_LABEL:
685 case TargetOpcode::EH_LABEL:
686 case TargetOpcode::GC_LABEL:
687 case TargetOpcode::DBG_VALUE:
692 /// getBundleSize - Return the number of instructions inside the MI bundle.
693 unsigned getBundleSize() const;
695 /// readsRegister - Return true if the MachineInstr reads the specified
696 /// register. If TargetRegisterInfo is passed, then it also checks if there
697 /// is a read of a super-register.
698 /// This does not count partial redefines of virtual registers as reads:
700 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
701 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
704 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
705 /// virtual register. Take into account that a partial define is a
706 /// read-modify-write operation.
707 bool readsVirtualRegister(unsigned Reg) const {
708 return readsWritesVirtualRegister(Reg).first;
711 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
712 /// indicating if this instruction reads or writes Reg. This also considers
714 /// If Ops is not null, all operand indices for Reg are added.
715 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
716 SmallVectorImpl<unsigned> *Ops = 0) const;
718 /// killsRegister - Return true if the MachineInstr kills the specified
719 /// register. If TargetRegisterInfo is passed, then it also checks if there is
720 /// a kill of a super-register.
721 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
722 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
725 /// definesRegister - Return true if the MachineInstr fully defines the
726 /// specified register. If TargetRegisterInfo is passed, then it also checks
727 /// if there is a def of a super-register.
728 /// NOTE: It's ignoring subreg indices on virtual registers.
729 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
730 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
733 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
734 /// or partially define) the specified register.
735 /// NOTE: It's ignoring subreg indices on virtual registers.
736 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
737 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
740 /// registerDefIsDead - Returns true if the register is dead in this machine
741 /// instruction. If TargetRegisterInfo is passed, then it also checks
742 /// if there is a dead def of a super-register.
743 bool registerDefIsDead(unsigned Reg,
744 const TargetRegisterInfo *TRI = NULL) const {
745 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
748 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
749 /// the specific register or -1 if it is not found. It further tightens
750 /// the search criteria to a use that kills the register if isKill is true.
751 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
752 const TargetRegisterInfo *TRI = NULL) const;
754 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
755 /// a pointer to the MachineOperand rather than an index.
756 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
757 const TargetRegisterInfo *TRI = NULL) {
758 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
759 return (Idx == -1) ? NULL : &getOperand(Idx);
762 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
763 /// the specified register or -1 if it is not found. If isDead is true, defs
764 /// that are not dead are skipped. If Overlap is true, then it also looks for
765 /// defs that merely overlap the specified register. If TargetRegisterInfo is
766 /// non-null, then it also checks if there is a def of a super-register.
767 /// This may also return a register mask operand when Overlap is true.
768 int findRegisterDefOperandIdx(unsigned Reg,
769 bool isDead = false, bool Overlap = false,
770 const TargetRegisterInfo *TRI = NULL) const;
772 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
773 /// a pointer to the MachineOperand rather than an index.
774 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
775 const TargetRegisterInfo *TRI = NULL) {
776 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
777 return (Idx == -1) ? NULL : &getOperand(Idx);
780 /// findFirstPredOperandIdx() - Find the index of the first operand in the
781 /// operand list that is used to represent the predicate. It returns -1 if
783 int findFirstPredOperandIdx() const;
785 /// findInlineAsmFlagIdx() - Find the index of the flag word operand that
786 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
787 /// getOperand(OpIdx) does not belong to an inline asm operand group.
789 /// If GroupNo is not NULL, it will receive the number of the operand group
790 /// containing OpIdx.
792 /// The flag operand is an immediate that can be decoded with methods like
793 /// InlineAsm::hasRegClassConstraint().
795 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const;
797 /// getRegClassConstraint - Compute the static register class constraint for
798 /// operand OpIdx. For normal instructions, this is derived from the
799 /// MCInstrDesc. For inline assembly it is derived from the flag words.
801 /// Returns NULL if the static register classs constraint cannot be
804 const TargetRegisterClass*
805 getRegClassConstraint(unsigned OpIdx,
806 const TargetInstrInfo *TII,
807 const TargetRegisterInfo *TRI) const;
809 /// tieOperands - Add a tie between the register operands at DefIdx and
810 /// UseIdx. The tie will cause the register allocator to ensure that the two
811 /// operands are assigned the same physical register.
813 /// Tied operands are managed automatically for explicit operands in the
814 /// MCInstrDesc. This method is for exceptional cases like inline asm.
815 void tieOperands(unsigned DefIdx, unsigned UseIdx);
817 /// findTiedOperandIdx - Given the index of a tied register operand, find the
818 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
819 /// index of the tied operand which must exist.
820 unsigned findTiedOperandIdx(unsigned OpIdx) const;
822 /// isRegTiedToUseOperand - Given the index of a register def operand,
823 /// check if the register def is tied to a source operand, due to either
824 /// two-address elimination or inline assembly constraints. Returns the
825 /// first tied use operand index by reference if UseOpIdx is not null.
826 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const {
827 const MachineOperand &MO = getOperand(DefOpIdx);
828 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
831 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
835 /// isRegTiedToDefOperand - Return true if the use operand of the specified
836 /// index is tied to an def operand. It also returns the def operand index by
837 /// reference if DefOpIdx is not null.
838 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const {
839 const MachineOperand &MO = getOperand(UseOpIdx);
840 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
843 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
847 /// clearKillInfo - Clears kill flags on all operands.
849 void clearKillInfo();
851 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
852 /// properly composing subreg indices where necessary.
853 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
854 const TargetRegisterInfo &RegInfo);
856 /// addRegisterKilled - We have determined MI kills a register. Look for the
857 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
858 /// add a implicit operand if it's not found. Returns true if the operand
859 /// exists / is added.
860 bool addRegisterKilled(unsigned IncomingReg,
861 const TargetRegisterInfo *RegInfo,
862 bool AddIfNotFound = false);
864 /// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is
865 /// provided, this includes super-register kills.
866 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
868 /// addRegisterDead - We have determined MI defined a register without a use.
869 /// Look for the operand that defines it and mark it as IsDead. If
870 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
871 /// true if the operand exists / is added.
872 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
873 bool AddIfNotFound = false);
875 /// addRegisterDefined - We have determined MI defines a register. Make sure
876 /// there is an operand defining Reg.
877 void addRegisterDefined(unsigned IncomingReg,
878 const TargetRegisterInfo *RegInfo = 0);
880 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
881 /// dead except those in the UsedRegs list.
883 /// On instructions with register mask operands, also add implicit-def
884 /// operands for all registers in UsedRegs.
885 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
886 const TargetRegisterInfo &TRI);
888 /// isSafeToMove - Return true if it is safe to move this instruction. If
889 /// SawStore is set to true, it means that there is a store (or call) between
890 /// the instruction's location and its intended destination.
891 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
892 bool &SawStore) const;
894 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
895 /// instruction which defined the specified register instead of copying it.
896 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
897 unsigned DstReg) const;
899 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
900 /// or volatile memory reference, or if the information describing the memory
901 /// reference is not available. Return false if it is known to have no
902 /// ordered or volatile memory references.
903 bool hasOrderedMemoryRef() const;
905 /// isInvariantLoad - Return true if this instruction is loading from a
906 /// location whose value is invariant across the function. For example,
907 /// loading a value from the constant pool or from the argument area of
908 /// a function if it does not change. This should only return true of *all*
909 /// loads the instruction does are invariant (if it does multiple loads).
910 bool isInvariantLoad(AliasAnalysis *AA) const;
912 /// isConstantValuePHI - If the specified instruction is a PHI that always
913 /// merges together the same virtual register, return the register, otherwise
915 unsigned isConstantValuePHI() const;
917 /// hasUnmodeledSideEffects - Return true if this instruction has side
918 /// effects that are not modeled by mayLoad / mayStore, etc.
919 /// For all instructions, the property is encoded in MCInstrDesc::Flags
920 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
921 /// INLINEASM instruction, in which case the side effect property is encoded
922 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
924 bool hasUnmodeledSideEffects() const;
926 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
928 bool allDefsAreDead() const;
930 /// copyImplicitOps - Copy implicit register operands from specified
931 /// instruction to this instruction.
932 void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI);
937 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
940 //===--------------------------------------------------------------------===//
941 // Accessors used to build up machine instructions.
943 /// Add the specified operand to the instruction. If it is an implicit
944 /// operand, it is added to the end of the operand list. If it is an
945 /// explicit operand it is added at the end of the explicit operand list
946 /// (before the first implicit operand).
948 /// MF must be the machine function that was used to allocate this
951 /// MachineInstrBuilder provides a more convenient interface for creating
952 /// instructions and adding operands.
953 void addOperand(MachineFunction &MF, const MachineOperand &Op);
955 /// Add an operand without providing an MF reference. This only works for
956 /// instructions that are inserted in a basic block.
958 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
960 void addOperand(const MachineOperand &Op);
962 /// setDesc - Replace the instruction descriptor (thus opcode) of
963 /// the current instruction with a new one.
965 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
967 /// setDebugLoc - Replace current source information with new such.
968 /// Avoid using this, the constructor argument is preferable.
970 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
972 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
973 /// fewer operand than it started with.
975 void RemoveOperand(unsigned i);
977 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
978 /// This function should be used only occasionally. The setMemRefs function
979 /// is the primary method for setting up a MachineInstr's MemRefs list.
980 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
982 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
983 /// list. This does not transfer ownership.
984 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
985 MemRefs = NewMemRefs;
986 NumMemRefs = NewMemRefsEnd - NewMemRefs;
990 /// getRegInfo - If this instruction is embedded into a MachineFunction,
991 /// return the MachineRegisterInfo object for the current function, otherwise
993 MachineRegisterInfo *getRegInfo();
995 /// untieRegOperand - Break any tie involving OpIdx.
996 void untieRegOperand(unsigned OpIdx) {
997 MachineOperand &MO = getOperand(OpIdx);
998 if (MO.isReg() && MO.isTied()) {
999 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1004 /// addImplicitDefUseOperands - Add all implicit def and use operands to
1005 /// this instruction.
1006 void addImplicitDefUseOperands(MachineFunction &MF);
1008 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
1009 /// this instruction from their respective use lists. This requires that the
1010 /// operands already be on their use lists.
1011 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1013 /// AddRegOperandsToUseLists - Add all of the register operands in
1014 /// this instruction from their respective use lists. This requires that the
1015 /// operands not be on their use lists yet.
1016 void AddRegOperandsToUseLists(MachineRegisterInfo&);
1018 /// hasPropertyInBundle - Slow path for hasProperty when we're dealing with a
1020 bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
1023 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
1024 /// MachineInstr* by *value* of the instruction rather than by pointer value.
1025 /// The hashing and equality testing functions ignore definitions so this is
1026 /// useful for CSE, etc.
1027 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1028 static inline MachineInstr *getEmptyKey() {
1032 static inline MachineInstr *getTombstoneKey() {
1033 return reinterpret_cast<MachineInstr*>(-1);
1036 static unsigned getHashValue(const MachineInstr* const &MI);
1038 static bool isEqual(const MachineInstr* const &LHS,
1039 const MachineInstr* const &RHS) {
1040 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1041 LHS == getEmptyKey() || LHS == getTombstoneKey())
1043 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
1047 //===----------------------------------------------------------------------===//
1048 // Debugging Support
1050 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1055 } // End llvm namespace