1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/ADT/alist.h"
20 #include "llvm/CodeGen/MachineOperand.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
26 class TargetInstrDesc;
27 class TargetInstrInfo;
28 class TargetRegisterInfo;
29 class MachineFunction;
31 //===----------------------------------------------------------------------===//
32 /// MachineInstr - Representation of each machine instruction.
35 const TargetInstrDesc *TID; // Instruction descriptor.
36 unsigned short NumImplicitOps; // Number of implicit operands (which
37 // are determined at construction time).
39 std::vector<MachineOperand> Operands; // the operands
40 alist<MachineMemOperand> MemOperands; // information on memory references
41 MachineBasicBlock *Parent; // Pointer to the owning basic block.
43 // OperandComplete - Return true if it's illegal to add a new operand
44 bool OperandsComplete() const;
46 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
47 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
49 // Intrusive list support
50 friend struct alist_traits<MachineInstr>;
51 friend struct alist_traits<MachineBasicBlock>;
52 void setParent(MachineBasicBlock *P) { Parent = P; }
54 /// MachineInstr ctor - This constructor creates a copy of the given
55 /// MachineInstr in the given MachineFunction.
56 MachineInstr(MachineFunction &, const MachineInstr &);
58 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
59 /// TID NULL and no operands.
62 /// MachineInstr ctor - This constructor create a MachineInstr and add the
63 /// implicit operands. It reserves space for number of operands specified by
65 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
67 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
68 /// the MachineInstr is created and added to the end of the specified basic
71 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
75 // MachineInstrs are pool-allocated and owned by MachineFunction.
76 friend class MachineFunction;
79 const MachineBasicBlock* getParent() const { return Parent; }
80 MachineBasicBlock* getParent() { return Parent; }
82 /// getDesc - Returns the target instruction descriptor of this
84 const TargetInstrDesc &getDesc() const { return *TID; }
86 /// getOpcode - Returns the opcode of this MachineInstr.
88 int getOpcode() const;
90 /// Access to explicit operands of the instruction.
92 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
94 const MachineOperand& getOperand(unsigned i) const {
95 assert(i < getNumOperands() && "getOperand() out of range!");
98 MachineOperand& getOperand(unsigned i) {
99 assert(i < getNumOperands() && "getOperand() out of range!");
103 /// getNumExplicitOperands - Returns the number of non-implicit operands.
105 unsigned getNumExplicitOperands() const;
107 /// Access to memory operands of the instruction
108 alist<MachineMemOperand>::iterator memoperands_begin()
109 { return MemOperands.begin(); }
110 alist<MachineMemOperand>::iterator memoperands_end()
111 { return MemOperands.end(); }
112 alist<MachineMemOperand>::const_iterator memoperands_begin() const
113 { return MemOperands.begin(); }
114 alist<MachineMemOperand>::const_iterator memoperands_end() const
115 { return MemOperands.end(); }
116 bool memoperands_empty() const { return MemOperands.empty(); }
118 /// hasOneMemOperand - Return true if this instruction has exactly one
119 /// MachineMemOperand.
120 bool hasOneMemOperand() const {
121 return !memoperands_empty() &&
122 next(memoperands_begin()) == memoperands_end();
125 /// isIdenticalTo - Return true if this instruction is identical to (same
126 /// opcode and same operands as) the specified instruction.
127 bool isIdenticalTo(const MachineInstr *Other) const {
128 if (Other->getOpcode() != getOpcode() ||
129 Other->getNumOperands() != getNumOperands())
131 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
132 if (!getOperand(i).isIdenticalTo(Other->getOperand(i)))
137 /// removeFromParent - This method unlinks 'this' from the containing basic
138 /// block, and returns it, but does not delete it.
139 MachineInstr *removeFromParent();
141 /// eraseFromParent - This method unlinks 'this' from the containing basic
142 /// block and deletes it.
143 void eraseFromParent();
145 /// isLabel - Returns true if the MachineInstr represents a label.
147 bool isLabel() const;
149 /// isDebugLabel - Returns true if the MachineInstr represents a debug label.
151 bool isDebugLabel() const;
153 /// readsRegister - Return true if the MachineInstr reads the specified
154 /// register. If TargetRegisterInfo is passed, then it also checks if there
155 /// is a read of a super-register.
156 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
157 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
160 /// killsRegister - Return true if the MachineInstr kills the specified
161 /// register. If TargetRegisterInfo is passed, then it also checks if there is
162 /// a kill of a super-register.
163 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
164 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
167 /// modifiesRegister - Return true if the MachineInstr modifies the
168 /// specified register. If TargetRegisterInfo is passed, then it also checks
169 /// if there is a def of a super-register.
170 bool modifiesRegister(unsigned Reg,
171 const TargetRegisterInfo *TRI = NULL) const {
172 return findRegisterDefOperandIdx(Reg, false, TRI) != -1;
175 /// registerDefIsDead - Returns true if the register is dead in this machine
176 /// instruction. If TargetRegisterInfo is passed, then it also checks
177 /// if there is a dead def of a super-register.
178 bool registerDefIsDead(unsigned Reg,
179 const TargetRegisterInfo *TRI = NULL) const {
180 return findRegisterDefOperandIdx(Reg, true, TRI) != -1;
183 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
184 /// the specific register or -1 if it is not found. It further tightening
185 /// the search criteria to a use that kills the register if isKill is true.
186 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
187 const TargetRegisterInfo *TRI = NULL) const;
189 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
190 /// a pointer to the MachineOperand rather than an index.
191 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
192 const TargetRegisterInfo *TRI = NULL) {
193 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
194 return (Idx == -1) ? NULL : &getOperand(Idx);
197 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
198 /// the specified register or -1 if it is not found. If isDead is true, defs
199 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
200 /// also checks if there is a def of a super-register.
201 int findRegisterDefOperandIdx(unsigned Reg, bool isDead = false,
202 const TargetRegisterInfo *TRI = NULL) const;
204 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
205 /// a pointer to the MachineOperand rather than an index.
206 MachineOperand *findRegisterDefOperand(unsigned Reg,bool isDead = false,
207 const TargetRegisterInfo *TRI = NULL) {
208 int Idx = findRegisterDefOperandIdx(Reg, isDead, TRI);
209 return (Idx == -1) ? NULL : &getOperand(Idx);
212 /// findFirstPredOperandIdx() - Find the index of the first operand in the
213 /// operand list that is used to represent the predicate. It returns -1 if
215 int findFirstPredOperandIdx() const;
217 /// isRegReDefinedByTwoAddr - Given the defined register and the operand index,
218 /// check if the register def is a re-definition due to two addr elimination.
219 bool isRegReDefinedByTwoAddr(unsigned Reg, unsigned DefIdx) const;
221 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
223 void copyKillDeadInfo(const MachineInstr *MI);
225 /// copyPredicates - Copies predicate operand(s) from MI.
226 void copyPredicates(const MachineInstr *MI);
228 /// addRegisterKilled - We have determined MI kills a register. Look for the
229 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
230 /// add a implicit operand if it's not found. Returns true if the operand
231 /// exists / is added.
232 bool addRegisterKilled(unsigned IncomingReg,
233 const TargetRegisterInfo *RegInfo,
234 bool AddIfNotFound = false);
236 /// addRegisterDead - We have determined MI defined a register without a use.
237 /// Look for the operand that defines it and mark it as IsDead. If
238 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
239 /// true if the operand exists / is added.
240 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
241 bool AddIfNotFound = false);
243 /// isSafeToMove - Return true if it is safe to move this instruction. If
244 /// SawStore is set to true, it means that there is a store (or call) between
245 /// the instruction's location and its intended destination.
246 bool isSafeToMove(const TargetInstrInfo *TII, bool &SawStore);
251 void print(std::ostream *OS, const TargetMachine *TM) const {
252 if (OS) print(*OS, TM);
254 void print(std::ostream &OS, const TargetMachine *TM = 0) const;
255 void print(std::ostream *OS) const { if (OS) print(*OS); }
258 //===--------------------------------------------------------------------===//
259 // Accessors used to build up machine instructions.
261 /// addOperand - Add the specified operand to the instruction. If it is an
262 /// implicit operand, it is added to the end of the operand list. If it is
263 /// an explicit operand it is added at the end of the explicit operand list
264 /// (before the first implicit operand).
265 void addOperand(const MachineOperand &Op);
267 /// setDesc - Replace the instruction descriptor (thus opcode) of
268 /// the current instruction with a new one.
270 void setDesc(const TargetInstrDesc &tid) { TID = &tid; }
272 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
273 /// fewer operand than it started with.
275 void RemoveOperand(unsigned i);
277 /// addMemOperand - Add a MachineMemOperand to the machine instruction,
278 /// referencing arbitrary storage.
279 void addMemOperand(MachineFunction &MF,
280 const MachineMemOperand &MO);
282 /// clearMemOperands - Erase all of this MachineInstr's MachineMemOperands.
283 void clearMemOperands(MachineFunction &MF);
286 /// getRegInfo - If this instruction is embedded into a MachineFunction,
287 /// return the MachineRegisterInfo object for the current function, otherwise
289 MachineRegisterInfo *getRegInfo();
291 /// addImplicitDefUseOperands - Add all implicit def and use operands to
292 /// this instruction.
293 void addImplicitDefUseOperands();
295 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
296 /// this instruction from their respective use lists. This requires that the
297 /// operands already be on their use lists.
298 void RemoveRegOperandsFromUseLists();
300 /// AddRegOperandsToUseLists - Add all of the register operands in
301 /// this instruction from their respective use lists. This requires that the
302 /// operands not be on their use lists yet.
303 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
306 //===----------------------------------------------------------------------===//
309 inline std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI) {
314 } // End llvm namespace