1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/Target/TargetOpcodes.h"
22 #include "llvm/ADT/ilist.h"
23 #include "llvm/ADT/ilist_node.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/DenseMapInfo.h"
27 #include "llvm/Support/DebugLoc.h"
32 template <typename T> class SmallVectorImpl;
34 class TargetInstrInfo;
35 class TargetRegisterClass;
36 class TargetRegisterInfo;
37 class MachineFunction;
38 class MachineMemOperand;
40 //===----------------------------------------------------------------------===//
41 /// MachineInstr - Representation of each machine instruction.
43 class MachineInstr : public ilist_node<MachineInstr> {
45 typedef MachineMemOperand **mmo_iterator;
47 /// Flags to specify different kinds of comments to output in
48 /// assembly code. These flags carry semantic information not
49 /// otherwise easily derivable from the IR text.
57 FrameSetup = 1 << 0, // Instruction is used as a part of
58 // function frame setup code.
59 InsideBundle = 1 << 1 // Instruction is inside a bundle (not
60 // the first MI in a bundle)
63 const MCInstrDesc *MCID; // Instruction descriptor.
65 uint8_t Flags; // Various bits of additional
66 // information about machine
69 uint8_t AsmPrinterFlags; // Various bits of information used by
70 // the AsmPrinter to emit helpful
71 // comments. This is *not* semantic
72 // information. Do not use this for
73 // anything other than to convey comment
74 // information to AsmPrinter.
76 std::vector<MachineOperand> Operands; // the operands
77 mmo_iterator MemRefs; // information on memory references
78 mmo_iterator MemRefsEnd;
79 MachineBasicBlock *Parent; // Pointer to the owning basic block.
80 DebugLoc debugLoc; // Source line information.
82 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
83 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
85 // Intrusive list support
86 friend struct ilist_traits<MachineInstr>;
87 friend struct ilist_traits<MachineBasicBlock>;
88 void setParent(MachineBasicBlock *P) { Parent = P; }
90 /// MachineInstr ctor - This constructor creates a copy of the given
91 /// MachineInstr in the given MachineFunction.
92 MachineInstr(MachineFunction &, const MachineInstr &);
94 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
95 /// MCID NULL and no operands.
98 // The next two constructors have DebugLoc and non-DebugLoc versions;
99 // over time, the non-DebugLoc versions should be phased out and eventually
102 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
103 /// implicit operands. It reserves space for the number of operands specified
104 /// by the MCInstrDesc. The version with a DebugLoc should be preferred.
105 explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
107 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
108 /// the MachineInstr is created and added to the end of the specified basic
109 /// block. The version with a DebugLoc should be preferred.
110 MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
112 /// MachineInstr ctor - This constructor create a MachineInstr and add the
113 /// implicit operands. It reserves space for number of operands specified by
114 /// MCInstrDesc. An explicit DebugLoc is supplied.
115 explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
118 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
119 /// the MachineInstr is created and added to the end of the specified basic
121 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
122 const MCInstrDesc &MCID);
126 // MachineInstrs are pool-allocated and owned by MachineFunction.
127 friend class MachineFunction;
130 const MachineBasicBlock* getParent() const { return Parent; }
131 MachineBasicBlock* getParent() { return Parent; }
133 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
135 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
137 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
139 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
141 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
143 bool getAsmPrinterFlag(CommentFlag Flag) const {
144 return AsmPrinterFlags & Flag;
147 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
149 void setAsmPrinterFlag(CommentFlag Flag) {
150 AsmPrinterFlags |= (uint8_t)Flag;
153 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
155 void clearAsmPrinterFlag(CommentFlag Flag) {
156 AsmPrinterFlags &= ~Flag;
159 /// getFlags - Return the MI flags bitvector.
160 uint8_t getFlags() const {
164 /// getFlag - Return whether an MI flag is set.
165 bool getFlag(MIFlag Flag) const {
169 /// setFlag - Set a MI flag.
170 void setFlag(MIFlag Flag) {
171 Flags |= (uint8_t)Flag;
174 void setFlags(unsigned flags) {
178 /// isInsideBundle - Return true if MI is in a bundle (but not the first MI
181 /// A bundle looks like this before it's finalized:
193 /// In this case, the first MI starts a bundle but is not inside a bundle, the
194 /// next 2 MIs are considered "inside" the bundle.
196 /// After a bundle is finalized, it looks like this:
212 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
213 /// a bundle, but the next three MIs are.
214 bool isInsideBundle() const {
215 return getFlag(InsideBundle);
218 /// getDebugLoc - Returns the debug location id of this MachineInstr.
220 DebugLoc getDebugLoc() const { return debugLoc; }
222 /// emitError - Emit an error referring to the source location of this
223 /// instruction. This should only be used for inline assembly that is somehow
224 /// impossible to compile. Other errors should have been handled much
227 /// If this method returns, the caller should try to recover from the error.
229 void emitError(StringRef Msg) const;
231 /// getDesc - Returns the target instruction descriptor of this
233 const MCInstrDesc &getDesc() const { return *MCID; }
235 /// getOpcode - Returns the opcode of this MachineInstr.
237 int getOpcode() const { return MCID->Opcode; }
239 /// Access to explicit operands of the instruction.
241 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
243 const MachineOperand& getOperand(unsigned i) const {
244 assert(i < getNumOperands() && "getOperand() out of range!");
247 MachineOperand& getOperand(unsigned i) {
248 assert(i < getNumOperands() && "getOperand() out of range!");
252 /// getNumExplicitOperands - Returns the number of non-implicit operands.
254 unsigned getNumExplicitOperands() const;
256 /// iterator/begin/end - Iterate over all operands of a machine instruction.
257 typedef std::vector<MachineOperand>::iterator mop_iterator;
258 typedef std::vector<MachineOperand>::const_iterator const_mop_iterator;
260 mop_iterator operands_begin() { return Operands.begin(); }
261 mop_iterator operands_end() { return Operands.end(); }
263 const_mop_iterator operands_begin() const { return Operands.begin(); }
264 const_mop_iterator operands_end() const { return Operands.end(); }
266 /// Access to memory operands of the instruction
267 mmo_iterator memoperands_begin() const { return MemRefs; }
268 mmo_iterator memoperands_end() const { return MemRefsEnd; }
269 bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
271 /// hasOneMemOperand - Return true if this instruction has exactly one
272 /// MachineMemOperand.
273 bool hasOneMemOperand() const {
274 return MemRefsEnd - MemRefs == 1;
277 /// API for querying MachineInstr properties. These are bundle aware.
279 bool hasProperty(unsigned short Flag) const;
281 bool isTerminator() const {
282 return hasProperty(MCID::Terminator);
286 CheckDefs, // Check all operands for equality
287 CheckKillDead, // Check all operands including kill / dead markers
288 IgnoreDefs, // Ignore all definitions
289 IgnoreVRegDefs // Ignore virtual register definitions
292 /// isIdenticalTo - Return true if this instruction is identical to (same
293 /// opcode and same operands as) the specified instruction.
294 bool isIdenticalTo(const MachineInstr *Other,
295 MICheckType Check = CheckDefs) const;
297 /// removeFromParent - This method unlinks 'this' from the containing basic
298 /// block, and returns it, but does not delete it.
299 MachineInstr *removeFromParent();
301 /// eraseFromParent - This method unlinks 'this' from the containing basic
302 /// block and deletes it.
303 void eraseFromParent();
305 /// isLabel - Returns true if the MachineInstr represents a label.
307 bool isLabel() const {
308 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
309 getOpcode() == TargetOpcode::EH_LABEL ||
310 getOpcode() == TargetOpcode::GC_LABEL;
313 bool isPrologLabel() const {
314 return getOpcode() == TargetOpcode::PROLOG_LABEL;
316 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
317 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
318 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
320 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
321 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
322 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
323 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
324 bool isStackAligningInlineAsm() const;
325 bool isInsertSubreg() const {
326 return getOpcode() == TargetOpcode::INSERT_SUBREG;
328 bool isSubregToReg() const {
329 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
331 bool isRegSequence() const {
332 return getOpcode() == TargetOpcode::REG_SEQUENCE;
334 bool isCopy() const {
335 return getOpcode() == TargetOpcode::COPY;
337 bool isFullCopy() const {
338 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
341 /// isCopyLike - Return true if the instruction behaves like a copy.
342 /// This does not include native copy instructions.
343 bool isCopyLike() const {
344 return isCopy() || isSubregToReg();
347 /// isIdentityCopy - Return true is the instruction is an identity copy.
348 bool isIdentityCopy() const {
349 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
350 getOperand(0).getSubReg() == getOperand(1).getSubReg();
353 /// readsRegister - Return true if the MachineInstr reads the specified
354 /// register. If TargetRegisterInfo is passed, then it also checks if there
355 /// is a read of a super-register.
356 /// This does not count partial redefines of virtual registers as reads:
358 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
359 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
362 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
363 /// virtual register. Take into account that a partial define is a
364 /// read-modify-write operation.
365 bool readsVirtualRegister(unsigned Reg) const {
366 return readsWritesVirtualRegister(Reg).first;
369 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
370 /// indicating if this instruction reads or writes Reg. This also considers
372 /// If Ops is not null, all operand indices for Reg are added.
373 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
374 SmallVectorImpl<unsigned> *Ops = 0) const;
376 /// killsRegister - Return true if the MachineInstr kills the specified
377 /// register. If TargetRegisterInfo is passed, then it also checks if there is
378 /// a kill of a super-register.
379 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
380 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
383 /// definesRegister - Return true if the MachineInstr fully defines the
384 /// specified register. If TargetRegisterInfo is passed, then it also checks
385 /// if there is a def of a super-register.
386 /// NOTE: It's ignoring subreg indices on virtual registers.
387 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
388 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
391 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
392 /// or partially define) the specified register.
393 /// NOTE: It's ignoring subreg indices on virtual registers.
394 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
395 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
398 /// registerDefIsDead - Returns true if the register is dead in this machine
399 /// instruction. If TargetRegisterInfo is passed, then it also checks
400 /// if there is a dead def of a super-register.
401 bool registerDefIsDead(unsigned Reg,
402 const TargetRegisterInfo *TRI = NULL) const {
403 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
406 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
407 /// the specific register or -1 if it is not found. It further tightens
408 /// the search criteria to a use that kills the register if isKill is true.
409 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
410 const TargetRegisterInfo *TRI = NULL) const;
412 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
413 /// a pointer to the MachineOperand rather than an index.
414 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
415 const TargetRegisterInfo *TRI = NULL) {
416 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
417 return (Idx == -1) ? NULL : &getOperand(Idx);
420 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
421 /// the specified register or -1 if it is not found. If isDead is true, defs
422 /// that are not dead are skipped. If Overlap is true, then it also looks for
423 /// defs that merely overlap the specified register. If TargetRegisterInfo is
424 /// non-null, then it also checks if there is a def of a super-register.
425 int findRegisterDefOperandIdx(unsigned Reg,
426 bool isDead = false, bool Overlap = false,
427 const TargetRegisterInfo *TRI = NULL) const;
429 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
430 /// a pointer to the MachineOperand rather than an index.
431 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
432 const TargetRegisterInfo *TRI = NULL) {
433 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
434 return (Idx == -1) ? NULL : &getOperand(Idx);
437 /// findFirstPredOperandIdx() - Find the index of the first operand in the
438 /// operand list that is used to represent the predicate. It returns -1 if
440 int findFirstPredOperandIdx() const;
442 /// findInlineAsmFlagIdx() - Find the index of the flag word operand that
443 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
444 /// getOperand(OpIdx) does not belong to an inline asm operand group.
446 /// If GroupNo is not NULL, it will receive the number of the operand group
447 /// containing OpIdx.
449 /// The flag operand is an immediate that can be decoded with methods like
450 /// InlineAsm::hasRegClassConstraint().
452 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = 0) const;
454 /// getRegClassConstraint - Compute the static register class constraint for
455 /// operand OpIdx. For normal instructions, this is derived from the
456 /// MCInstrDesc. For inline assembly it is derived from the flag words.
458 /// Returns NULL if the static register classs constraint cannot be
461 const TargetRegisterClass*
462 getRegClassConstraint(unsigned OpIdx,
463 const TargetInstrInfo *TII,
464 const TargetRegisterInfo *TRI) const;
466 /// isRegTiedToUseOperand - Given the index of a register def operand,
467 /// check if the register def is tied to a source operand, due to either
468 /// two-address elimination or inline assembly constraints. Returns the
469 /// first tied use operand index by reference is UseOpIdx is not null.
470 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
472 /// isRegTiedToDefOperand - Return true if the use operand of the specified
473 /// index is tied to an def operand. It also returns the def operand index by
474 /// reference if DefOpIdx is not null.
475 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
477 /// clearKillInfo - Clears kill flags on all operands.
479 void clearKillInfo();
481 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
483 void copyKillDeadInfo(const MachineInstr *MI);
485 /// copyPredicates - Copies predicate operand(s) from MI.
486 void copyPredicates(const MachineInstr *MI);
488 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
489 /// properly composing subreg indices where necessary.
490 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
491 const TargetRegisterInfo &RegInfo);
493 /// addRegisterKilled - We have determined MI kills a register. Look for the
494 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
495 /// add a implicit operand if it's not found. Returns true if the operand
496 /// exists / is added.
497 bool addRegisterKilled(unsigned IncomingReg,
498 const TargetRegisterInfo *RegInfo,
499 bool AddIfNotFound = false);
501 /// addRegisterDead - We have determined MI defined a register without a use.
502 /// Look for the operand that defines it and mark it as IsDead. If
503 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
504 /// true if the operand exists / is added.
505 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
506 bool AddIfNotFound = false);
508 /// addRegisterDefined - We have determined MI defines a register. Make sure
509 /// there is an operand defining Reg.
510 void addRegisterDefined(unsigned IncomingReg,
511 const TargetRegisterInfo *RegInfo = 0);
513 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
514 /// dead except those in the UsedRegs list.
515 void setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
516 const TargetRegisterInfo &TRI);
518 /// isSafeToMove - Return true if it is safe to move this instruction. If
519 /// SawStore is set to true, it means that there is a store (or call) between
520 /// the instruction's location and its intended destination.
521 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
522 bool &SawStore) const;
524 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
525 /// instruction which defined the specified register instead of copying it.
526 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
527 unsigned DstReg) const;
529 /// hasVolatileMemoryRef - Return true if this instruction may have a
530 /// volatile memory reference, or if the information describing the
531 /// memory reference is not available. Return false if it is known to
532 /// have no volatile memory references.
533 bool hasVolatileMemoryRef() const;
535 /// isInvariantLoad - Return true if this instruction is loading from a
536 /// location whose value is invariant across the function. For example,
537 /// loading a value from the constant pool or from the argument area of
538 /// a function if it does not change. This should only return true of *all*
539 /// loads the instruction does are invariant (if it does multiple loads).
540 bool isInvariantLoad(AliasAnalysis *AA) const;
542 /// isConstantValuePHI - If the specified instruction is a PHI that always
543 /// merges together the same virtual register, return the register, otherwise
545 unsigned isConstantValuePHI() const;
547 /// hasUnmodeledSideEffects - Return true if this instruction has side
548 /// effects that are not modeled by mayLoad / mayStore, etc.
549 /// For all instructions, the property is encoded in MCInstrDesc::Flags
550 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
551 /// INLINEASM instruction, in which case the side effect property is encoded
552 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
554 bool hasUnmodeledSideEffects() const;
556 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
558 bool allDefsAreDead() const;
560 /// copyImplicitOps - Copy implicit register operands from specified
561 /// instruction to this instruction.
562 void copyImplicitOps(const MachineInstr *MI);
567 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
570 //===--------------------------------------------------------------------===//
571 // Accessors used to build up machine instructions.
573 /// addOperand - Add the specified operand to the instruction. If it is an
574 /// implicit operand, it is added to the end of the operand list. If it is
575 /// an explicit operand it is added at the end of the explicit operand list
576 /// (before the first implicit operand).
577 void addOperand(const MachineOperand &Op);
579 /// setDesc - Replace the instruction descriptor (thus opcode) of
580 /// the current instruction with a new one.
582 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
584 /// setDebugLoc - Replace current source information with new such.
585 /// Avoid using this, the constructor argument is preferable.
587 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
589 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
590 /// fewer operand than it started with.
592 void RemoveOperand(unsigned i);
594 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
595 /// This function should be used only occasionally. The setMemRefs function
596 /// is the primary method for setting up a MachineInstr's MemRefs list.
597 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
599 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
600 /// list. This does not transfer ownership.
601 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
602 MemRefs = NewMemRefs;
603 MemRefsEnd = NewMemRefsEnd;
607 /// getRegInfo - If this instruction is embedded into a MachineFunction,
608 /// return the MachineRegisterInfo object for the current function, otherwise
610 MachineRegisterInfo *getRegInfo();
612 /// addImplicitDefUseOperands - Add all implicit def and use operands to
613 /// this instruction.
614 void addImplicitDefUseOperands();
616 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
617 /// this instruction from their respective use lists. This requires that the
618 /// operands already be on their use lists.
619 void RemoveRegOperandsFromUseLists();
621 /// AddRegOperandsToUseLists - Add all of the register operands in
622 /// this instruction from their respective use lists. This requires that the
623 /// operands not be on their use lists yet.
624 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
627 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
628 /// MachineInstr* by *value* of the instruction rather than by pointer value.
629 /// The hashing and equality testing functions ignore definitions so this is
630 /// useful for CSE, etc.
631 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
632 static inline MachineInstr *getEmptyKey() {
636 static inline MachineInstr *getTombstoneKey() {
637 return reinterpret_cast<MachineInstr*>(-1);
640 static unsigned getHashValue(const MachineInstr* const &MI);
642 static bool isEqual(const MachineInstr* const &LHS,
643 const MachineInstr* const &RHS) {
644 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
645 LHS == getEmptyKey() || LHS == getTombstoneKey())
647 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
651 //===----------------------------------------------------------------------===//
654 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
659 } // End llvm namespace