1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/CodeGen/MachineOperand.h"
20 #include "llvm/Target/TargetInstrDesc.h"
21 #include "llvm/Target/TargetOpcodes.h"
22 #include "llvm/ADT/ilist.h"
23 #include "llvm/ADT/ilist_node.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/DenseMapInfo.h"
26 #include "llvm/Support/DebugLoc.h"
31 template <typename T> class SmallVectorImpl;
33 class TargetInstrDesc;
34 class TargetInstrInfo;
35 class TargetRegisterInfo;
36 class MachineFunction;
37 class MachineMemOperand;
39 //===----------------------------------------------------------------------===//
40 /// MachineInstr - Representation of each machine instruction.
42 class MachineInstr : public ilist_node<MachineInstr> {
44 typedef MachineMemOperand **mmo_iterator;
46 /// Flags to specify different kinds of comments to output in
47 /// assembly code. These flags carry semantic information not
48 /// otherwise easily derivable from the IR text.
55 const TargetInstrDesc *TID; // Instruction descriptor.
56 unsigned short NumImplicitOps; // Number of implicit operands (which
57 // are determined at construction time).
59 unsigned short AsmPrinterFlags; // Various bits of information used by
60 // the AsmPrinter to emit helpful
61 // comments. This is *not* semantic
62 // information. Do not use this for
63 // anything other than to convey comment
64 // information to AsmPrinter.
66 std::vector<MachineOperand> Operands; // the operands
67 mmo_iterator MemRefs; // information on memory references
68 mmo_iterator MemRefsEnd;
69 MachineBasicBlock *Parent; // Pointer to the owning basic block.
70 DebugLoc debugLoc; // Source line information.
72 // OperandComplete - Return true if it's illegal to add a new operand
73 bool OperandsComplete() const;
75 MachineInstr(const MachineInstr&); // DO NOT IMPLEMENT
76 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
78 // Intrusive list support
79 friend struct ilist_traits<MachineInstr>;
80 friend struct ilist_traits<MachineBasicBlock>;
81 void setParent(MachineBasicBlock *P) { Parent = P; }
83 /// MachineInstr ctor - This constructor creates a copy of the given
84 /// MachineInstr in the given MachineFunction.
85 MachineInstr(MachineFunction &, const MachineInstr &);
87 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
88 /// TID NULL and no operands.
91 // The next two constructors have DebugLoc and non-DebugLoc versions;
92 // over time, the non-DebugLoc versions should be phased out and eventually
95 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
96 /// implicit operands. It reserves space for the number of operands specified
97 /// by the TargetInstrDesc. The version with a DebugLoc should be preferred.
98 explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
100 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
101 /// the MachineInstr is created and added to the end of the specified basic
102 /// block. The version with a DebugLoc should be preferred.
103 MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
105 /// MachineInstr ctor - This constructor create a MachineInstr and add the
106 /// implicit operands. It reserves space for number of operands specified by
107 /// TargetInstrDesc. An explicit DebugLoc is supplied.
108 explicit MachineInstr(const TargetInstrDesc &TID, const DebugLoc dl,
111 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
112 /// the MachineInstr is created and added to the end of the specified basic
114 MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl,
115 const TargetInstrDesc &TID);
119 // MachineInstrs are pool-allocated and owned by MachineFunction.
120 friend class MachineFunction;
123 const MachineBasicBlock* getParent() const { return Parent; }
124 MachineBasicBlock* getParent() { return Parent; }
126 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
128 unsigned short getAsmPrinterFlags() const { return AsmPrinterFlags; }
130 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
132 bool getAsmPrinterFlag(CommentFlag Flag) const {
133 return AsmPrinterFlags & Flag;
136 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
138 void setAsmPrinterFlag(CommentFlag Flag) {
139 AsmPrinterFlags |= (unsigned short)Flag;
142 /// getDebugLoc - Returns the debug location id of this MachineInstr.
144 DebugLoc getDebugLoc() const { return debugLoc; }
146 /// getDesc - Returns the target instruction descriptor of this
148 const TargetInstrDesc &getDesc() const { return *TID; }
150 /// getOpcode - Returns the opcode of this MachineInstr.
152 int getOpcode() const { return TID->Opcode; }
154 /// Access to explicit operands of the instruction.
156 unsigned getNumOperands() const { return (unsigned)Operands.size(); }
158 const MachineOperand& getOperand(unsigned i) const {
159 assert(i < getNumOperands() && "getOperand() out of range!");
162 MachineOperand& getOperand(unsigned i) {
163 assert(i < getNumOperands() && "getOperand() out of range!");
167 /// getNumExplicitOperands - Returns the number of non-implicit operands.
169 unsigned getNumExplicitOperands() const;
171 /// Access to memory operands of the instruction
172 mmo_iterator memoperands_begin() const { return MemRefs; }
173 mmo_iterator memoperands_end() const { return MemRefsEnd; }
174 bool memoperands_empty() const { return MemRefsEnd == MemRefs; }
176 /// hasOneMemOperand - Return true if this instruction has exactly one
177 /// MachineMemOperand.
178 bool hasOneMemOperand() const {
179 return MemRefsEnd - MemRefs == 1;
183 CheckDefs, // Check all operands for equality
184 IgnoreDefs, // Ignore all definitions
185 IgnoreVRegDefs // Ignore virtual register definitions
188 /// isIdenticalTo - Return true if this instruction is identical to (same
189 /// opcode and same operands as) the specified instruction.
190 bool isIdenticalTo(const MachineInstr *Other,
191 MICheckType Check = CheckDefs) const;
193 /// removeFromParent - This method unlinks 'this' from the containing basic
194 /// block, and returns it, but does not delete it.
195 MachineInstr *removeFromParent();
197 /// eraseFromParent - This method unlinks 'this' from the containing basic
198 /// block and deletes it.
199 void eraseFromParent();
201 /// isLabel - Returns true if the MachineInstr represents a label.
203 bool isLabel() const {
204 return getOpcode() == TargetOpcode::DBG_LABEL ||
205 getOpcode() == TargetOpcode::EH_LABEL ||
206 getOpcode() == TargetOpcode::GC_LABEL;
209 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
210 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
211 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
212 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
214 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
215 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
216 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
217 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
218 bool isExtractSubreg() const {
219 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
221 bool isInsertSubreg() const {
222 return getOpcode() == TargetOpcode::INSERT_SUBREG;
224 bool isSubregToReg() const {
225 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
227 bool isRegSequence() const {
228 return getOpcode() == TargetOpcode::REG_SEQUENCE;
230 bool isCopy() const {
231 return getOpcode() == TargetOpcode::COPY;
234 /// isCopyLike - Return true if the instruction behaves like a copy.
235 /// This does not include native copy instructions.
236 bool isCopyLike() const {
237 return isCopy() || isSubregToReg() || isExtractSubreg() || isInsertSubreg();
240 /// readsRegister - Return true if the MachineInstr reads the specified
241 /// register. If TargetRegisterInfo is passed, then it also checks if there
242 /// is a read of a super-register.
243 /// This does not count partial redefines of virtual registers as reads:
245 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
246 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
249 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
250 /// virtual register. Take into account that a partial define is a
251 /// read-modify-write operation.
252 bool readsVirtualRegister(unsigned Reg) const {
253 return readsWritesVirtualRegister(Reg).first;
256 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
257 /// indicating if this instruction reads or writes Reg. This also considers
259 /// If Ops is not null, all operand indices for Reg are added.
260 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
261 SmallVectorImpl<unsigned> *Ops = 0) const;
263 /// killsRegister - Return true if the MachineInstr kills the specified
264 /// register. If TargetRegisterInfo is passed, then it also checks if there is
265 /// a kill of a super-register.
266 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
267 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
270 /// definesRegister - Return true if the MachineInstr fully defines the
271 /// specified register. If TargetRegisterInfo is passed, then it also checks
272 /// if there is a def of a super-register.
273 /// NOTE: It's ignoring subreg indices on virtual registers.
274 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
275 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
278 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
279 /// or partially define) the specified register.
280 /// NOTE: It's ignoring subreg indices on virtual registers.
281 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
282 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
285 /// registerDefIsDead - Returns true if the register is dead in this machine
286 /// instruction. If TargetRegisterInfo is passed, then it also checks
287 /// if there is a dead def of a super-register.
288 bool registerDefIsDead(unsigned Reg,
289 const TargetRegisterInfo *TRI = NULL) const {
290 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
293 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
294 /// the specific register or -1 if it is not found. It further tightens
295 /// the search criteria to a use that kills the register if isKill is true.
296 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
297 const TargetRegisterInfo *TRI = NULL) const;
299 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
300 /// a pointer to the MachineOperand rather than an index.
301 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
302 const TargetRegisterInfo *TRI = NULL) {
303 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
304 return (Idx == -1) ? NULL : &getOperand(Idx);
307 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
308 /// the specified register or -1 if it is not found. If isDead is true, defs
309 /// that are not dead are skipped. If Overlap is true, then it also looks for
310 /// defs that merely overlap the specified register. If TargetRegisterInfo is
311 /// non-null, then it also checks if there is a def of a super-register.
312 int findRegisterDefOperandIdx(unsigned Reg,
313 bool isDead = false, bool Overlap = false,
314 const TargetRegisterInfo *TRI = NULL) const;
316 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
317 /// a pointer to the MachineOperand rather than an index.
318 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
319 const TargetRegisterInfo *TRI = NULL) {
320 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
321 return (Idx == -1) ? NULL : &getOperand(Idx);
324 /// findFirstPredOperandIdx() - Find the index of the first operand in the
325 /// operand list that is used to represent the predicate. It returns -1 if
327 int findFirstPredOperandIdx() const;
329 /// isRegTiedToUseOperand - Given the index of a register def operand,
330 /// check if the register def is tied to a source operand, due to either
331 /// two-address elimination or inline assembly constraints. Returns the
332 /// first tied use operand index by reference is UseOpIdx is not null.
333 bool isRegTiedToUseOperand(unsigned DefOpIdx, unsigned *UseOpIdx = 0) const;
335 /// isRegTiedToDefOperand - Return true if the use operand of the specified
336 /// index is tied to an def operand. It also returns the def operand index by
337 /// reference if DefOpIdx is not null.
338 bool isRegTiedToDefOperand(unsigned UseOpIdx, unsigned *DefOpIdx = 0) const;
340 /// clearKillInfo - Clears kill flags on all operands.
342 void clearKillInfo();
344 /// copyKillDeadInfo - Copies kill / dead operand properties from MI.
346 void copyKillDeadInfo(const MachineInstr *MI);
348 /// copyPredicates - Copies predicate operand(s) from MI.
349 void copyPredicates(const MachineInstr *MI);
351 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
352 /// properly composing subreg indices where necessary.
353 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
354 const TargetRegisterInfo &RegInfo);
356 /// addRegisterKilled - We have determined MI kills a register. Look for the
357 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
358 /// add a implicit operand if it's not found. Returns true if the operand
359 /// exists / is added.
360 bool addRegisterKilled(unsigned IncomingReg,
361 const TargetRegisterInfo *RegInfo,
362 bool AddIfNotFound = false);
364 /// addRegisterDead - We have determined MI defined a register without a use.
365 /// Look for the operand that defines it and mark it as IsDead. If
366 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
367 /// true if the operand exists / is added.
368 bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
369 bool AddIfNotFound = false);
371 /// addRegisterDefined - We have determined MI defines a register. Make sure
372 /// there is an operand defining Reg.
373 void addRegisterDefined(unsigned IncomingReg,
374 const TargetRegisterInfo *RegInfo = 0);
376 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as dead
377 /// except those in the UsedRegs list.
378 void setPhysRegsDeadExcept(const SmallVectorImpl<unsigned> &UsedRegs,
379 const TargetRegisterInfo &TRI);
381 /// isSafeToMove - Return true if it is safe to move this instruction. If
382 /// SawStore is set to true, it means that there is a store (or call) between
383 /// the instruction's location and its intended destination.
384 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
385 bool &SawStore) const;
387 /// isSafeToReMat - Return true if it's safe to rematerialize the specified
388 /// instruction which defined the specified register instead of copying it.
389 bool isSafeToReMat(const TargetInstrInfo *TII, AliasAnalysis *AA,
390 unsigned DstReg) const;
392 /// hasVolatileMemoryRef - Return true if this instruction may have a
393 /// volatile memory reference, or if the information describing the
394 /// memory reference is not available. Return false if it is known to
395 /// have no volatile memory references.
396 bool hasVolatileMemoryRef() const;
398 /// isInvariantLoad - Return true if this instruction is loading from a
399 /// location whose value is invariant across the function. For example,
400 /// loading a value from the constant pool or from the argument area of
401 /// a function if it does not change. This should only return true of *all*
402 /// loads the instruction does are invariant (if it does multiple loads).
403 bool isInvariantLoad(AliasAnalysis *AA) const;
405 /// isConstantValuePHI - If the specified instruction is a PHI that always
406 /// merges together the same virtual register, return the register, otherwise
408 unsigned isConstantValuePHI() const;
410 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
412 bool allDefsAreDead() const;
417 void print(raw_ostream &OS, const TargetMachine *TM = 0) const;
420 //===--------------------------------------------------------------------===//
421 // Accessors used to build up machine instructions.
423 /// addOperand - Add the specified operand to the instruction. If it is an
424 /// implicit operand, it is added to the end of the operand list. If it is
425 /// an explicit operand it is added at the end of the explicit operand list
426 /// (before the first implicit operand).
427 void addOperand(const MachineOperand &Op);
429 /// setDesc - Replace the instruction descriptor (thus opcode) of
430 /// the current instruction with a new one.
432 void setDesc(const TargetInstrDesc &tid) { TID = &tid; }
434 /// setDebugLoc - Replace current source information with new such.
435 /// Avoid using this, the constructor argument is preferable.
437 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
439 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
440 /// fewer operand than it started with.
442 void RemoveOperand(unsigned i);
444 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
445 /// This function should be used only occasionally. The setMemRefs function
446 /// is the primary method for setting up a MachineInstr's MemRefs list.
447 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
449 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
450 /// list. This does not transfer ownership.
451 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
452 MemRefs = NewMemRefs;
453 MemRefsEnd = NewMemRefsEnd;
457 /// getRegInfo - If this instruction is embedded into a MachineFunction,
458 /// return the MachineRegisterInfo object for the current function, otherwise
460 MachineRegisterInfo *getRegInfo();
462 /// addImplicitDefUseOperands - Add all implicit def and use operands to
463 /// this instruction.
464 void addImplicitDefUseOperands();
466 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
467 /// this instruction from their respective use lists. This requires that the
468 /// operands already be on their use lists.
469 void RemoveRegOperandsFromUseLists();
471 /// AddRegOperandsToUseLists - Add all of the register operands in
472 /// this instruction from their respective use lists. This requires that the
473 /// operands not be on their use lists yet.
474 void AddRegOperandsToUseLists(MachineRegisterInfo &RegInfo);
477 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
478 /// MachineInstr* by *value* of the instruction rather than by pointer value.
479 /// The hashing and equality testing functions ignore definitions so this is
480 /// useful for CSE, etc.
481 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
482 static inline MachineInstr *getEmptyKey() {
486 static inline MachineInstr *getTombstoneKey() {
487 return reinterpret_cast<MachineInstr*>(-1);
490 static unsigned getHashValue(const MachineInstr* const &MI);
492 static bool isEqual(const MachineInstr* const &LHS,
493 const MachineInstr* const &RHS) {
494 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
495 LHS == getEmptyKey() || LHS == getTombstoneKey())
497 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
501 //===----------------------------------------------------------------------===//
504 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
509 } // End llvm namespace