1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/DenseMapInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/ilist.h"
24 #include "llvm/ADT/ilist_node.h"
25 #include "llvm/ADT/iterator_range.h"
26 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/CodeGen/MachineOperand.h"
28 #include "llvm/IR/DebugInfo.h"
29 #include "llvm/IR/DebugLoc.h"
30 #include "llvm/IR/InlineAsm.h"
31 #include "llvm/MC/MCInstrDesc.h"
32 #include "llvm/Support/ArrayRecycler.h"
33 #include "llvm/Target/TargetOpcodes.h"
37 template <typename T> class SmallVectorImpl;
38 class TargetInstrInfo;
39 class TargetRegisterClass;
40 class TargetRegisterInfo;
41 class MachineFunction;
42 class MachineMemOperand;
44 //===----------------------------------------------------------------------===//
45 /// Representation of each machine instruction.
47 /// This class isn't a POD type, but it must have a trivial destructor. When a
48 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
49 /// without having their destructor called.
52 : public ilist_node_with_parent<MachineInstr, MachineBasicBlock> {
54 typedef MachineMemOperand **mmo_iterator;
56 /// Flags to specify different kinds of comments to output in
57 /// assembly code. These flags carry semantic information not
58 /// otherwise easily derivable from the IR text.
66 FrameSetup = 1 << 0, // Instruction is used as a part of
67 // function frame setup code.
68 FrameDestroy = 1 << 1, // Instruction is used as a part of
69 // function frame destruction code.
70 BundledPred = 1 << 2, // Instruction has bundled predecessors.
71 BundledSucc = 1 << 3 // Instruction has bundled successors.
74 const MCInstrDesc *MCID; // Instruction descriptor.
75 MachineBasicBlock *Parent; // Pointer to the owning basic block.
77 // Operands are allocated by an ArrayRecycler.
78 MachineOperand *Operands; // Pointer to the first operand.
79 unsigned NumOperands; // Number of operands on instruction.
80 typedef ArrayRecycler<MachineOperand>::Capacity OperandCapacity;
81 OperandCapacity CapOperands; // Capacity of the Operands array.
83 uint8_t Flags; // Various bits of additional
84 // information about machine
87 uint8_t AsmPrinterFlags; // Various bits of information used by
88 // the AsmPrinter to emit helpful
89 // comments. This is *not* semantic
90 // information. Do not use this for
91 // anything other than to convey comment
92 // information to AsmPrinter.
94 uint8_t NumMemRefs; // Information on memory references.
97 DebugLoc debugLoc; // Source line information.
99 MachineInstr(const MachineInstr&) = delete;
100 void operator=(const MachineInstr&) = delete;
101 // Use MachineFunction::DeleteMachineInstr() instead.
102 ~MachineInstr() = delete;
104 // Intrusive list support
105 friend struct ilist_traits<MachineInstr>;
106 friend struct ilist_traits<MachineBasicBlock>;
107 void setParent(MachineBasicBlock *P) { Parent = P; }
109 /// This constructor creates a copy of the given
110 /// MachineInstr in the given MachineFunction.
111 MachineInstr(MachineFunction &, const MachineInstr &);
113 /// This constructor create a MachineInstr and add the implicit operands.
114 /// It reserves space for number of operands specified by
115 /// MCInstrDesc. An explicit DebugLoc is supplied.
116 MachineInstr(MachineFunction &, const MCInstrDesc &MCID, DebugLoc dl,
119 // MachineInstrs are pool-allocated and owned by MachineFunction.
120 friend class MachineFunction;
123 const MachineBasicBlock* getParent() const { return Parent; }
124 MachineBasicBlock* getParent() { return Parent; }
126 /// Return the asm printer flags bitvector.
127 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
129 /// Clear the AsmPrinter bitvector.
130 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
132 /// Return whether an AsmPrinter flag is set.
133 bool getAsmPrinterFlag(CommentFlag Flag) const {
134 return AsmPrinterFlags & Flag;
137 /// Set a flag for the AsmPrinter.
138 void setAsmPrinterFlag(CommentFlag Flag) {
139 AsmPrinterFlags |= (uint8_t)Flag;
142 /// Clear specific AsmPrinter flags.
143 void clearAsmPrinterFlag(CommentFlag Flag) {
144 AsmPrinterFlags &= ~Flag;
147 /// Return the MI flags bitvector.
148 uint8_t getFlags() const {
152 /// Return whether an MI flag is set.
153 bool getFlag(MIFlag Flag) const {
158 void setFlag(MIFlag Flag) {
159 Flags |= (uint8_t)Flag;
162 void setFlags(unsigned flags) {
163 // Filter out the automatically maintained flags.
164 unsigned Mask = BundledPred | BundledSucc;
165 Flags = (Flags & Mask) | (flags & ~Mask);
168 /// clearFlag - Clear a MI flag.
169 void clearFlag(MIFlag Flag) {
170 Flags &= ~((uint8_t)Flag);
173 /// Return true if MI is in a bundle (but not the first MI in a bundle).
175 /// A bundle looks like this before it's finalized:
187 /// In this case, the first MI starts a bundle but is not inside a bundle, the
188 /// next 2 MIs are considered "inside" the bundle.
190 /// After a bundle is finalized, it looks like this:
206 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
207 /// a bundle, but the next three MIs are.
208 bool isInsideBundle() const {
209 return getFlag(BundledPred);
212 /// Return true if this instruction part of a bundle. This is true
213 /// if either itself or its following instruction is marked "InsideBundle".
214 bool isBundled() const {
215 return isBundledWithPred() || isBundledWithSucc();
218 /// Return true if this instruction is part of a bundle, and it is not the
219 /// first instruction in the bundle.
220 bool isBundledWithPred() const { return getFlag(BundledPred); }
222 /// Return true if this instruction is part of a bundle, and it is not the
223 /// last instruction in the bundle.
224 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
226 /// Bundle this instruction with its predecessor. This can be an unbundled
227 /// instruction, or it can be the first instruction in a bundle.
228 void bundleWithPred();
230 /// Bundle this instruction with its successor. This can be an unbundled
231 /// instruction, or it can be the last instruction in a bundle.
232 void bundleWithSucc();
234 /// Break bundle above this instruction.
235 void unbundleFromPred();
237 /// Break bundle below this instruction.
238 void unbundleFromSucc();
240 /// Returns the debug location id of this MachineInstr.
241 const DebugLoc &getDebugLoc() const { return debugLoc; }
243 /// Return the debug variable referenced by
244 /// this DBG_VALUE instruction.
245 const DILocalVariable *getDebugVariable() const {
246 assert(isDebugValue() && "not a DBG_VALUE");
247 return cast<DILocalVariable>(getOperand(2).getMetadata());
250 /// Return the complex address expression referenced by
251 /// this DBG_VALUE instruction.
252 const DIExpression *getDebugExpression() const {
253 assert(isDebugValue() && "not a DBG_VALUE");
254 return cast<DIExpression>(getOperand(3).getMetadata());
257 /// Emit an error referring to the source location of this instruction.
258 /// This should only be used for inline assembly that is somehow
259 /// impossible to compile. Other errors should have been handled much
262 /// If this method returns, the caller should try to recover from the error.
264 void emitError(StringRef Msg) const;
266 /// Returns the target instruction descriptor of this MachineInstr.
267 const MCInstrDesc &getDesc() const { return *MCID; }
269 /// Returns the opcode of this MachineInstr.
270 unsigned getOpcode() const { return MCID->Opcode; }
272 /// Access to explicit operands of the instruction.
274 unsigned getNumOperands() const { return NumOperands; }
276 const MachineOperand& getOperand(unsigned i) const {
277 assert(i < getNumOperands() && "getOperand() out of range!");
280 MachineOperand& getOperand(unsigned i) {
281 assert(i < getNumOperands() && "getOperand() out of range!");
285 /// Returns the number of non-implicit operands.
286 unsigned getNumExplicitOperands() const;
288 /// iterator/begin/end - Iterate over all operands of a machine instruction.
289 typedef MachineOperand *mop_iterator;
290 typedef const MachineOperand *const_mop_iterator;
292 mop_iterator operands_begin() { return Operands; }
293 mop_iterator operands_end() { return Operands + NumOperands; }
295 const_mop_iterator operands_begin() const { return Operands; }
296 const_mop_iterator operands_end() const { return Operands + NumOperands; }
298 iterator_range<mop_iterator> operands() {
299 return make_range(operands_begin(), operands_end());
301 iterator_range<const_mop_iterator> operands() const {
302 return make_range(operands_begin(), operands_end());
304 iterator_range<mop_iterator> explicit_operands() {
305 return make_range(operands_begin(),
306 operands_begin() + getNumExplicitOperands());
308 iterator_range<const_mop_iterator> explicit_operands() const {
309 return make_range(operands_begin(),
310 operands_begin() + getNumExplicitOperands());
312 iterator_range<mop_iterator> implicit_operands() {
313 return make_range(explicit_operands().end(), operands_end());
315 iterator_range<const_mop_iterator> implicit_operands() const {
316 return make_range(explicit_operands().end(), operands_end());
318 /// Returns a range over all explicit operands that are register definitions.
319 /// Implicit definition are not included!
320 iterator_range<mop_iterator> defs() {
321 return make_range(operands_begin(),
322 operands_begin() + getDesc().getNumDefs());
325 iterator_range<const_mop_iterator> defs() const {
326 return make_range(operands_begin(),
327 operands_begin() + getDesc().getNumDefs());
329 /// Returns a range that includes all operands that are register uses.
330 /// This may include unrelated operands which are not register uses.
331 iterator_range<mop_iterator> uses() {
332 return make_range(operands_begin() + getDesc().getNumDefs(),
336 iterator_range<const_mop_iterator> uses() const {
337 return make_range(operands_begin() + getDesc().getNumDefs(),
341 /// Returns the number of the operand iterator \p I points to.
342 unsigned getOperandNo(const_mop_iterator I) const {
343 return I - operands_begin();
346 /// Access to memory operands of the instruction
347 mmo_iterator memoperands_begin() const { return MemRefs; }
348 mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
349 bool memoperands_empty() const { return NumMemRefs == 0; }
351 iterator_range<mmo_iterator> memoperands() {
352 return make_range(memoperands_begin(), memoperands_end());
354 iterator_range<mmo_iterator> memoperands() const {
355 return make_range(memoperands_begin(), memoperands_end());
358 /// Return true if this instruction has exactly one MachineMemOperand.
359 bool hasOneMemOperand() const {
360 return NumMemRefs == 1;
363 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
364 /// queries but they are bundle aware.
367 IgnoreBundle, // Ignore bundles
368 AnyInBundle, // Return true if any instruction in bundle has property
369 AllInBundle // Return true if all instructions in bundle have property
372 /// Return true if the instruction (or in the case of a bundle,
373 /// the instructions inside the bundle) has the specified property.
374 /// The first argument is the property being queried.
375 /// The second argument indicates whether the query should look inside
376 /// instruction bundles.
377 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
378 // Inline the fast path for unbundled or bundle-internal instructions.
379 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
380 return getDesc().getFlags() & (1 << MCFlag);
382 // If this is the first instruction in a bundle, take the slow path.
383 return hasPropertyInBundle(1 << MCFlag, Type);
386 /// Return true if this instruction can have a variable number of operands.
387 /// In this case, the variable operands will be after the normal
388 /// operands but before the implicit definitions and uses (if any are
390 bool isVariadic(QueryType Type = IgnoreBundle) const {
391 return hasProperty(MCID::Variadic, Type);
394 /// Set if this instruction has an optional definition, e.g.
395 /// ARM instructions which can set condition code if 's' bit is set.
396 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
397 return hasProperty(MCID::HasOptionalDef, Type);
400 /// Return true if this is a pseudo instruction that doesn't
401 /// correspond to a real machine instruction.
402 bool isPseudo(QueryType Type = IgnoreBundle) const {
403 return hasProperty(MCID::Pseudo, Type);
406 bool isReturn(QueryType Type = AnyInBundle) const {
407 return hasProperty(MCID::Return, Type);
410 bool isCall(QueryType Type = AnyInBundle) const {
411 return hasProperty(MCID::Call, Type);
414 /// Returns true if the specified instruction stops control flow
415 /// from executing the instruction immediately following it. Examples include
416 /// unconditional branches and return instructions.
417 bool isBarrier(QueryType Type = AnyInBundle) const {
418 return hasProperty(MCID::Barrier, Type);
421 /// Returns true if this instruction part of the terminator for a basic block.
422 /// Typically this is things like return and branch instructions.
424 /// Various passes use this to insert code into the bottom of a basic block,
425 /// but before control flow occurs.
426 bool isTerminator(QueryType Type = AnyInBundle) const {
427 return hasProperty(MCID::Terminator, Type);
430 /// Returns true if this is a conditional, unconditional, or indirect branch.
431 /// Predicates below can be used to discriminate between
432 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
433 /// get more information.
434 bool isBranch(QueryType Type = AnyInBundle) const {
435 return hasProperty(MCID::Branch, Type);
438 /// Return true if this is an indirect branch, such as a
439 /// branch through a register.
440 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
441 return hasProperty(MCID::IndirectBranch, Type);
444 /// Return true if this is a branch which may fall
445 /// through to the next instruction or may transfer control flow to some other
446 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
447 /// information about this branch.
448 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
449 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
452 /// Return true if this is a branch which always
453 /// transfers control flow to some other block. The
454 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
455 /// about this branch.
456 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
457 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
460 /// Return true if this instruction has a predicate operand that
461 /// controls execution. It may be set to 'always', or may be set to other
462 /// values. There are various methods in TargetInstrInfo that can be used to
463 /// control and modify the predicate in this instruction.
464 bool isPredicable(QueryType Type = AllInBundle) const {
465 // If it's a bundle than all bundled instructions must be predicable for this
467 return hasProperty(MCID::Predicable, Type);
470 /// Return true if this instruction is a comparison.
471 bool isCompare(QueryType Type = IgnoreBundle) const {
472 return hasProperty(MCID::Compare, Type);
475 /// Return true if this instruction is a move immediate
476 /// (including conditional moves) instruction.
477 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
478 return hasProperty(MCID::MoveImm, Type);
481 /// Return true if this instruction is a bitcast instruction.
482 bool isBitcast(QueryType Type = IgnoreBundle) const {
483 return hasProperty(MCID::Bitcast, Type);
486 /// Return true if this instruction is a select instruction.
487 bool isSelect(QueryType Type = IgnoreBundle) const {
488 return hasProperty(MCID::Select, Type);
491 /// Return true if this instruction cannot be safely duplicated.
492 /// For example, if the instruction has a unique labels attached
493 /// to it, duplicating it would cause multiple definition errors.
494 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
495 return hasProperty(MCID::NotDuplicable, Type);
498 /// Return true if this instruction is convergent.
499 /// Convergent instructions can not be made control-dependent on any
500 /// additional values.
501 bool isConvergent(QueryType Type = AnyInBundle) const {
502 return hasProperty(MCID::Convergent, Type);
505 /// Returns true if the specified instruction has a delay slot
506 /// which must be filled by the code generator.
507 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
508 return hasProperty(MCID::DelaySlot, Type);
511 /// Return true for instructions that can be folded as
512 /// memory operands in other instructions. The most common use for this
513 /// is instructions that are simple loads from memory that don't modify
514 /// the loaded value in any way, but it can also be used for instructions
515 /// that can be expressed as constant-pool loads, such as V_SETALLONES
516 /// on x86, to allow them to be folded when it is beneficial.
517 /// This should only be set on instructions that return a value in their
518 /// only virtual register definition.
519 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
520 return hasProperty(MCID::FoldableAsLoad, Type);
523 /// \brief Return true if this instruction behaves
524 /// the same way as the generic REG_SEQUENCE instructions.
526 /// dX VMOVDRR rY, rZ
528 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1.
530 /// Note that for the optimizers to be able to take advantage of
531 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be
532 /// override accordingly.
533 bool isRegSequenceLike(QueryType Type = IgnoreBundle) const {
534 return hasProperty(MCID::RegSequence, Type);
537 /// \brief Return true if this instruction behaves
538 /// the same way as the generic EXTRACT_SUBREG instructions.
540 /// rX, rY VMOVRRD dZ
541 /// is equivalent to two EXTRACT_SUBREG:
542 /// rX = EXTRACT_SUBREG dZ, ssub_0
543 /// rY = EXTRACT_SUBREG dZ, ssub_1
545 /// Note that for the optimizers to be able to take advantage of
546 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be
547 /// override accordingly.
548 bool isExtractSubregLike(QueryType Type = IgnoreBundle) const {
549 return hasProperty(MCID::ExtractSubreg, Type);
552 /// \brief Return true if this instruction behaves
553 /// the same way as the generic INSERT_SUBREG instructions.
555 /// dX = VSETLNi32 dY, rZ, Imm
556 /// is equivalent to a INSERT_SUBREG:
557 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm)
559 /// Note that for the optimizers to be able to take advantage of
560 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be
561 /// override accordingly.
562 bool isInsertSubregLike(QueryType Type = IgnoreBundle) const {
563 return hasProperty(MCID::InsertSubreg, Type);
566 //===--------------------------------------------------------------------===//
567 // Side Effect Analysis
568 //===--------------------------------------------------------------------===//
570 /// Return true if this instruction could possibly read memory.
571 /// Instructions with this flag set are not necessarily simple load
572 /// instructions, they may load a value and modify it, for example.
573 bool mayLoad(QueryType Type = AnyInBundle) const {
575 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
576 if (ExtraInfo & InlineAsm::Extra_MayLoad)
579 return hasProperty(MCID::MayLoad, Type);
582 /// Return true if this instruction could possibly modify memory.
583 /// Instructions with this flag set are not necessarily simple store
584 /// instructions, they may store a modified value based on their operands, or
585 /// may not actually modify anything, for example.
586 bool mayStore(QueryType Type = AnyInBundle) const {
588 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
589 if (ExtraInfo & InlineAsm::Extra_MayStore)
592 return hasProperty(MCID::MayStore, Type);
595 /// Return true if this instruction could possibly read or modify memory.
596 bool mayLoadOrStore(QueryType Type = AnyInBundle) const {
597 return mayLoad(Type) || mayStore(Type);
600 //===--------------------------------------------------------------------===//
601 // Flags that indicate whether an instruction can be modified by a method.
602 //===--------------------------------------------------------------------===//
604 /// Return true if this may be a 2- or 3-address
605 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
606 /// result if Y and Z are exchanged. If this flag is set, then the
607 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
610 /// Note that this flag may be set on instructions that are only commutable
611 /// sometimes. In these cases, the call to commuteInstruction will fail.
612 /// Also note that some instructions require non-trivial modification to
614 bool isCommutable(QueryType Type = IgnoreBundle) const {
615 return hasProperty(MCID::Commutable, Type);
618 /// Return true if this is a 2-address instruction
619 /// which can be changed into a 3-address instruction if needed. Doing this
620 /// transformation can be profitable in the register allocator, because it
621 /// means that the instruction can use a 2-address form if possible, but
622 /// degrade into a less efficient form if the source and dest register cannot
623 /// be assigned to the same register. For example, this allows the x86
624 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
625 /// is the same speed as the shift but has bigger code size.
627 /// If this returns true, then the target must implement the
628 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
629 /// is allowed to fail if the transformation isn't valid for this specific
630 /// instruction (e.g. shl reg, 4 on x86).
632 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
633 return hasProperty(MCID::ConvertibleTo3Addr, Type);
636 /// Return true if this instruction requires
637 /// custom insertion support when the DAG scheduler is inserting it into a
638 /// machine basic block. If this is true for the instruction, it basically
639 /// means that it is a pseudo instruction used at SelectionDAG time that is
640 /// expanded out into magic code by the target when MachineInstrs are formed.
642 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
643 /// is used to insert this into the MachineBasicBlock.
644 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
645 return hasProperty(MCID::UsesCustomInserter, Type);
648 /// Return true if this instruction requires *adjustment*
649 /// after instruction selection by calling a target hook. For example, this
650 /// can be used to fill in ARM 's' optional operand depending on whether
651 /// the conditional flag register is used.
652 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
653 return hasProperty(MCID::HasPostISelHook, Type);
656 /// Returns true if this instruction is a candidate for remat.
657 /// This flag is deprecated, please don't use it anymore. If this
658 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
659 /// verify the instruction is really rematable.
660 bool isRematerializable(QueryType Type = AllInBundle) const {
661 // It's only possible to re-mat a bundle if all bundled instructions are
662 // re-materializable.
663 return hasProperty(MCID::Rematerializable, Type);
666 /// Returns true if this instruction has the same cost (or less) than a move
667 /// instruction. This is useful during certain types of optimizations
668 /// (e.g., remat during two-address conversion or machine licm)
669 /// where we would like to remat or hoist the instruction, but not if it costs
670 /// more than moving the instruction into the appropriate register. Note, we
671 /// are not marking copies from and to the same register class with this flag.
672 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
673 // Only returns true for a bundle if all bundled instructions are cheap.
674 return hasProperty(MCID::CheapAsAMove, Type);
677 /// Returns true if this instruction source operands
678 /// have special register allocation requirements that are not captured by the
679 /// operand register classes. e.g. ARM::STRD's two source registers must be an
680 /// even / odd pair, ARM::STM registers have to be in ascending order.
681 /// Post-register allocation passes should not attempt to change allocations
682 /// for sources of instructions with this flag.
683 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
684 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
687 /// Returns true if this instruction def operands
688 /// have special register allocation requirements that are not captured by the
689 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
690 /// even / odd pair, ARM::LDM registers have to be in ascending order.
691 /// Post-register allocation passes should not attempt to change allocations
692 /// for definitions of instructions with this flag.
693 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
694 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
699 CheckDefs, // Check all operands for equality
700 CheckKillDead, // Check all operands including kill / dead markers
701 IgnoreDefs, // Ignore all definitions
702 IgnoreVRegDefs // Ignore virtual register definitions
705 /// Return true if this instruction is identical to (same
706 /// opcode and same operands as) the specified instruction.
707 bool isIdenticalTo(const MachineInstr *Other,
708 MICheckType Check = CheckDefs) const;
710 /// Unlink 'this' from the containing basic block, and return it without
713 /// This function can not be used on bundled instructions, use
714 /// removeFromBundle() to remove individual instructions from a bundle.
715 MachineInstr *removeFromParent();
717 /// Unlink this instruction from its basic block and return it without
720 /// If the instruction is part of a bundle, the other instructions in the
721 /// bundle remain bundled.
722 MachineInstr *removeFromBundle();
724 /// Unlink 'this' from the containing basic block and delete it.
726 /// If this instruction is the header of a bundle, the whole bundle is erased.
727 /// This function can not be used for instructions inside a bundle, use
728 /// eraseFromBundle() to erase individual bundled instructions.
729 void eraseFromParent();
731 /// Unlink 'this' from the containing basic block and delete it.
733 /// For all definitions mark their uses in DBG_VALUE nodes
734 /// as undefined. Otherwise like eraseFromParent().
735 void eraseFromParentAndMarkDBGValuesForRemoval();
737 /// Unlink 'this' form its basic block and delete it.
739 /// If the instruction is part of a bundle, the other instructions in the
740 /// bundle remain bundled.
741 void eraseFromBundle();
743 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
744 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
746 /// Returns true if the MachineInstr represents a label.
747 bool isLabel() const { return isEHLabel() || isGCLabel(); }
748 bool isCFIInstruction() const {
749 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
752 // True if the instruction represents a position in the function.
753 bool isPosition() const { return isLabel() || isCFIInstruction(); }
755 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
756 /// A DBG_VALUE is indirect iff the first operand is a register and
757 /// the second operand is an immediate.
758 bool isIndirectDebugValue() const {
759 return isDebugValue()
760 && getOperand(0).isReg()
761 && getOperand(1).isImm();
764 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
765 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
766 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
767 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
768 bool isMSInlineAsm() const {
769 return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();
771 bool isStackAligningInlineAsm() const;
772 InlineAsm::AsmDialect getInlineAsmDialect() const;
773 bool isInsertSubreg() const {
774 return getOpcode() == TargetOpcode::INSERT_SUBREG;
776 bool isSubregToReg() const {
777 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
779 bool isRegSequence() const {
780 return getOpcode() == TargetOpcode::REG_SEQUENCE;
782 bool isBundle() const {
783 return getOpcode() == TargetOpcode::BUNDLE;
785 bool isCopy() const {
786 return getOpcode() == TargetOpcode::COPY;
788 bool isFullCopy() const {
789 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
791 bool isExtractSubreg() const {
792 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
795 /// Return true if the instruction behaves like a copy.
796 /// This does not include native copy instructions.
797 bool isCopyLike() const {
798 return isCopy() || isSubregToReg();
801 /// Return true is the instruction is an identity copy.
802 bool isIdentityCopy() const {
803 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
804 getOperand(0).getSubReg() == getOperand(1).getSubReg();
807 /// Return true if this is a transient instruction that is
808 /// either very likely to be eliminated during register allocation (such as
809 /// copy-like instructions), or if this instruction doesn't have an
810 /// execution-time cost.
811 bool isTransient() const {
812 switch(getOpcode()) {
813 default: return false;
814 // Copy-like instructions are usually eliminated during register allocation.
815 case TargetOpcode::PHI:
816 case TargetOpcode::COPY:
817 case TargetOpcode::INSERT_SUBREG:
818 case TargetOpcode::SUBREG_TO_REG:
819 case TargetOpcode::REG_SEQUENCE:
820 // Pseudo-instructions that don't produce any real output.
821 case TargetOpcode::IMPLICIT_DEF:
822 case TargetOpcode::KILL:
823 case TargetOpcode::CFI_INSTRUCTION:
824 case TargetOpcode::EH_LABEL:
825 case TargetOpcode::GC_LABEL:
826 case TargetOpcode::DBG_VALUE:
831 /// Return the number of instructions inside the MI bundle, excluding the
834 /// This is the number of instructions that MachineBasicBlock::iterator
835 /// skips, 0 for unbundled instructions.
836 unsigned getBundleSize() const;
838 /// Return true if the MachineInstr reads the specified register.
839 /// If TargetRegisterInfo is passed, then it also checks if there
840 /// is a read of a super-register.
841 /// This does not count partial redefines of virtual registers as reads:
843 bool readsRegister(unsigned Reg,
844 const TargetRegisterInfo *TRI = nullptr) const {
845 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
848 /// Return true if the MachineInstr reads the specified virtual register.
849 /// Take into account that a partial define is a
850 /// read-modify-write operation.
851 bool readsVirtualRegister(unsigned Reg) const {
852 return readsWritesVirtualRegister(Reg).first;
855 /// Return a pair of bools (reads, writes) indicating if this instruction
856 /// reads or writes Reg. This also considers partial defines.
857 /// If Ops is not null, all operand indices for Reg are added.
858 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
859 SmallVectorImpl<unsigned> *Ops = nullptr) const;
861 /// Return true if the MachineInstr kills the specified register.
862 /// If TargetRegisterInfo is passed, then it also checks if there is
863 /// a kill of a super-register.
864 bool killsRegister(unsigned Reg,
865 const TargetRegisterInfo *TRI = nullptr) const {
866 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
869 /// Return true if the MachineInstr fully defines the specified register.
870 /// If TargetRegisterInfo is passed, then it also checks
871 /// if there is a def of a super-register.
872 /// NOTE: It's ignoring subreg indices on virtual registers.
873 bool definesRegister(unsigned Reg,
874 const TargetRegisterInfo *TRI = nullptr) const {
875 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
878 /// Return true if the MachineInstr modifies (fully define or partially
879 /// define) the specified register.
880 /// NOTE: It's ignoring subreg indices on virtual registers.
881 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
882 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
885 /// Returns true if the register is dead in this machine instruction.
886 /// If TargetRegisterInfo is passed, then it also checks
887 /// if there is a dead def of a super-register.
888 bool registerDefIsDead(unsigned Reg,
889 const TargetRegisterInfo *TRI = nullptr) const {
890 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
893 /// Returns the operand index that is a use of the specific register or -1
894 /// if it is not found. It further tightens the search criteria to a use
895 /// that kills the register if isKill is true.
896 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
897 const TargetRegisterInfo *TRI = nullptr) const;
899 /// Wrapper for findRegisterUseOperandIdx, it returns
900 /// a pointer to the MachineOperand rather than an index.
901 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
902 const TargetRegisterInfo *TRI = nullptr) {
903 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
904 return (Idx == -1) ? nullptr : &getOperand(Idx);
907 const MachineOperand *findRegisterUseOperand(
908 unsigned Reg, bool isKill = false,
909 const TargetRegisterInfo *TRI = nullptr) const {
910 return const_cast<MachineInstr *>(this)->
911 findRegisterUseOperand(Reg, isKill, TRI);
914 /// Returns the operand index that is a def of the specified register or
915 /// -1 if it is not found. If isDead is true, defs that are not dead are
916 /// skipped. If Overlap is true, then it also looks for defs that merely
917 /// overlap the specified register. If TargetRegisterInfo is non-null,
918 /// then it also checks if there is a def of a super-register.
919 /// This may also return a register mask operand when Overlap is true.
920 int findRegisterDefOperandIdx(unsigned Reg,
921 bool isDead = false, bool Overlap = false,
922 const TargetRegisterInfo *TRI = nullptr) const;
924 /// Wrapper for findRegisterDefOperandIdx, it returns
925 /// a pointer to the MachineOperand rather than an index.
926 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
927 const TargetRegisterInfo *TRI = nullptr) {
928 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
929 return (Idx == -1) ? nullptr : &getOperand(Idx);
932 /// Find the index of the first operand in the
933 /// operand list that is used to represent the predicate. It returns -1 if
935 int findFirstPredOperandIdx() const;
937 /// Find the index of the flag word operand that
938 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
939 /// getOperand(OpIdx) does not belong to an inline asm operand group.
941 /// If GroupNo is not NULL, it will receive the number of the operand group
942 /// containing OpIdx.
944 /// The flag operand is an immediate that can be decoded with methods like
945 /// InlineAsm::hasRegClassConstraint().
947 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
949 /// Compute the static register class constraint for operand OpIdx.
950 /// For normal instructions, this is derived from the MCInstrDesc.
951 /// For inline assembly it is derived from the flag words.
953 /// Returns NULL if the static register class constraint cannot be
956 const TargetRegisterClass*
957 getRegClassConstraint(unsigned OpIdx,
958 const TargetInstrInfo *TII,
959 const TargetRegisterInfo *TRI) const;
961 /// \brief Applies the constraints (def/use) implied by this MI on \p Reg to
962 /// the given \p CurRC.
963 /// If \p ExploreBundle is set and MI is part of a bundle, all the
964 /// instructions inside the bundle will be taken into account. In other words,
965 /// this method accumulates all the constraints of the operand of this MI and
966 /// the related bundle if MI is a bundle or inside a bundle.
968 /// Returns the register class that satisfies both \p CurRC and the
969 /// constraints set by MI. Returns NULL if such a register class does not
972 /// \pre CurRC must not be NULL.
973 const TargetRegisterClass *getRegClassConstraintEffectForVReg(
974 unsigned Reg, const TargetRegisterClass *CurRC,
975 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
976 bool ExploreBundle = false) const;
978 /// \brief Applies the constraints (def/use) implied by the \p OpIdx operand
979 /// to the given \p CurRC.
981 /// Returns the register class that satisfies both \p CurRC and the
982 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
985 /// \pre CurRC must not be NULL.
986 /// \pre The operand at \p OpIdx must be a register.
987 const TargetRegisterClass *
988 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
989 const TargetInstrInfo *TII,
990 const TargetRegisterInfo *TRI) const;
992 /// Add a tie between the register operands at DefIdx and UseIdx.
993 /// The tie will cause the register allocator to ensure that the two
994 /// operands are assigned the same physical register.
996 /// Tied operands are managed automatically for explicit operands in the
997 /// MCInstrDesc. This method is for exceptional cases like inline asm.
998 void tieOperands(unsigned DefIdx, unsigned UseIdx);
1000 /// Given the index of a tied register operand, find the
1001 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
1002 /// index of the tied operand which must exist.
1003 unsigned findTiedOperandIdx(unsigned OpIdx) const;
1005 /// Given the index of a register def operand,
1006 /// check if the register def is tied to a source operand, due to either
1007 /// two-address elimination or inline assembly constraints. Returns the
1008 /// first tied use operand index by reference if UseOpIdx is not null.
1009 bool isRegTiedToUseOperand(unsigned DefOpIdx,
1010 unsigned *UseOpIdx = nullptr) const {
1011 const MachineOperand &MO = getOperand(DefOpIdx);
1012 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
1015 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
1019 /// Return true if the use operand of the specified index is tied to a def
1020 /// operand. It also returns the def operand index by reference if DefOpIdx
1022 bool isRegTiedToDefOperand(unsigned UseOpIdx,
1023 unsigned *DefOpIdx = nullptr) const {
1024 const MachineOperand &MO = getOperand(UseOpIdx);
1025 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
1028 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
1032 /// Clears kill flags on all operands.
1033 void clearKillInfo();
1035 /// Replace all occurrences of FromReg with ToReg:SubIdx,
1036 /// properly composing subreg indices where necessary.
1037 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
1038 const TargetRegisterInfo &RegInfo);
1040 /// We have determined MI kills a register. Look for the
1041 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
1042 /// add a implicit operand if it's not found. Returns true if the operand
1043 /// exists / is added.
1044 bool addRegisterKilled(unsigned IncomingReg,
1045 const TargetRegisterInfo *RegInfo,
1046 bool AddIfNotFound = false);
1048 /// Clear all kill flags affecting Reg. If RegInfo is
1049 /// provided, this includes super-register kills.
1050 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
1052 /// We have determined MI defined a register without a use.
1053 /// Look for the operand that defines it and mark it as IsDead. If
1054 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
1055 /// true if the operand exists / is added.
1056 bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
1057 bool AddIfNotFound = false);
1059 /// Clear all dead flags on operands defining register @p Reg.
1060 void clearRegisterDeads(unsigned Reg);
1062 /// Mark all subregister defs of register @p Reg with the undef flag.
1063 /// This function is used when we determined to have a subregister def in an
1064 /// otherwise undefined super register.
1065 void setRegisterDefReadUndef(unsigned Reg, bool IsUndef = true);
1067 /// We have determined MI defines a register. Make sure there is an operand
1069 void addRegisterDefined(unsigned Reg,
1070 const TargetRegisterInfo *RegInfo = nullptr);
1072 /// Mark every physreg used by this instruction as
1073 /// dead except those in the UsedRegs list.
1075 /// On instructions with register mask operands, also add implicit-def
1076 /// operands for all registers in UsedRegs.
1077 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1078 const TargetRegisterInfo &TRI);
1080 /// Return true if it is safe to move this instruction. If
1081 /// SawStore is set to true, it means that there is a store (or call) between
1082 /// the instruction's location and its intended destination.
1083 bool isSafeToMove(AliasAnalysis *AA, bool &SawStore) const;
1085 /// Return true if this instruction may have an ordered
1086 /// or volatile memory reference, or if the information describing the memory
1087 /// reference is not available. Return false if it is known to have no
1088 /// ordered or volatile memory references.
1089 bool hasOrderedMemoryRef() const;
1091 /// Return true if this instruction is loading from a
1092 /// location whose value is invariant across the function. For example,
1093 /// loading a value from the constant pool or from the argument area of
1094 /// a function if it does not change. This should only return true of *all*
1095 /// loads the instruction does are invariant (if it does multiple loads).
1096 bool isInvariantLoad(AliasAnalysis *AA) const;
1098 /// If the specified instruction is a PHI that always merges together the
1099 /// same virtual register, return the register, otherwise return 0.
1100 unsigned isConstantValuePHI() const;
1102 /// Return true if this instruction has side effects that are not modeled
1103 /// by mayLoad / mayStore, etc.
1104 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1105 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1106 /// INLINEASM instruction, in which case the side effect property is encoded
1107 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1109 bool hasUnmodeledSideEffects() const;
1111 /// Returns true if it is illegal to fold a load across this instruction.
1112 bool isLoadFoldBarrier() const;
1114 /// Return true if all the defs of this instruction are dead.
1115 bool allDefsAreDead() const;
1117 /// Copy implicit register operands from specified
1118 /// instruction to this instruction.
1119 void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI);
1122 // Debugging support
1124 void print(raw_ostream &OS, bool SkipOpers = false) const;
1125 void print(raw_ostream &OS, ModuleSlotTracker &MST,
1126 bool SkipOpers = false) const;
1129 //===--------------------------------------------------------------------===//
1130 // Accessors used to build up machine instructions.
1132 /// Add the specified operand to the instruction. If it is an implicit
1133 /// operand, it is added to the end of the operand list. If it is an
1134 /// explicit operand it is added at the end of the explicit operand list
1135 /// (before the first implicit operand).
1137 /// MF must be the machine function that was used to allocate this
1140 /// MachineInstrBuilder provides a more convenient interface for creating
1141 /// instructions and adding operands.
1142 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1144 /// Add an operand without providing an MF reference. This only works for
1145 /// instructions that are inserted in a basic block.
1147 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1149 void addOperand(const MachineOperand &Op);
1151 /// Replace the instruction descriptor (thus opcode) of
1152 /// the current instruction with a new one.
1153 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1155 /// Replace current source information with new such.
1156 /// Avoid using this, the constructor argument is preferable.
1157 void setDebugLoc(DebugLoc dl) {
1158 debugLoc = std::move(dl);
1159 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
1162 /// Erase an operand from an instruction, leaving it with one
1163 /// fewer operand than it started with.
1164 void RemoveOperand(unsigned i);
1166 /// Add a MachineMemOperand to the machine instruction.
1167 /// This function should be used only occasionally. The setMemRefs function
1168 /// is the primary method for setting up a MachineInstr's MemRefs list.
1169 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1171 /// Assign this MachineInstr's memory reference descriptor list.
1172 /// This does not transfer ownership.
1173 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
1174 MemRefs = NewMemRefs;
1175 NumMemRefs = uint8_t(NewMemRefsEnd - NewMemRefs);
1176 assert(NumMemRefs == NewMemRefsEnd - NewMemRefs && "Too many memrefs");
1179 /// Clear this MachineInstr's memory reference descriptor list.
1180 void clearMemRefs() {
1185 /// Break any tie involving OpIdx.
1186 void untieRegOperand(unsigned OpIdx) {
1187 MachineOperand &MO = getOperand(OpIdx);
1188 if (MO.isReg() && MO.isTied()) {
1189 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1194 /// Add all implicit def and use operands to this instruction.
1195 void addImplicitDefUseOperands(MachineFunction &MF);
1198 /// If this instruction is embedded into a MachineFunction, return the
1199 /// MachineRegisterInfo object for the current function, otherwise
1201 MachineRegisterInfo *getRegInfo();
1203 /// Unlink all of the register operands in this instruction from their
1204 /// respective use lists. This requires that the operands already be on their
1206 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1208 /// Add all of the register operands in this instruction from their
1209 /// respective use lists. This requires that the operands not be on their
1211 void AddRegOperandsToUseLists(MachineRegisterInfo&);
1213 /// Slow path for hasProperty when we're dealing with a bundle.
1214 bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
1216 /// \brief Implements the logic of getRegClassConstraintEffectForVReg for the
1217 /// this MI and the given operand index \p OpIdx.
1218 /// If the related operand does not constrained Reg, this returns CurRC.
1219 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1220 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1221 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1224 /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the
1225 /// instruction rather than by pointer value.
1226 /// The hashing and equality testing functions ignore definitions so this is
1227 /// useful for CSE, etc.
1228 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1229 static inline MachineInstr *getEmptyKey() {
1233 static inline MachineInstr *getTombstoneKey() {
1234 return reinterpret_cast<MachineInstr*>(-1);
1237 static unsigned getHashValue(const MachineInstr* const &MI);
1239 static bool isEqual(const MachineInstr* const &LHS,
1240 const MachineInstr* const &RHS) {
1241 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1242 LHS == getEmptyKey() || LHS == getTombstoneKey())
1244 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
1248 //===----------------------------------------------------------------------===//
1249 // Debugging Support
1251 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1256 } // End llvm namespace