1 //===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariables analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using a sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #ifndef LLVM_CODEGEN_LIVEVARIABLES_H
30 #define LLVM_CODEGEN_LIVEVARIABLES_H
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/DenseMap.h"
35 #include "llvm/ADT/SmallVector.h"
39 class MachineRegisterInfo;
40 class TargetRegisterInfo;
42 class LiveVariables : public MachineFunctionPass {
44 static char ID; // Pass identification, replacement for typeid
45 LiveVariables() : MachineFunctionPass(&ID) {}
47 /// VarInfo - This represents the regions where a virtual register is live in
48 /// the program. We represent this with three different pieces of
49 /// information: the set of blocks in which the instruction is live
50 /// throughout, the set of blocks in which the instruction is actually used,
51 /// and the set of non-phi instructions that are the last users of the value.
53 /// In the common case where a value is defined and killed in the same block,
54 /// There is one killing instruction, and AliveBlocks is empty.
56 /// Otherwise, the value is live out of the block. If the value is live
57 /// throughout any blocks, these blocks are listed in AliveBlocks. Blocks
58 /// where the liveness range ends are not included in AliveBlocks, instead
59 /// being captured by the Kills set. In these blocks, the value is live into
60 /// the block (unless the value is defined and killed in the same block) and
61 /// lives until the specified instruction. Note that there cannot ever be a
62 /// value whose Kills set contains two instructions from the same basic block.
64 /// PHI nodes complicate things a bit. If a PHI node is the last user of a
65 /// value in one of its predecessor blocks, it is not listed in the kills set,
66 /// but does include the predecessor block in the AliveBlocks set (unless that
67 /// block also defines the value). This leads to the (perfectly sensical)
68 /// situation where a value is defined in a block, and the last use is a phi
69 /// node in the successor. In this case, AliveBlocks is empty (the value is
70 /// not live across any blocks) and Kills is empty (phi nodes are not
71 /// included). This is sensical because the value must be live to the end of
72 /// the block, but is not live in any successor blocks.
74 /// AliveBlocks - Set of blocks in which this value is alive completely
75 /// through. This is a bit set which uses the basic block number as an
78 BitVector AliveBlocks;
80 /// NumUses - Number of uses of this register across the entire function.
84 /// Kills - List of MachineInstruction's which are the last use of this
85 /// virtual register (kill it) in their basic block.
87 std::vector<MachineInstr*> Kills;
89 VarInfo() : NumUses(0) {}
91 /// removeKill - Delete a kill corresponding to the specified
92 /// machine instruction. Returns true if there was a kill
93 /// corresponding to this instruction, false otherwise.
94 bool removeKill(MachineInstr *MI) {
95 std::vector<MachineInstr*>::iterator
96 I = std::find(Kills.begin(), Kills.end(), MI);
107 /// VirtRegInfo - This list is a mapping from virtual register number to
108 /// variable information. FirstVirtualRegister is subtracted from the virtual
109 /// register number before indexing into this list.
111 std::vector<VarInfo> VirtRegInfo;
113 /// ReservedRegisters - This vector keeps track of which registers
114 /// are reserved register which are not allocatable by the target machine.
115 /// We can not track liveness for values that are in this set.
117 BitVector ReservedRegisters;
119 private: // Intermediate data structures
122 MachineRegisterInfo* MRI;
124 const TargetRegisterInfo *TRI;
126 // PhysRegInfo - Keep track of which instruction was the last def of a
127 // physical register. This is a purely local property, because all physical
128 // register references are presumed dead across basic blocks.
129 MachineInstr **PhysRegDef;
131 // PhysRegInfo - Keep track of which instruction was the last use of a
132 // physical register. This is a purely local property, because all physical
133 // register references are presumed dead across basic blocks.
134 MachineInstr **PhysRegUse;
136 SmallVector<unsigned, 4> *PHIVarInfo;
138 // DistanceMap - Keep track the distance of a MI from the start of the
139 // current basic block.
140 DenseMap<MachineInstr*, unsigned> DistanceMap;
142 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
143 /// uses. Pay special attention to the sub-register uses which may come below
144 /// the last use of the whole register.
145 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
147 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
148 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI);
150 /// FindLastPartialDef - Return the last partial def of the specified register.
151 /// Also returns the sub-register that's defined.
152 MachineInstr *FindLastPartialDef(unsigned Reg, unsigned &PartDefReg);
154 /// hasRegisterUseBelow - Return true if the specified register is used after
155 /// the current instruction and before it's next definition.
156 bool hasRegisterUseBelow(unsigned Reg, MachineBasicBlock::iterator I,
157 MachineBasicBlock *MBB);
159 /// analyzePHINodes - Gather information about the PHI nodes in here. In
160 /// particular, we want to map the variable information of a virtual
161 /// register which is used in a PHI node. We map that to the BB the vreg
163 void analyzePHINodes(const MachineFunction& Fn);
166 virtual bool runOnMachineFunction(MachineFunction &MF);
168 /// RegisterDefIsDead - Return true if the specified instruction defines the
169 /// specified register, but that definition is dead.
170 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
172 //===--------------------------------------------------------------------===//
173 // API to update live variable information
175 /// replaceKillInstruction - Update register kill info by replacing a kill
176 /// instruction with a new one.
177 void replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
178 MachineInstr *NewMI);
180 /// addVirtualRegisterKilled - Add information about the fact that the
181 /// specified register is killed after being used by the specified
182 /// instruction. If AddIfNotFound is true, add a implicit operand if it's
184 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
185 bool AddIfNotFound = false) {
186 if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
187 getVarInfo(IncomingReg).Kills.push_back(MI);
190 /// removeVirtualRegisterKilled - Remove the specified kill of the virtual
191 /// register from the live variable information. Returns true if the
192 /// variable was marked as killed by the specified instruction,
194 bool removeVirtualRegisterKilled(unsigned reg, MachineInstr *MI) {
195 if (!getVarInfo(reg).removeKill(MI))
198 bool Removed = false;
199 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
200 MachineOperand &MO = MI->getOperand(i);
201 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
208 assert(Removed && "Register is not used by this instruction!");
212 /// removeVirtualRegistersKilled - Remove all killed info for the specified
214 void removeVirtualRegistersKilled(MachineInstr *MI);
216 /// addVirtualRegisterDead - Add information about the fact that the specified
217 /// register is dead after being used by the specified instruction. If
218 /// AddIfNotFound is true, add a implicit operand if it's not found.
219 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI,
220 bool AddIfNotFound = false) {
221 if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
222 getVarInfo(IncomingReg).Kills.push_back(MI);
225 /// removeVirtualRegisterDead - Remove the specified kill of the virtual
226 /// register from the live variable information. Returns true if the
227 /// variable was marked dead at the specified instruction, false
229 bool removeVirtualRegisterDead(unsigned reg, MachineInstr *MI) {
230 if (!getVarInfo(reg).removeKill(MI))
233 bool Removed = false;
234 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
235 MachineOperand &MO = MI->getOperand(i);
236 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
242 assert(Removed && "Register is not defined by this instruction!");
246 void getAnalysisUsage(AnalysisUsage &AU) const;
248 virtual void releaseMemory() {
252 /// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
254 VarInfo &getVarInfo(unsigned RegIdx);
256 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
257 MachineBasicBlock *BB);
258 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
259 MachineBasicBlock *BB,
260 std::vector<MachineBasicBlock*> &WorkList);
261 void HandleVirtRegDef(unsigned reg, MachineInstr *MI);
262 void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
266 } // End llvm namespace