1 //===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #ifndef LLVM_CODEGEN_LIVEVARIABLES_H
30 #define LLVM_CODEGEN_LIVEVARIABLES_H
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/ADT/BitVector.h"
40 class LiveVariables : public MachineFunctionPass {
42 /// VarInfo - This represents the regions where a virtual register is live in
43 /// the program. We represent this with three different pieces of
44 /// information: the instruction that uniquely defines the value, the set of
45 /// blocks the instruction is live into and live out of, and the set of
46 /// non-phi instructions that are the last users of the value.
48 /// In the common case where a value is defined and killed in the same block,
49 /// DefInst is the defining inst, there is one killing instruction, and
50 /// AliveBlocks is empty.
52 /// Otherwise, the value is live out of the block. If the value is live
53 /// across any blocks, these blocks are listed in AliveBlocks. Blocks where
54 /// the liveness range ends are not included in AliveBlocks, instead being
55 /// captured by the Kills set. In these blocks, the value is live into the
56 /// block (unless the value is defined and killed in the same block) and lives
57 /// until the specified instruction. Note that there cannot ever be a value
58 /// whose Kills set contains two instructions from the same basic block.
60 /// PHI nodes complicate things a bit. If a PHI node is the last user of a
61 /// value in one of its predecessor blocks, it is not listed in the kills set,
62 /// but does include the predecessor block in the AliveBlocks set (unless that
63 /// block also defines the value). This leads to the (perfectly sensical)
64 /// situation where a value is defined in a block, and the last use is a phi
65 /// node in the successor. In this case, DefInst will be the defining
66 /// instruction, AliveBlocks is empty (the value is not live across any
67 /// blocks) and Kills is empty (phi nodes are not included). This is sensical
68 /// because the value must be live to the end of the block, but is not live in
69 /// any successor blocks.
71 /// DefInst - The machine instruction that defines this register.
73 MachineInstr *DefInst;
75 /// AliveBlocks - Set of blocks of which this value is alive completely
76 /// through. This is a bit set which uses the basic block number as an
79 BitVector AliveBlocks;
81 /// Kills - List of MachineInstruction's which are the last use of this
82 /// virtual register (kill it) in their basic block.
84 std::vector<MachineInstr*> Kills;
86 VarInfo() : DefInst(0) {}
88 /// removeKill - Delete a kill corresponding to the specified
89 /// machine instruction. Returns true if there was a kill
90 /// corresponding to this instruction, false otherwise.
91 bool removeKill(MachineInstr *MI) {
92 for (std::vector<MachineInstr*>::iterator i = Kills.begin(),
93 e = Kills.end(); i != e; ++i)
105 /// VirtRegInfo - This list is a mapping from virtual register number to
106 /// variable information. FirstVirtualRegister is subtracted from the virtual
107 /// register number before indexing into this list.
109 std::vector<VarInfo> VirtRegInfo;
111 /// AllocatablePhysicalRegisters - This vector keeps track of which registers
112 /// are actually register allocatable by the target machine. We can not track
113 /// liveness for values that are not in this set.
115 BitVector AllocatablePhysicalRegisters;
117 private: // Intermediate data structures
118 const MRegisterInfo *RegInfo;
120 MachineInstr **PhysRegInfo;
123 typedef std::map<const MachineBasicBlock*,
124 std::vector<unsigned> > PHIVarInfoMap;
126 PHIVarInfoMap PHIVarInfo;
129 /// addRegisterKilled - We have determined MI kills a register. Look for the
130 /// operand that uses it and mark it as IsKill.
131 void addRegisterKilled(unsigned IncomingReg, MachineInstr *MI);
133 /// addRegisterDead - We have determined MI defined a register without a use.
134 /// Look for the operand that defines it and mark it as IsDead.
135 void addRegisterDead(unsigned IncomingReg, MachineInstr *MI);
137 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
138 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI);
140 /// analyzePHINodes - Gather information about the PHI nodes in here. In
141 /// particular, we want to map the variable information of a virtual
142 /// register which is used in a PHI node. We map that to the BB the vreg
144 void analyzePHINodes(const MachineFunction& Fn);
147 virtual bool runOnMachineFunction(MachineFunction &MF);
149 /// KillsRegister - Return true if the specified instruction kills the
150 /// specified register.
151 bool KillsRegister(MachineInstr *MI, unsigned Reg) const;
153 /// RegisterDefIsDead - Return true if the specified instruction defines the
154 /// specified register, but that definition is dead.
155 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
157 /// ModifiesRegister - Return true if the specified instruction modifies the
158 /// specified register.
159 bool ModifiesRegister(MachineInstr *MI, unsigned Reg) const;
161 //===--------------------------------------------------------------------===//
162 // API to update live variable information
164 /// instructionChanged - When the address of an instruction changes, this
165 /// method should be called so that live variables can update its internal
166 /// data structures. This removes the records for OldMI, transfering them to
167 /// the records for NewMI.
168 void instructionChanged(MachineInstr *OldMI, MachineInstr *NewMI);
170 /// addVirtualRegisterKilled - Add information about the fact that the
171 /// specified register is killed after being used by the specified
174 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI) {
175 addRegisterKilled(IncomingReg, MI);
176 getVarInfo(IncomingReg).Kills.push_back(MI);
179 /// removeVirtualRegisterKilled - Remove the specified virtual
180 /// register from the live variable information. Returns true if the
181 /// variable was marked as killed by the specified instruction,
183 bool removeVirtualRegisterKilled(unsigned reg,
184 MachineBasicBlock *MBB,
186 if (!getVarInfo(reg).removeKill(MI))
189 bool Removed = false;
190 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
191 MachineOperand &MO = MI->getOperand(i);
192 if (MO.isReg() && MO.isUse() && MO.getReg() == reg) {
199 assert(Removed && "Register is not used by this instruction!");
203 /// removeVirtualRegistersKilled - Remove all killed info for the specified
205 void removeVirtualRegistersKilled(MachineInstr *MI);
207 /// addVirtualRegisterDead - Add information about the fact that the specified
208 /// register is dead after being used by the specified instruction.
210 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI) {
211 addRegisterDead(IncomingReg, MI);
212 getVarInfo(IncomingReg).Kills.push_back(MI);
215 /// removeVirtualRegisterDead - Remove the specified virtual
216 /// register from the live variable information. Returns true if the
217 /// variable was marked dead at the specified instruction, false
219 bool removeVirtualRegisterDead(unsigned reg,
220 MachineBasicBlock *MBB,
222 if (!getVarInfo(reg).removeKill(MI))
225 bool Removed = false;
226 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
227 MachineOperand &MO = MI->getOperand(i);
228 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
234 assert(Removed && "Register is not defined by this instruction!");
238 /// removeVirtualRegistersDead - Remove all of the dead registers for the
239 /// specified instruction from the live variable information.
240 void removeVirtualRegistersDead(MachineInstr *MI);
242 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
243 AU.setPreservesAll();
246 virtual void releaseMemory() {
250 /// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
252 VarInfo &getVarInfo(unsigned RegIdx);
254 void MarkVirtRegAliveInBlock(VarInfo &VRInfo, MachineBasicBlock *BB);
255 void HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
259 } // End llvm namespace