1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass. Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' and there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
18 //===----------------------------------------------------------------------===//
20 #ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/LiveInterval.h"
25 #include "llvm/ADT/BitVector.h"
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/ADT/SmallPtrSet.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/Support/Allocator.h"
36 class MachineLoopInfo;
37 class TargetRegisterInfo;
38 class MachineRegisterInfo;
39 class TargetInstrInfo;
40 class TargetRegisterClass;
42 typedef std::pair<unsigned, MachineBasicBlock*> IdxMBBPair;
44 inline bool operator<(unsigned V, const IdxMBBPair &IM) {
48 inline bool operator<(const IdxMBBPair &IM, unsigned V) {
52 struct Idx2MBBCompare {
53 bool operator()(const IdxMBBPair &LHS, const IdxMBBPair &RHS) const {
54 return LHS.first < RHS.first;
58 class LiveIntervals : public MachineFunctionPass {
60 MachineRegisterInfo* mri_;
61 const TargetMachine* tm_;
62 const TargetRegisterInfo* tri_;
63 const TargetInstrInfo* tii_;
67 /// Special pool allocator for VNInfo's (LiveInterval val#).
69 BumpPtrAllocator VNInfoAllocator;
71 /// MBB2IdxMap - The indexes of the first and last instructions in the
72 /// specified basic block.
73 std::vector<std::pair<unsigned, unsigned> > MBB2IdxMap;
75 /// Idx2MBBMap - Sorted list of pairs of index of first instruction
77 std::vector<IdxMBBPair> Idx2MBBMap;
79 /// FunctionSize - The number of instructions present in the function
80 uint64_t FunctionSize;
82 typedef DenseMap<MachineInstr*, unsigned> Mi2IndexMap;
85 typedef std::vector<MachineInstr*> Index2MiMap;
88 typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap;
89 Reg2IntervalMap r2iMap_;
91 DenseMap<MachineBasicBlock*, unsigned> terminatorGaps;
93 BitVector allocatableRegs_;
95 std::vector<MachineInstr*> ClonedMIs;
97 typedef LiveInterval::InstrSlots InstrSlots;
100 static char ID; // Pass identification, replacement for typeid
101 LiveIntervals() : MachineFunctionPass(&ID) {}
103 static unsigned getBaseIndex(unsigned index) {
104 return index - (index % InstrSlots::NUM);
106 static unsigned getBoundaryIndex(unsigned index) {
107 return getBaseIndex(index + InstrSlots::NUM - 1);
109 static unsigned getLoadIndex(unsigned index) {
110 return getBaseIndex(index) + InstrSlots::LOAD;
112 static unsigned getUseIndex(unsigned index) {
113 return getBaseIndex(index) + InstrSlots::USE;
115 static unsigned getDefIndex(unsigned index) {
116 return getBaseIndex(index) + InstrSlots::DEF;
118 static unsigned getStoreIndex(unsigned index) {
119 return getBaseIndex(index) + InstrSlots::STORE;
122 static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth) {
123 return (isDef + isUse) * powf(10.0F, (float)loopDepth);
126 typedef Reg2IntervalMap::iterator iterator;
127 typedef Reg2IntervalMap::const_iterator const_iterator;
128 const_iterator begin() const { return r2iMap_.begin(); }
129 const_iterator end() const { return r2iMap_.end(); }
130 iterator begin() { return r2iMap_.begin(); }
131 iterator end() { return r2iMap_.end(); }
132 unsigned getNumIntervals() const { return (unsigned)r2iMap_.size(); }
134 LiveInterval &getInterval(unsigned reg) {
135 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
136 assert(I != r2iMap_.end() && "Interval does not exist for register");
140 const LiveInterval &getInterval(unsigned reg) const {
141 Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
142 assert(I != r2iMap_.end() && "Interval does not exist for register");
146 bool hasInterval(unsigned reg) const {
147 return r2iMap_.count(reg);
150 /// getMBBStartIdx - Return the base index of the first instruction in the
151 /// specified MachineBasicBlock.
152 unsigned getMBBStartIdx(MachineBasicBlock *MBB) const {
153 return getMBBStartIdx(MBB->getNumber());
155 unsigned getMBBStartIdx(unsigned MBBNo) const {
156 assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
157 return MBB2IdxMap[MBBNo].first;
160 /// getMBBEndIdx - Return the store index of the last instruction in the
161 /// specified MachineBasicBlock.
162 unsigned getMBBEndIdx(MachineBasicBlock *MBB) const {
163 return getMBBEndIdx(MBB->getNumber());
165 unsigned getMBBEndIdx(unsigned MBBNo) const {
166 assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
167 return MBB2IdxMap[MBBNo].second;
170 /// getScaledIntervalSize - get the size of an interval in "units,"
171 /// where every function is composed of one thousand units. This
172 /// measure scales properly with empty index slots in the function.
173 double getScaledIntervalSize(LiveInterval& I) {
174 return (1000.0 / InstrSlots::NUM * I.getSize()) / i2miMap_.size();
177 /// getApproximateInstructionCount - computes an estimate of the number
178 /// of instructions in a given LiveInterval.
179 unsigned getApproximateInstructionCount(LiveInterval& I) {
180 double IntervalPercentage = getScaledIntervalSize(I) / 1000.0;
181 return (unsigned)(IntervalPercentage * FunctionSize);
184 /// getMBBFromIndex - given an index in any instruction of an
185 /// MBB return a pointer the MBB
186 MachineBasicBlock* getMBBFromIndex(unsigned index) const {
187 std::vector<IdxMBBPair>::const_iterator I =
188 std::lower_bound(Idx2MBBMap.begin(), Idx2MBBMap.end(), index);
189 // Take the pair containing the index
190 std::vector<IdxMBBPair>::const_iterator J =
191 ((I != Idx2MBBMap.end() && I->first > index) ||
192 (I == Idx2MBBMap.end() && Idx2MBBMap.size()>0)) ? (I-1): I;
194 assert(J != Idx2MBBMap.end() && J->first < index+1 &&
195 index <= getMBBEndIdx(J->second) &&
196 "index does not correspond to an MBB");
200 /// getInstructionIndex - returns the base index of instr
201 unsigned getInstructionIndex(MachineInstr* instr) const {
202 Mi2IndexMap::const_iterator it = mi2iMap_.find(instr);
203 assert(it != mi2iMap_.end() && "Invalid instruction!");
207 /// getInstructionFromIndex - given an index in any slot of an
208 /// instruction return a pointer the instruction
209 MachineInstr* getInstructionFromIndex(unsigned index) const {
210 index /= InstrSlots::NUM; // convert index to vector index
211 assert(index < i2miMap_.size() &&
212 "index does not correspond to an instruction");
213 return i2miMap_[index];
216 /// hasGapBeforeInstr - Return true if the previous instruction slot,
217 /// i.e. Index - InstrSlots::NUM, is not occupied.
218 bool hasGapBeforeInstr(unsigned Index) {
219 Index = getBaseIndex(Index - InstrSlots::NUM);
220 return getInstructionFromIndex(Index) == 0;
223 /// hasGapAfterInstr - Return true if the successive instruction slot,
224 /// i.e. Index + InstrSlots::Num, is not occupied.
225 bool hasGapAfterInstr(unsigned Index) {
226 Index = getBaseIndex(Index + InstrSlots::NUM);
227 return getInstructionFromIndex(Index) == 0;
230 /// findGapBeforeInstr - Find an empty instruction slot before the
231 /// specified index. If "Furthest" is true, find one that's furthest
232 /// away from the index (but before any index that's occupied).
233 unsigned findGapBeforeInstr(unsigned Index, bool Furthest = false) {
234 Index = getBaseIndex(Index - InstrSlots::NUM);
235 if (getInstructionFromIndex(Index))
239 unsigned PrevIndex = getBaseIndex(Index - InstrSlots::NUM);
240 while (getInstructionFromIndex(Index)) {
242 PrevIndex = getBaseIndex(Index - InstrSlots::NUM);
247 /// InsertMachineInstrInMaps - Insert the specified machine instruction
248 /// into the instruction index map at the given index.
249 void InsertMachineInstrInMaps(MachineInstr *MI, unsigned Index) {
250 i2miMap_[Index / InstrSlots::NUM] = MI;
251 Mi2IndexMap::iterator it = mi2iMap_.find(MI);
252 assert(it == mi2iMap_.end() && "Already in map!");
253 mi2iMap_[MI] = Index;
256 /// conflictsWithPhysRegDef - Returns true if the specified register
257 /// is defined during the duration of the specified interval.
258 bool conflictsWithPhysRegDef(const LiveInterval &li, VirtRegMap &vrm,
261 /// conflictsWithPhysRegRef - Similar to conflictsWithPhysRegRef except
262 /// it can check use as well.
263 bool conflictsWithPhysRegRef(LiveInterval &li, unsigned Reg,
265 SmallPtrSet<MachineInstr*,32> &JoinedCopies);
267 /// findLiveInMBBs - Given a live range, if the value of the range
268 /// is live in any MBB returns true as well as the list of basic blocks
269 /// in which the value is live.
270 bool findLiveInMBBs(unsigned Start, unsigned End,
271 SmallVectorImpl<MachineBasicBlock*> &MBBs) const;
273 /// findReachableMBBs - Return a list MBB that can be reached via any
274 /// branch or fallthroughs. Return true if the list is not empty.
275 bool findReachableMBBs(unsigned Start, unsigned End,
276 SmallVectorImpl<MachineBasicBlock*> &MBBs) const;
280 LiveInterval &getOrCreateInterval(unsigned reg) {
281 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
282 if (I == r2iMap_.end())
283 I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first;
287 /// dupInterval - Duplicate a live interval. The caller is responsible for
288 /// managing the allocated memory.
289 LiveInterval *dupInterval(LiveInterval *li);
291 /// addLiveRangeToEndOfBlock - Given a register and an instruction,
292 /// adds a live range from that instruction to the end of its MBB.
293 LiveRange addLiveRangeToEndOfBlock(unsigned reg,
294 MachineInstr* startInst);
298 void removeInterval(unsigned Reg) {
299 DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.find(Reg);
304 /// isNotInMIMap - returns true if the specified machine instr has been
305 /// removed or was never entered in the map.
306 bool isNotInMIMap(MachineInstr* instr) const {
307 return !mi2iMap_.count(instr);
310 /// RemoveMachineInstrFromMaps - This marks the specified machine instr as
312 void RemoveMachineInstrFromMaps(MachineInstr *MI) {
313 // remove index -> MachineInstr and
314 // MachineInstr -> index mappings
315 Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
316 if (mi2i != mi2iMap_.end()) {
317 i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
318 mi2iMap_.erase(mi2i);
322 /// ReplaceMachineInstrInMaps - Replacing a machine instr with a new one in
323 /// maps used by register allocator.
324 void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
325 Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
326 if (mi2i == mi2iMap_.end())
328 i2miMap_[mi2i->second/InstrSlots::NUM] = NewMI;
329 Mi2IndexMap::iterator it = mi2iMap_.find(MI);
330 assert(it != mi2iMap_.end() && "Invalid instruction!");
331 unsigned Index = it->second;
333 mi2iMap_[NewMI] = Index;
336 BumpPtrAllocator& getVNInfoAllocator() { return VNInfoAllocator; }
338 /// getVNInfoSourceReg - Helper function that parses the specified VNInfo
339 /// copy field and returns the source register that defines it.
340 unsigned getVNInfoSourceReg(const VNInfo *VNI) const;
342 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
343 virtual void releaseMemory();
345 /// runOnMachineFunction - pass entry point
346 virtual bool runOnMachineFunction(MachineFunction&);
348 /// print - Implement the dump method.
349 virtual void print(std::ostream &O, const Module* = 0) const;
350 void print(std::ostream *O, const Module* M = 0) const {
354 /// addIntervalsForSpills - Create new intervals for spilled defs / uses of
355 /// the given interval. FIXME: It also returns the weight of the spill slot
356 /// (if any is created) by reference. This is temporary.
357 std::vector<LiveInterval*>
358 addIntervalsForSpills(const LiveInterval& i,
359 SmallVectorImpl<LiveInterval*> &SpillIs,
360 const MachineLoopInfo *loopInfo, VirtRegMap& vrm);
362 /// addIntervalsForSpillsFast - Quickly create new intervals for spilled
363 /// defs / uses without remat or splitting.
364 std::vector<LiveInterval*>
365 addIntervalsForSpillsFast(const LiveInterval &li,
366 const MachineLoopInfo *loopInfo, VirtRegMap &vrm);
368 /// spillPhysRegAroundRegDefsUses - Spill the specified physical register
369 /// around all defs and uses of the specified interval. Return true if it
370 /// was able to cut its interval.
371 bool spillPhysRegAroundRegDefsUses(const LiveInterval &li,
372 unsigned PhysReg, VirtRegMap &vrm);
374 /// isReMaterializable - Returns true if every definition of MI of every
375 /// val# of the specified interval is re-materializable. Also returns true
376 /// by reference if all of the defs are load instructions.
377 bool isReMaterializable(const LiveInterval &li,
378 SmallVectorImpl<LiveInterval*> &SpillIs,
381 /// isReMaterializable - Returns true if the definition MI of the specified
382 /// val# of the specified interval is re-materializable.
383 bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
386 /// getRepresentativeReg - Find the largest super register of the specified
387 /// physical register.
388 unsigned getRepresentativeReg(unsigned Reg) const;
390 /// getNumConflictsWithPhysReg - Return the number of uses and defs of the
391 /// specified interval that conflicts with the specified physical register.
392 unsigned getNumConflictsWithPhysReg(const LiveInterval &li,
393 unsigned PhysReg) const;
395 /// processImplicitDefs - Process IMPLICIT_DEF instructions. Add isUndef
396 /// marker to implicit_def defs and their uses.
397 void processImplicitDefs();
399 /// computeNumbering - Compute the index numbering.
400 void computeNumbering();
402 /// scaleNumbering - Rescale interval numbers to introduce gaps for new
404 void scaleNumbering(int factor);
406 /// intervalIsInOneMBB - Returns true if the specified interval is entirely
407 /// within a single basic block.
408 bool intervalIsInOneMBB(const LiveInterval &li) const;
411 /// computeIntervals - Compute live intervals.
412 void computeIntervals();
414 /// handleRegisterDef - update intervals for a register def
415 /// (calls handlePhysicalRegisterDef and
416 /// handleVirtualRegisterDef)
417 void handleRegisterDef(MachineBasicBlock *MBB,
418 MachineBasicBlock::iterator MI, unsigned MIIdx,
419 MachineOperand& MO, unsigned MOIdx);
421 /// handleVirtualRegisterDef - update intervals for a virtual
423 void handleVirtualRegisterDef(MachineBasicBlock *MBB,
424 MachineBasicBlock::iterator MI,
425 unsigned MIIdx, MachineOperand& MO,
426 unsigned MOIdx, LiveInterval& interval);
428 /// handlePhysicalRegisterDef - update intervals for a physical register
430 void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
431 MachineBasicBlock::iterator mi,
432 unsigned MIIdx, MachineOperand& MO,
433 LiveInterval &interval,
434 MachineInstr *CopyMI);
436 /// handleLiveInRegister - Create interval for a livein register.
437 void handleLiveInRegister(MachineBasicBlock* mbb,
439 LiveInterval &interval, bool isAlias = false);
441 /// getReMatImplicitUse - If the remat definition MI has one (for now, we
442 /// only allow one) virtual register operand, then its uses are implicitly
443 /// using the register. Returns the virtual register.
444 unsigned getReMatImplicitUse(const LiveInterval &li,
445 MachineInstr *MI) const;
447 /// isValNoAvailableAt - Return true if the val# of the specified interval
448 /// which reaches the given instruction also reaches the specified use
450 bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
451 unsigned UseIdx) const;
453 /// isReMaterializable - Returns true if the definition MI of the specified
454 /// val# of the specified interval is re-materializable. Also returns true
455 /// by reference if the def is a load.
456 bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
458 SmallVectorImpl<LiveInterval*> &SpillIs,
461 /// tryFoldMemoryOperand - Attempts to fold either a spill / restore from
462 /// slot / to reg or any rematerialized load into ith operand of specified
463 /// MI. If it is successul, MI is updated with the newly created MI and
465 bool tryFoldMemoryOperand(MachineInstr* &MI, VirtRegMap &vrm,
466 MachineInstr *DefMI, unsigned InstrIdx,
467 SmallVector<unsigned, 2> &Ops,
468 bool isSS, int Slot, unsigned Reg);
470 /// canFoldMemoryOperand - Return true if the specified load / store
471 /// folding is possible.
472 bool canFoldMemoryOperand(MachineInstr *MI,
473 SmallVector<unsigned, 2> &Ops,
474 bool ReMatLoadSS) const;
476 /// anyKillInMBBAfterIdx - Returns true if there is a kill of the specified
477 /// VNInfo that's after the specified index but is within the basic block.
478 bool anyKillInMBBAfterIdx(const LiveInterval &li, const VNInfo *VNI,
479 MachineBasicBlock *MBB, unsigned Idx) const;
481 /// hasAllocatableSuperReg - Return true if the specified physical register
482 /// has any super register that's allocatable.
483 bool hasAllocatableSuperReg(unsigned Reg) const;
485 /// SRInfo - Spill / restore info.
490 SRInfo(int i, unsigned vr, bool f) : index(i), vreg(vr), canFold(f) {};
493 bool alsoFoldARestore(int Id, int index, unsigned vr,
494 BitVector &RestoreMBBs,
495 DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
496 void eraseRestoreInfo(int Id, int index, unsigned vr,
497 BitVector &RestoreMBBs,
498 DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
500 /// handleSpilledImpDefs - Remove IMPLICIT_DEF instructions which are being
501 /// spilled and create empty intervals for their uses.
502 void handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm,
503 const TargetRegisterClass* rc,
504 std::vector<LiveInterval*> &NewLIs);
506 /// rewriteImplicitOps - Rewrite implicit use operands of MI (i.e. uses of
507 /// interval on to-be re-materialized operands of MI) with new register.
508 void rewriteImplicitOps(const LiveInterval &li,
509 MachineInstr *MI, unsigned NewVReg, VirtRegMap &vrm);
511 /// rewriteInstructionForSpills, rewriteInstructionsForSpills - Helper
512 /// functions for addIntervalsForSpills to rewrite uses / defs for the given
514 bool rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
515 bool TrySplit, unsigned index, unsigned end, MachineInstr *MI,
516 MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
517 bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
518 VirtRegMap &vrm, const TargetRegisterClass* rc,
519 SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
520 unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse,
521 DenseMap<unsigned,unsigned> &MBBVRegsMap,
522 std::vector<LiveInterval*> &NewLIs);
523 void rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
524 LiveInterval::Ranges::const_iterator &I,
525 MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
526 bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
527 VirtRegMap &vrm, const TargetRegisterClass* rc,
528 SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
529 BitVector &SpillMBBs,
530 DenseMap<unsigned,std::vector<SRInfo> > &SpillIdxes,
531 BitVector &RestoreMBBs,
532 DenseMap<unsigned,std::vector<SRInfo> > &RestoreIdxes,
533 DenseMap<unsigned,unsigned> &MBBVRegsMap,
534 std::vector<LiveInterval*> &NewLIs);
536 static LiveInterval* createInterval(unsigned Reg);
538 void printRegName(unsigned reg) const;
541 } // End llvm namespace