1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass. Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' and there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
18 //===----------------------------------------------------------------------===//
20 #ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
23 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/LiveInterval.h"
26 #include "llvm/CodeGen/SlotIndexes.h"
27 #include "llvm/ADT/BitVector.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/SmallPtrSet.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/Support/Allocator.h"
39 class MachineLoopInfo;
40 class TargetRegisterInfo;
41 class MachineRegisterInfo;
42 class TargetInstrInfo;
43 class TargetRegisterClass;
46 class LiveIntervals : public MachineFunctionPass {
48 MachineRegisterInfo* mri_;
49 const TargetMachine* tm_;
50 const TargetRegisterInfo* tri_;
51 const TargetInstrInfo* tii_;
54 SlotIndexes* indexes_;
56 /// Special pool allocator for VNInfo's (LiveInterval val#).
58 VNInfo::Allocator VNInfoAllocator;
60 typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap;
61 Reg2IntervalMap r2iMap_;
63 /// allocatableRegs_ - A bit vector of allocatable registers.
64 BitVector allocatableRegs_;
66 /// CloneMIs - A list of clones as result of re-materialization.
67 std::vector<MachineInstr*> CloneMIs;
70 static char ID; // Pass identification, replacement for typeid
71 LiveIntervals() : MachineFunctionPass(ID) {
72 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
75 // Calculate the spill weight to assign to a single instruction.
76 static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth);
78 // After summing the spill weights of all defs and uses, the final weight
79 // should be normalized, dividing the weight of the interval by its size.
80 // This encourages spilling of intervals that are large and have few uses,
81 // and discourages spilling of small intervals with many uses.
82 void normalizeSpillWeight(LiveInterval &li) {
83 li.weight /= getApproximateInstructionCount(li) + 25;
86 typedef Reg2IntervalMap::iterator iterator;
87 typedef Reg2IntervalMap::const_iterator const_iterator;
88 const_iterator begin() const { return r2iMap_.begin(); }
89 const_iterator end() const { return r2iMap_.end(); }
90 iterator begin() { return r2iMap_.begin(); }
91 iterator end() { return r2iMap_.end(); }
92 unsigned getNumIntervals() const { return (unsigned)r2iMap_.size(); }
94 LiveInterval &getInterval(unsigned reg) {
95 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
96 assert(I != r2iMap_.end() && "Interval does not exist for register");
100 const LiveInterval &getInterval(unsigned reg) const {
101 Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
102 assert(I != r2iMap_.end() && "Interval does not exist for register");
106 bool hasInterval(unsigned reg) const {
107 return r2iMap_.count(reg);
110 /// isAllocatable - is the physical register reg allocatable in the current
112 bool isAllocatable(unsigned reg) const {
113 return allocatableRegs_.test(reg);
116 /// getScaledIntervalSize - get the size of an interval in "units,"
117 /// where every function is composed of one thousand units. This
118 /// measure scales properly with empty index slots in the function.
119 double getScaledIntervalSize(LiveInterval& I) {
120 return (1000.0 * I.getSize()) / indexes_->getIndexesLength();
123 /// getFuncInstructionCount - Return the number of instructions in the
124 /// current function.
125 unsigned getFuncInstructionCount() {
126 return indexes_->getFunctionSize();
129 /// getApproximateInstructionCount - computes an estimate of the number
130 /// of instructions in a given LiveInterval.
131 unsigned getApproximateInstructionCount(LiveInterval& I) {
132 double IntervalPercentage = getScaledIntervalSize(I) / 1000.0;
133 return (unsigned)(IntervalPercentage * indexes_->getFunctionSize());
136 /// conflictsWithPhysReg - Returns true if the specified register is used or
137 /// defined during the duration of the specified interval. Copies to and
138 /// from li.reg are allowed. This method is only able to analyze simple
139 /// ranges that stay within a single basic block. Anything else is
140 /// considered a conflict.
141 bool conflictsWithPhysReg(const LiveInterval &li, VirtRegMap &vrm,
144 /// conflictsWithAliasRef - Similar to conflictsWithPhysRegRef except
145 /// it checks for alias uses and defs.
146 bool conflictsWithAliasRef(LiveInterval &li, unsigned Reg,
147 SmallPtrSet<MachineInstr*,32> &JoinedCopies);
150 LiveInterval &getOrCreateInterval(unsigned reg) {
151 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
152 if (I == r2iMap_.end())
153 I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first;
157 /// dupInterval - Duplicate a live interval. The caller is responsible for
158 /// managing the allocated memory.
159 LiveInterval *dupInterval(LiveInterval *li);
161 /// addLiveRangeToEndOfBlock - Given a register and an instruction,
162 /// adds a live range from that instruction to the end of its MBB.
163 LiveRange addLiveRangeToEndOfBlock(unsigned reg,
164 MachineInstr* startInst);
166 /// shrinkToUses - After removing some uses of a register, shrink its live
167 /// range to just the remaining uses. This method does not compute reaching
168 /// defs for new uses, and it doesn't remove dead defs.
169 /// Dead PHIDef values are marked as unused.
170 void shrinkToUses(LiveInterval *li);
174 void removeInterval(unsigned Reg) {
175 DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.find(Reg);
180 SlotIndexes *getSlotIndexes() const {
184 SlotIndex getZeroIndex() const {
185 return indexes_->getZeroIndex();
188 SlotIndex getInvalidIndex() const {
189 return indexes_->getInvalidIndex();
192 /// isNotInMIMap - returns true if the specified machine instr has been
193 /// removed or was never entered in the map.
194 bool isNotInMIMap(const MachineInstr* Instr) const {
195 return !indexes_->hasIndex(Instr);
198 /// Returns the base index of the given instruction.
199 SlotIndex getInstructionIndex(const MachineInstr *instr) const {
200 return indexes_->getInstructionIndex(instr);
203 /// Returns the instruction associated with the given index.
204 MachineInstr* getInstructionFromIndex(SlotIndex index) const {
205 return indexes_->getInstructionFromIndex(index);
208 /// Return the first index in the given basic block.
209 SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
210 return indexes_->getMBBStartIdx(mbb);
213 /// Return the last index in the given basic block.
214 SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
215 return indexes_->getMBBEndIdx(mbb);
218 bool isLiveInToMBB(const LiveInterval &li,
219 const MachineBasicBlock *mbb) const {
220 return li.liveAt(getMBBStartIdx(mbb));
223 LiveRange* findEnteringRange(LiveInterval &li,
224 const MachineBasicBlock *mbb) {
225 return li.getLiveRangeContaining(getMBBStartIdx(mbb));
228 bool isLiveOutOfMBB(const LiveInterval &li,
229 const MachineBasicBlock *mbb) const {
230 return li.liveAt(getMBBEndIdx(mbb).getPrevSlot());
233 LiveRange* findExitingRange(LiveInterval &li,
234 const MachineBasicBlock *mbb) {
235 return li.getLiveRangeContaining(getMBBEndIdx(mbb).getPrevSlot());
238 MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
239 return indexes_->getMBBFromIndex(index);
242 SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
243 return indexes_->insertMachineInstrInMaps(MI);
246 void RemoveMachineInstrFromMaps(MachineInstr *MI) {
247 indexes_->removeMachineInstrFromMaps(MI);
250 void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
251 indexes_->replaceMachineInstrInMaps(MI, NewMI);
254 void InsertMBBInMaps(MachineBasicBlock *MBB) {
255 indexes_->insertMBBInMaps(MBB);
258 bool findLiveInMBBs(SlotIndex Start, SlotIndex End,
259 SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
260 return indexes_->findLiveInMBBs(Start, End, MBBs);
264 indexes_->renumberIndexes();
267 VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
269 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
270 virtual void releaseMemory();
272 /// runOnMachineFunction - pass entry point
273 virtual bool runOnMachineFunction(MachineFunction&);
275 /// print - Implement the dump method.
276 virtual void print(raw_ostream &O, const Module* = 0) const;
278 /// addIntervalsForSpills - Create new intervals for spilled defs / uses of
279 /// the given interval. FIXME: It also returns the weight of the spill slot
280 /// (if any is created) by reference. This is temporary.
281 std::vector<LiveInterval*>
282 addIntervalsForSpills(const LiveInterval& i,
283 const SmallVectorImpl<LiveInterval*> &SpillIs,
284 const MachineLoopInfo *loopInfo, VirtRegMap& vrm);
286 /// spillPhysRegAroundRegDefsUses - Spill the specified physical register
287 /// around all defs and uses of the specified interval. Return true if it
288 /// was able to cut its interval.
289 bool spillPhysRegAroundRegDefsUses(const LiveInterval &li,
290 unsigned PhysReg, VirtRegMap &vrm);
292 /// isReMaterializable - Returns true if every definition of MI of every
293 /// val# of the specified interval is re-materializable. Also returns true
294 /// by reference if all of the defs are load instructions.
295 bool isReMaterializable(const LiveInterval &li,
296 const SmallVectorImpl<LiveInterval*> &SpillIs,
299 /// isReMaterializable - Returns true if the definition MI of the specified
300 /// val# of the specified interval is re-materializable.
301 bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
304 /// getRepresentativeReg - Find the largest super register of the specified
305 /// physical register.
306 unsigned getRepresentativeReg(unsigned Reg) const;
308 /// getNumConflictsWithPhysReg - Return the number of uses and defs of the
309 /// specified interval that conflicts with the specified physical register.
310 unsigned getNumConflictsWithPhysReg(const LiveInterval &li,
311 unsigned PhysReg) const;
313 /// intervalIsInOneMBB - Returns true if the specified interval is entirely
314 /// within a single basic block.
315 bool intervalIsInOneMBB(const LiveInterval &li) const;
317 /// getLastSplitPoint - Return the last possible insertion point in mbb for
318 /// spilling and splitting code. This is the first terminator, or the call
319 /// instruction if li is live into a landing pad successor.
320 MachineBasicBlock::iterator getLastSplitPoint(const LiveInterval &li,
321 MachineBasicBlock *mbb);
324 /// computeIntervals - Compute live intervals.
325 void computeIntervals();
327 /// handleRegisterDef - update intervals for a register def
328 /// (calls handlePhysicalRegisterDef and
329 /// handleVirtualRegisterDef)
330 void handleRegisterDef(MachineBasicBlock *MBB,
331 MachineBasicBlock::iterator MI,
333 MachineOperand& MO, unsigned MOIdx);
335 /// isPartialRedef - Return true if the specified def at the specific index
336 /// is partially re-defining the specified live interval. A common case of
337 /// this is a definition of the sub-register.
338 bool isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
339 LiveInterval &interval);
341 /// handleVirtualRegisterDef - update intervals for a virtual
343 void handleVirtualRegisterDef(MachineBasicBlock *MBB,
344 MachineBasicBlock::iterator MI,
345 SlotIndex MIIdx, MachineOperand& MO,
347 LiveInterval& interval);
349 /// handlePhysicalRegisterDef - update intervals for a physical register
351 void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
352 MachineBasicBlock::iterator mi,
353 SlotIndex MIIdx, MachineOperand& MO,
354 LiveInterval &interval,
355 MachineInstr *CopyMI);
357 /// handleLiveInRegister - Create interval for a livein register.
358 void handleLiveInRegister(MachineBasicBlock* mbb,
360 LiveInterval &interval, bool isAlias = false);
362 /// getReMatImplicitUse - If the remat definition MI has one (for now, we
363 /// only allow one) virtual register operand, then its uses are implicitly
364 /// using the register. Returns the virtual register.
365 unsigned getReMatImplicitUse(const LiveInterval &li,
366 MachineInstr *MI) const;
368 /// isValNoAvailableAt - Return true if the val# of the specified interval
369 /// which reaches the given instruction also reaches the specified use
371 bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
372 SlotIndex UseIdx) const;
374 /// isReMaterializable - Returns true if the definition MI of the specified
375 /// val# of the specified interval is re-materializable. Also returns true
376 /// by reference if the def is a load.
377 bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
379 const SmallVectorImpl<LiveInterval*> &SpillIs,
382 /// tryFoldMemoryOperand - Attempts to fold either a spill / restore from
383 /// slot / to reg or any rematerialized load into ith operand of specified
384 /// MI. If it is successul, MI is updated with the newly created MI and
386 bool tryFoldMemoryOperand(MachineInstr* &MI, VirtRegMap &vrm,
387 MachineInstr *DefMI, SlotIndex InstrIdx,
388 SmallVector<unsigned, 2> &Ops,
389 bool isSS, int FrameIndex, unsigned Reg);
391 /// canFoldMemoryOperand - Return true if the specified load / store
392 /// folding is possible.
393 bool canFoldMemoryOperand(MachineInstr *MI,
394 SmallVector<unsigned, 2> &Ops,
395 bool ReMatLoadSS) const;
397 /// anyKillInMBBAfterIdx - Returns true if there is a kill of the specified
398 /// VNInfo that's after the specified index but is within the basic block.
399 bool anyKillInMBBAfterIdx(const LiveInterval &li, const VNInfo *VNI,
400 MachineBasicBlock *MBB,
401 SlotIndex Idx) const;
403 /// hasAllocatableSuperReg - Return true if the specified physical register
404 /// has any super register that's allocatable.
405 bool hasAllocatableSuperReg(unsigned Reg) const;
407 /// SRInfo - Spill / restore info.
412 SRInfo(SlotIndex i, unsigned vr, bool f)
413 : index(i), vreg(vr), canFold(f) {}
416 bool alsoFoldARestore(int Id, SlotIndex index, unsigned vr,
417 BitVector &RestoreMBBs,
418 DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
419 void eraseRestoreInfo(int Id, SlotIndex index, unsigned vr,
420 BitVector &RestoreMBBs,
421 DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
423 /// handleSpilledImpDefs - Remove IMPLICIT_DEF instructions which are being
424 /// spilled and create empty intervals for their uses.
425 void handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm,
426 const TargetRegisterClass* rc,
427 std::vector<LiveInterval*> &NewLIs);
429 /// rewriteImplicitOps - Rewrite implicit use operands of MI (i.e. uses of
430 /// interval on to-be re-materialized operands of MI) with new register.
431 void rewriteImplicitOps(const LiveInterval &li,
432 MachineInstr *MI, unsigned NewVReg, VirtRegMap &vrm);
434 /// rewriteInstructionForSpills, rewriteInstructionsForSpills - Helper
435 /// functions for addIntervalsForSpills to rewrite uses / defs for the given
437 bool rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
438 bool TrySplit, SlotIndex index, SlotIndex end,
439 MachineInstr *MI, MachineInstr *OrigDefMI, MachineInstr *DefMI,
440 unsigned Slot, int LdSlot,
441 bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
442 VirtRegMap &vrm, const TargetRegisterClass* rc,
443 SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
444 unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse,
445 DenseMap<unsigned,unsigned> &MBBVRegsMap,
446 std::vector<LiveInterval*> &NewLIs);
447 void rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
448 LiveInterval::Ranges::const_iterator &I,
449 MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
450 bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
451 VirtRegMap &vrm, const TargetRegisterClass* rc,
452 SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
453 BitVector &SpillMBBs,
454 DenseMap<unsigned,std::vector<SRInfo> > &SpillIdxes,
455 BitVector &RestoreMBBs,
456 DenseMap<unsigned,std::vector<SRInfo> > &RestoreIdxes,
457 DenseMap<unsigned,unsigned> &MBBVRegsMap,
458 std::vector<LiveInterval*> &NewLIs);
460 // Normalize the spill weight of all the intervals in NewLIs.
461 void normalizeSpillWeights(std::vector<LiveInterval*> &NewLIs);
463 static LiveInterval* createInterval(unsigned Reg);
465 void printInstrs(raw_ostream &O) const;
466 void dumpInstrs() const;
468 } // End llvm namespace