1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass. Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' abd there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
18 //===----------------------------------------------------------------------===//
20 #ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/LiveInterval.h"
25 #include "llvm/ADT/BitVector.h"
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/ADT/IndexedMap.h"
28 #include "llvm/ADT/SmallPtrSet.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/Support/Allocator.h"
36 class TargetInstrInfo;
37 class TargetRegisterClass;
40 class LiveIntervals : public MachineFunctionPass {
42 const TargetMachine* tm_;
43 const MRegisterInfo* mri_;
44 const TargetInstrInfo* tii_;
47 /// Special pool allocator for VNInfo's (LiveInterval val#).
49 BumpPtrAllocator VNInfoAllocator;
51 /// MBB2IdxMap - The indexes of the first and last instructions in the
52 /// specified basic block.
53 std::vector<std::pair<unsigned, unsigned> > MBB2IdxMap;
55 typedef std::map<MachineInstr*, unsigned> Mi2IndexMap;
58 typedef std::vector<MachineInstr*> Index2MiMap;
61 typedef std::map<unsigned, LiveInterval> Reg2IntervalMap;
62 Reg2IntervalMap r2iMap_;
64 BitVector allocatableRegs_;
66 std::vector<MachineInstr*> ClonedMIs;
69 static char ID; // Pass identification, replacement for typeid
70 LiveIntervals() : MachineFunctionPass((intptr_t)&ID) {}
82 static unsigned getBaseIndex(unsigned index) {
83 return index - (index % InstrSlots::NUM);
85 static unsigned getBoundaryIndex(unsigned index) {
86 return getBaseIndex(index + InstrSlots::NUM - 1);
88 static unsigned getLoadIndex(unsigned index) {
89 return getBaseIndex(index) + InstrSlots::LOAD;
91 static unsigned getUseIndex(unsigned index) {
92 return getBaseIndex(index) + InstrSlots::USE;
94 static unsigned getDefIndex(unsigned index) {
95 return getBaseIndex(index) + InstrSlots::DEF;
97 static unsigned getStoreIndex(unsigned index) {
98 return getBaseIndex(index) + InstrSlots::STORE;
101 typedef Reg2IntervalMap::iterator iterator;
102 typedef Reg2IntervalMap::const_iterator const_iterator;
103 const_iterator begin() const { return r2iMap_.begin(); }
104 const_iterator end() const { return r2iMap_.end(); }
105 iterator begin() { return r2iMap_.begin(); }
106 iterator end() { return r2iMap_.end(); }
107 unsigned getNumIntervals() const { return r2iMap_.size(); }
109 LiveInterval &getInterval(unsigned reg) {
110 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
111 assert(I != r2iMap_.end() && "Interval does not exist for register");
115 const LiveInterval &getInterval(unsigned reg) const {
116 Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
117 assert(I != r2iMap_.end() && "Interval does not exist for register");
121 bool hasInterval(unsigned reg) const {
122 return r2iMap_.count(reg);
125 /// getMBBStartIdx - Return the base index of the first instruction in the
126 /// specified MachineBasicBlock.
127 unsigned getMBBStartIdx(MachineBasicBlock *MBB) const {
128 return getMBBStartIdx(MBB->getNumber());
130 unsigned getMBBStartIdx(unsigned MBBNo) const {
131 assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
132 return MBB2IdxMap[MBBNo].first;
135 /// getMBBEndIdx - Return the store index of the last instruction in the
136 /// specified MachineBasicBlock.
137 unsigned getMBBEndIdx(MachineBasicBlock *MBB) const {
138 return getMBBEndIdx(MBB->getNumber());
140 unsigned getMBBEndIdx(unsigned MBBNo) const {
141 assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
142 return MBB2IdxMap[MBBNo].second;
145 /// getInstructionIndex - returns the base index of instr
146 unsigned getInstructionIndex(MachineInstr* instr) const {
147 Mi2IndexMap::const_iterator it = mi2iMap_.find(instr);
148 assert(it != mi2iMap_.end() && "Invalid instruction!");
152 /// getInstructionFromIndex - given an index in any slot of an
153 /// instruction return a pointer the instruction
154 MachineInstr* getInstructionFromIndex(unsigned index) const {
155 index /= InstrSlots::NUM; // convert index to vector index
156 assert(index < i2miMap_.size() &&
157 "index does not correspond to an instruction");
158 return i2miMap_[index];
163 LiveInterval &getOrCreateInterval(unsigned reg) {
164 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
165 if (I == r2iMap_.end())
166 I = r2iMap_.insert(I, std::make_pair(reg, createInterval(reg)));
170 /// CreateNewLiveInterval - Create a new live interval with the given live
171 /// ranges. The new live interval will have an infinite spill weight.
172 LiveInterval &CreateNewLiveInterval(const LiveInterval *LI,
173 const std::vector<LiveRange> &LRs);
175 std::vector<LiveInterval*> addIntervalsForSpills(const LiveInterval& i,
176 VirtRegMap& vrm, unsigned reg);
180 void removeInterval(unsigned Reg) {
184 /// isRemoved - returns true if the specified machine instr has been
186 bool isRemoved(MachineInstr* instr) const {
187 return !mi2iMap_.count(instr);
190 /// RemoveMachineInstrFromMaps - This marks the specified machine instr as
192 void RemoveMachineInstrFromMaps(MachineInstr *MI) {
193 // remove index -> MachineInstr and
194 // MachineInstr -> index mappings
195 Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
196 if (mi2i != mi2iMap_.end()) {
197 i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
198 mi2iMap_.erase(mi2i);
202 BumpPtrAllocator& getVNInfoAllocator() { return VNInfoAllocator; }
204 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
205 virtual void releaseMemory();
207 /// runOnMachineFunction - pass entry point
208 virtual bool runOnMachineFunction(MachineFunction&);
210 /// print - Implement the dump method.
211 virtual void print(std::ostream &O, const Module* = 0) const;
212 void print(std::ostream *O, const Module* M = 0) const {
217 /// computeIntervals - Compute live intervals.
218 void computeIntervals();
220 /// handleRegisterDef - update intervals for a register def
221 /// (calls handlePhysicalRegisterDef and
222 /// handleVirtualRegisterDef)
223 void handleRegisterDef(MachineBasicBlock *MBB,
224 MachineBasicBlock::iterator MI, unsigned MIIdx,
227 /// handleVirtualRegisterDef - update intervals for a virtual
229 void handleVirtualRegisterDef(MachineBasicBlock *MBB,
230 MachineBasicBlock::iterator MI,
232 LiveInterval& interval);
234 /// handlePhysicalRegisterDef - update intervals for a physical register
236 void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
237 MachineBasicBlock::iterator mi,
239 LiveInterval &interval,
242 /// handleLiveInRegister - Create interval for a livein register.
243 void handleLiveInRegister(MachineBasicBlock* mbb,
245 LiveInterval &interval, bool isAlias = false);
247 /// isReMaterializable - Returns true if the definition MI of the specified
248 /// val# of the specified interval is re-materializable.
249 bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
252 /// tryFoldMemoryOperand - Attempts to fold either a spill / restore from
253 /// slot / to reg or any rematerialized load into ith operand of specified
254 /// MI. If it is successul, MI is updated with the newly created MI and
256 bool tryFoldMemoryOperand(MachineInstr* &MI, VirtRegMap &vrm,
257 unsigned index, unsigned i, bool isSS,
258 MachineInstr *DefMI, int slot, unsigned reg);
260 static LiveInterval createInterval(unsigned Reg);
262 void printRegName(unsigned reg) const;
265 } // End llvm namespace