1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass. Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' and there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
18 //===----------------------------------------------------------------------===//
20 #ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
23 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/MachineFunctionPass.h"
25 #include "llvm/CodeGen/LiveInterval.h"
26 #include "llvm/CodeGen/SlotIndexes.h"
27 #include "llvm/ADT/BitVector.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/SmallPtrSet.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/Support/Allocator.h"
39 class MachineLoopInfo;
40 class TargetRegisterInfo;
41 class MachineRegisterInfo;
42 class TargetInstrInfo;
43 class TargetRegisterClass;
46 class LiveIntervals : public MachineFunctionPass {
48 MachineRegisterInfo* mri_;
49 const TargetMachine* tm_;
50 const TargetRegisterInfo* tri_;
51 const TargetInstrInfo* tii_;
54 SlotIndexes* indexes_;
56 /// Special pool allocator for VNInfo's (LiveInterval val#).
58 VNInfo::Allocator VNInfoAllocator;
60 typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap;
61 Reg2IntervalMap r2iMap_;
63 /// allocatableRegs_ - A bit vector of allocatable registers.
64 BitVector allocatableRegs_;
66 /// reservedRegs_ - A bit vector of reserved registers.
67 BitVector reservedRegs_;
69 /// RegMaskSlots - Sorted list of instructions with register mask operands.
70 /// Always use the 'r' slot, RegMasks are normal clobbers, not early
72 SmallVector<SlotIndex, 8> RegMaskSlots;
74 /// RegMaskBits - This vector is parallel to RegMaskSlots, it holds a
75 /// pointer to the corresponding register mask. This pointer can be
78 /// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
79 /// unsigned OpNum = findRegMaskOperand(MI);
80 /// RegMaskBits[N] = MI->getOperand(OpNum).getRegMask();
82 /// This is kept in a separate vector partly because some standard
83 /// libraries don't support lower_bound() with mixed objects, partly to
84 /// improve locality when searching in RegMaskSlots.
85 /// Also see the comment in LiveInterval::find().
86 SmallVector<const uint32_t*, 8> RegMaskBits;
88 /// For each basic block number, keep (begin, size) pairs indexing into the
89 /// RegMaskSlots and RegMaskBits arrays.
90 /// Note that basic block numbers may not be layout contiguous, that's why
91 /// we can't just keep track of the first register mask in each basic
93 SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks;
96 static char ID; // Pass identification, replacement for typeid
97 LiveIntervals() : MachineFunctionPass(ID) {
98 initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
101 // Calculate the spill weight to assign to a single instruction.
102 static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth);
104 typedef Reg2IntervalMap::iterator iterator;
105 typedef Reg2IntervalMap::const_iterator const_iterator;
106 const_iterator begin() const { return r2iMap_.begin(); }
107 const_iterator end() const { return r2iMap_.end(); }
108 iterator begin() { return r2iMap_.begin(); }
109 iterator end() { return r2iMap_.end(); }
110 unsigned getNumIntervals() const { return (unsigned)r2iMap_.size(); }
112 LiveInterval &getInterval(unsigned reg) {
113 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
114 assert(I != r2iMap_.end() && "Interval does not exist for register");
118 const LiveInterval &getInterval(unsigned reg) const {
119 Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
120 assert(I != r2iMap_.end() && "Interval does not exist for register");
124 bool hasInterval(unsigned reg) const {
125 return r2iMap_.count(reg);
128 /// isAllocatable - is the physical register reg allocatable in the current
130 bool isAllocatable(unsigned reg) const {
131 return allocatableRegs_.test(reg);
134 /// isReserved - is the physical register reg reserved in the current
136 bool isReserved(unsigned reg) const {
137 return reservedRegs_.test(reg);
140 /// getApproximateInstructionCount - computes an estimate of the number
141 /// of instructions in a given LiveInterval.
142 unsigned getApproximateInstructionCount(LiveInterval& I) {
143 return I.getSize()/SlotIndex::InstrDist;
147 LiveInterval &getOrCreateInterval(unsigned reg) {
148 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
149 if (I == r2iMap_.end())
150 I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first;
154 /// dupInterval - Duplicate a live interval. The caller is responsible for
155 /// managing the allocated memory.
156 LiveInterval *dupInterval(LiveInterval *li);
158 /// addLiveRangeToEndOfBlock - Given a register and an instruction,
159 /// adds a live range from that instruction to the end of its MBB.
160 LiveRange addLiveRangeToEndOfBlock(unsigned reg,
161 MachineInstr* startInst);
163 /// shrinkToUses - After removing some uses of a register, shrink its live
164 /// range to just the remaining uses. This method does not compute reaching
165 /// defs for new uses, and it doesn't remove dead defs.
166 /// Dead PHIDef values are marked as unused.
167 /// New dead machine instructions are added to the dead vector.
168 /// Return true if the interval may have been separated into multiple
169 /// connected components.
170 bool shrinkToUses(LiveInterval *li,
171 SmallVectorImpl<MachineInstr*> *dead = 0);
175 void removeInterval(unsigned Reg) {
176 DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.find(Reg);
181 SlotIndexes *getSlotIndexes() const {
185 /// isNotInMIMap - returns true if the specified machine instr has been
186 /// removed or was never entered in the map.
187 bool isNotInMIMap(const MachineInstr* Instr) const {
188 return !indexes_->hasIndex(Instr);
191 /// Returns the base index of the given instruction.
192 SlotIndex getInstructionIndex(const MachineInstr *instr) const {
193 return indexes_->getInstructionIndex(instr);
196 /// Returns the instruction associated with the given index.
197 MachineInstr* getInstructionFromIndex(SlotIndex index) const {
198 return indexes_->getInstructionFromIndex(index);
201 /// Return the first index in the given basic block.
202 SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
203 return indexes_->getMBBStartIdx(mbb);
206 /// Return the last index in the given basic block.
207 SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
208 return indexes_->getMBBEndIdx(mbb);
211 bool isLiveInToMBB(const LiveInterval &li,
212 const MachineBasicBlock *mbb) const {
213 return li.liveAt(getMBBStartIdx(mbb));
216 bool isLiveOutOfMBB(const LiveInterval &li,
217 const MachineBasicBlock *mbb) const {
218 return li.liveAt(getMBBEndIdx(mbb).getPrevSlot());
221 MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
222 return indexes_->getMBBFromIndex(index);
225 SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
226 return indexes_->insertMachineInstrInMaps(MI);
229 void RemoveMachineInstrFromMaps(MachineInstr *MI) {
230 indexes_->removeMachineInstrFromMaps(MI);
233 void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
234 indexes_->replaceMachineInstrInMaps(MI, NewMI);
237 bool findLiveInMBBs(SlotIndex Start, SlotIndex End,
238 SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
239 return indexes_->findLiveInMBBs(Start, End, MBBs);
242 VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
244 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
245 virtual void releaseMemory();
247 /// runOnMachineFunction - pass entry point
248 virtual bool runOnMachineFunction(MachineFunction&);
250 /// print - Implement the dump method.
251 virtual void print(raw_ostream &O, const Module* = 0) const;
253 /// isReMaterializable - Returns true if every definition of MI of every
254 /// val# of the specified interval is re-materializable. Also returns true
255 /// by reference if all of the defs are load instructions.
256 bool isReMaterializable(const LiveInterval &li,
257 const SmallVectorImpl<LiveInterval*> *SpillIs,
260 /// intervalIsInOneMBB - If LI is confined to a single basic block, return
261 /// a pointer to that block. If LI is live in to or out of any block,
263 MachineBasicBlock *intervalIsInOneMBB(const LiveInterval &LI) const;
265 /// addKillFlags - Add kill flags to any instruction that kills a virtual
269 /// handleMove - call this method to notify LiveIntervals that
270 /// instruction 'mi' has been moved within a basic block. This will update
271 /// the live intervals for all operands of mi. Moves between basic blocks
272 /// are not supported.
273 void handleMove(MachineInstr* MI);
275 /// moveIntoBundle - Update intervals for operands of MI so that they
276 /// begin/end on the SlotIndex for BundleStart.
278 /// Requires MI and BundleStart to have SlotIndexes, and assumes
279 /// existing liveness is accurate. BundleStart should be the first
280 /// instruction in the Bundle.
281 void handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart);
283 // Register mask functions.
285 // Machine instructions may use a register mask operand to indicate that a
286 // large number of registers are clobbered by the instruction. This is
287 // typically used for calls.
289 // For compile time performance reasons, these clobbers are not recorded in
290 // the live intervals for individual physical registers. Instead,
291 // LiveIntervalAnalysis maintains a sorted list of instructions with
292 // register mask operands.
294 /// getRegMaskSlots - Returns a sorted array of slot indices of all
295 /// instructions with register mask operands.
296 ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; }
298 /// getRegMaskSlotsInBlock - Returns a sorted array of slot indices of all
299 /// instructions with register mask operands in the basic block numbered
301 ArrayRef<SlotIndex> getRegMaskSlotsInBlock(unsigned MBBNum) const {
302 std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
303 return getRegMaskSlots().slice(P.first, P.second);
306 /// getRegMaskBits() - Returns an array of register mask pointers
307 /// corresponding to getRegMaskSlots().
308 ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; }
310 /// getRegMaskBitsInBlock - Returns an array of mask pointers corresponding
311 /// to getRegMaskSlotsInBlock(MBBNum).
312 ArrayRef<const uint32_t*> getRegMaskBitsInBlock(unsigned MBBNum) const {
313 std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
314 return getRegMaskBits().slice(P.first, P.second);
317 /// checkRegMaskInterference - Test if LI is live across any register mask
318 /// instructions, and compute a bit mask of physical registers that are not
319 /// clobbered by any of them.
321 /// Returns false if LI doesn't cross any register mask instructions. In
322 /// that case, the bit vector is not filled in.
323 bool checkRegMaskInterference(LiveInterval &LI,
324 BitVector &UsableRegs);
327 /// computeIntervals - Compute live intervals.
328 void computeIntervals();
330 /// handleRegisterDef - update intervals for a register def
331 /// (calls handlePhysicalRegisterDef and
332 /// handleVirtualRegisterDef)
333 void handleRegisterDef(MachineBasicBlock *MBB,
334 MachineBasicBlock::iterator MI,
336 MachineOperand& MO, unsigned MOIdx);
338 /// isPartialRedef - Return true if the specified def at the specific index
339 /// is partially re-defining the specified live interval. A common case of
340 /// this is a definition of the sub-register.
341 bool isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
342 LiveInterval &interval);
344 /// handleVirtualRegisterDef - update intervals for a virtual
346 void handleVirtualRegisterDef(MachineBasicBlock *MBB,
347 MachineBasicBlock::iterator MI,
348 SlotIndex MIIdx, MachineOperand& MO,
350 LiveInterval& interval);
352 /// handlePhysicalRegisterDef - update intervals for a physical register
354 void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
355 MachineBasicBlock::iterator mi,
356 SlotIndex MIIdx, MachineOperand& MO,
357 LiveInterval &interval);
359 /// handleLiveInRegister - Create interval for a livein register.
360 void handleLiveInRegister(MachineBasicBlock* mbb,
362 LiveInterval &interval);
364 /// getReMatImplicitUse - If the remat definition MI has one (for now, we
365 /// only allow one) virtual register operand, then its uses are implicitly
366 /// using the register. Returns the virtual register.
367 unsigned getReMatImplicitUse(const LiveInterval &li,
368 MachineInstr *MI) const;
370 /// isValNoAvailableAt - Return true if the val# of the specified interval
371 /// which reaches the given instruction also reaches the specified use
373 bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
374 SlotIndex UseIdx) const;
376 /// isReMaterializable - Returns true if the definition MI of the specified
377 /// val# of the specified interval is re-materializable. Also returns true
378 /// by reference if the def is a load.
379 bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
381 const SmallVectorImpl<LiveInterval*> *SpillIs,
384 static LiveInterval* createInterval(unsigned Reg);
386 void printInstrs(raw_ostream &O) const;
387 void dumpInstrs() const;
391 } // End llvm namespace