1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass. Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' abd there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
18 //===----------------------------------------------------------------------===//
20 #ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
23 #include "llvm/CodeGen/MachineFunctionPass.h"
24 #include "llvm/CodeGen/LiveInterval.h"
25 #include "llvm/ADT/BitVector.h"
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/ADT/SmallPtrSet.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/Support/Allocator.h"
37 class TargetInstrInfo;
38 class TargetRegisterClass;
40 typedef std::pair<unsigned, MachineBasicBlock*> IdxMBBPair;
42 class LiveIntervals : public MachineFunctionPass {
44 const TargetMachine* tm_;
45 const MRegisterInfo* mri_;
46 const TargetInstrInfo* tii_;
49 /// Special pool allocator for VNInfo's (LiveInterval val#).
51 BumpPtrAllocator VNInfoAllocator;
53 /// MBB2IdxMap - The indexes of the first and last instructions in the
54 /// specified basic block.
55 std::vector<std::pair<unsigned, unsigned> > MBB2IdxMap;
57 /// Idx2MBBMap - Sorted list of pairs of index of first instruction
59 std::vector<IdxMBBPair> Idx2MBBMap;
61 typedef std::map<MachineInstr*, unsigned> Mi2IndexMap;
64 typedef std::vector<MachineInstr*> Index2MiMap;
67 typedef std::map<unsigned, LiveInterval> Reg2IntervalMap;
68 Reg2IntervalMap r2iMap_;
70 BitVector allocatableRegs_;
72 std::vector<MachineInstr*> ClonedMIs;
75 static char ID; // Pass identification, replacement for typeid
76 LiveIntervals() : MachineFunctionPass((intptr_t)&ID) {}
88 static unsigned getBaseIndex(unsigned index) {
89 return index - (index % InstrSlots::NUM);
91 static unsigned getBoundaryIndex(unsigned index) {
92 return getBaseIndex(index + InstrSlots::NUM - 1);
94 static unsigned getLoadIndex(unsigned index) {
95 return getBaseIndex(index) + InstrSlots::LOAD;
97 static unsigned getUseIndex(unsigned index) {
98 return getBaseIndex(index) + InstrSlots::USE;
100 static unsigned getDefIndex(unsigned index) {
101 return getBaseIndex(index) + InstrSlots::DEF;
103 static unsigned getStoreIndex(unsigned index) {
104 return getBaseIndex(index) + InstrSlots::STORE;
107 static float getSpillWeight(const MachineOperand &mop, unsigned loopDepth) {
108 return (mop.isUse()+mop.isDef()) * powf(10.0F, (float)loopDepth);
111 typedef Reg2IntervalMap::iterator iterator;
112 typedef Reg2IntervalMap::const_iterator const_iterator;
113 const_iterator begin() const { return r2iMap_.begin(); }
114 const_iterator end() const { return r2iMap_.end(); }
115 iterator begin() { return r2iMap_.begin(); }
116 iterator end() { return r2iMap_.end(); }
117 unsigned getNumIntervals() const { return r2iMap_.size(); }
119 LiveInterval &getInterval(unsigned reg) {
120 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
121 assert(I != r2iMap_.end() && "Interval does not exist for register");
125 const LiveInterval &getInterval(unsigned reg) const {
126 Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
127 assert(I != r2iMap_.end() && "Interval does not exist for register");
131 bool hasInterval(unsigned reg) const {
132 return r2iMap_.count(reg);
135 /// getMBBStartIdx - Return the base index of the first instruction in the
136 /// specified MachineBasicBlock.
137 unsigned getMBBStartIdx(MachineBasicBlock *MBB) const {
138 return getMBBStartIdx(MBB->getNumber());
140 unsigned getMBBStartIdx(unsigned MBBNo) const {
141 assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
142 return MBB2IdxMap[MBBNo].first;
145 /// getMBBEndIdx - Return the store index of the last instruction in the
146 /// specified MachineBasicBlock.
147 unsigned getMBBEndIdx(MachineBasicBlock *MBB) const {
148 return getMBBEndIdx(MBB->getNumber());
150 unsigned getMBBEndIdx(unsigned MBBNo) const {
151 assert(MBBNo < MBB2IdxMap.size() && "Invalid MBB number!");
152 return MBB2IdxMap[MBBNo].second;
155 /// getInstructionIndex - returns the base index of instr
156 unsigned getInstructionIndex(MachineInstr* instr) const {
157 Mi2IndexMap::const_iterator it = mi2iMap_.find(instr);
158 assert(it != mi2iMap_.end() && "Invalid instruction!");
162 /// getInstructionFromIndex - given an index in any slot of an
163 /// instruction return a pointer the instruction
164 MachineInstr* getInstructionFromIndex(unsigned index) const {
165 index /= InstrSlots::NUM; // convert index to vector index
166 assert(index < i2miMap_.size() &&
167 "index does not correspond to an instruction");
168 return i2miMap_[index];
171 /// conflictsWithPhysRegDef - Returns true if the specified register
172 /// is defined during the duration of the specified interval.
173 bool conflictsWithPhysRegDef(const LiveInterval &li, VirtRegMap &vrm,
176 /// findLiveInMBBs - Given a live range, if the value of the range
177 /// is live in any MBB returns true as well as the list of basic blocks
178 /// where the value is live in.
179 bool findLiveInMBBs(const LiveRange &LR,
180 SmallVectorImpl<MachineBasicBlock*> &MBBs) const;
184 LiveInterval &getOrCreateInterval(unsigned reg) {
185 Reg2IntervalMap::iterator I = r2iMap_.find(reg);
186 if (I == r2iMap_.end())
187 I = r2iMap_.insert(I, std::make_pair(reg, createInterval(reg)));
193 void removeInterval(unsigned Reg) {
197 /// isRemoved - returns true if the specified machine instr has been
199 bool isRemoved(MachineInstr* instr) const {
200 return !mi2iMap_.count(instr);
203 /// RemoveMachineInstrFromMaps - This marks the specified machine instr as
205 void RemoveMachineInstrFromMaps(MachineInstr *MI) {
206 // remove index -> MachineInstr and
207 // MachineInstr -> index mappings
208 Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
209 if (mi2i != mi2iMap_.end()) {
210 i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
211 mi2iMap_.erase(mi2i);
215 BumpPtrAllocator& getVNInfoAllocator() { return VNInfoAllocator; }
217 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
218 virtual void releaseMemory();
220 /// runOnMachineFunction - pass entry point
221 virtual bool runOnMachineFunction(MachineFunction&);
223 /// print - Implement the dump method.
224 virtual void print(std::ostream &O, const Module* = 0) const;
225 void print(std::ostream *O, const Module* M = 0) const {
229 /// addIntervalsForSpills - Create new intervals for spilled defs / uses of
230 /// the given interval.
231 std::vector<LiveInterval*>
232 addIntervalsForSpills(const LiveInterval& i, VirtRegMap& vrm);
235 /// computeIntervals - Compute live intervals.
236 void computeIntervals();
238 /// handleRegisterDef - update intervals for a register def
239 /// (calls handlePhysicalRegisterDef and
240 /// handleVirtualRegisterDef)
241 void handleRegisterDef(MachineBasicBlock *MBB,
242 MachineBasicBlock::iterator MI, unsigned MIIdx,
245 /// handleVirtualRegisterDef - update intervals for a virtual
247 void handleVirtualRegisterDef(MachineBasicBlock *MBB,
248 MachineBasicBlock::iterator MI,
250 LiveInterval& interval);
252 /// handlePhysicalRegisterDef - update intervals for a physical register
254 void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
255 MachineBasicBlock::iterator mi,
257 LiveInterval &interval,
260 /// handleLiveInRegister - Create interval for a livein register.
261 void handleLiveInRegister(MachineBasicBlock* mbb,
263 LiveInterval &interval, bool isAlias = false);
265 /// isReMaterializable - Returns true if the definition MI of the specified
266 /// val# of the specified interval is re-materializable.
267 bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
270 /// tryFoldMemoryOperand - Attempts to fold either a spill / restore from
271 /// slot / to reg or any rematerialized load into ith operand of specified
272 /// MI. If it is successul, MI is updated with the newly created MI and
274 bool tryFoldMemoryOperand(MachineInstr* &MI, VirtRegMap &vrm,
275 MachineInstr *DefMI, unsigned index, unsigned i,
276 bool isSS, int slot, unsigned reg);
278 /// rewriteInstructionForSpills, rewriteInstructionsForSpills - Helper functions
279 /// for addIntervalsForSpills to rewrite uses / defs for the given live range.
280 void rewriteInstructionForSpills(const LiveInterval &li,
281 unsigned id, unsigned index, unsigned end, MachineInstr *MI,
282 MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
283 bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
284 VirtRegMap &vrm, SSARegMap *RegMap, const TargetRegisterClass* rc,
285 SmallVector<int, 4> &ReMatIds,
286 std::vector<LiveInterval*> &NewLIs);
287 void rewriteInstructionsForSpills(const LiveInterval &li,
288 LiveInterval::Ranges::const_iterator &I,
289 MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
290 bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
291 VirtRegMap &vrm, SSARegMap *RegMap, const TargetRegisterClass* rc,
292 SmallVector<int, 4> &ReMatIds,
293 std::vector<LiveInterval*> &NewLIs);
295 static LiveInterval createInterval(unsigned Reg);
297 void printRegName(unsigned reg) const;
300 } // End llvm namespace