1 //===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares codegen opcodes and related utilities.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_ISDOPCODES_H
15 #define LLVM_CODEGEN_ISDOPCODES_H
19 /// ISD namespace - This namespace contains an enum which represents all of the
20 /// SelectionDAG node types and value types.
24 //===--------------------------------------------------------------------===//
25 /// ISD::NodeType enum - This enum defines the target-independent operators
26 /// for a SelectionDAG.
28 /// Targets may also define target-dependent operator codes for SDNodes. For
29 /// example, on x86, these are the enum values in the X86ISD namespace.
30 /// Targets should aim to use target-independent operators to model their
31 /// instruction sets as much as possible, and only use target-dependent
32 /// operators when they have special requirements.
34 /// Finally, during and after selection proper, SNodes may use special
35 /// operator codes that correspond directly with MachineInstr opcodes. These
36 /// are used to represent selected instructions. See the isMachineOpcode()
37 /// and getMachineOpcode() member functions of SDNode.
40 /// DELETED_NODE - This is an illegal value that is used to catch
41 /// errors. This opcode is not a legal opcode for any node.
44 /// EntryToken - This is the marker used to indicate the start of a region.
47 /// TokenFactor - This node takes multiple tokens as input and produces a
48 /// single token result. This is used to represent the fact that the operand
49 /// operators are independent of each other.
52 /// AssertSext, AssertZext - These nodes record if a register contains a
53 /// value that has already been zero or sign extended from a narrower type.
54 /// These nodes take two operands. The first is the node that has already
55 /// been extended, and the second is a value type node indicating the width
57 AssertSext, AssertZext,
59 /// Various leaf nodes.
60 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask,
62 GlobalAddress, GlobalTLSAddress, FrameIndex,
63 JumpTable, ConstantPool, ExternalSymbol, BlockAddress,
65 /// The address of the GOT
68 /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and
69 /// llvm.returnaddress on the DAG. These nodes take one operand, the index
70 /// of the frame or return address to return. An index of zero corresponds
71 /// to the current function's frame or return address, an index of one to
72 /// the parent's frame or return address, and so on.
73 FRAMEADDR, RETURNADDR,
75 /// LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
76 /// Materializes the offset from the local object pointer of another
77 /// function to a particular local object passed to llvm.localescape. The
78 /// operand is the MCSymbol label used to represent this offset, since
79 /// typically the offset is not known until after code generation of the
83 /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on
84 /// the DAG, which implements the named register global variables extension.
88 /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to
89 /// first (possible) on-stack argument. This is needed for correct stack
90 /// adjustment during unwind.
93 /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents
94 /// 'eh_return' gcc dwarf builtin, which is used to return from
95 /// exception. The general meaning is: adjust stack by OFFSET and pass
96 /// execution to HANDLER. Many platform-related details also :)
99 /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer)
100 /// This corresponds to the eh.sjlj.setjmp intrinsic.
101 /// It takes an input chain and a pointer to the jump buffer as inputs
102 /// and returns an outchain.
105 /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer)
106 /// This corresponds to the eh.sjlj.longjmp intrinsic.
107 /// It takes an input chain and a pointer to the jump buffer as inputs
108 /// and returns an outchain.
111 /// TargetConstant* - Like Constant*, but the DAG does not do any folding,
112 /// simplification, or lowering of the constant. They are used for constants
113 /// which are known to fit in the immediate fields of their users, or for
114 /// carrying magic numbers which are not values which need to be
115 /// materialized in registers.
119 /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or
120 /// anything else with this node, and this is valid in the target-specific
121 /// dag, turning into a GlobalAddress operand.
123 TargetGlobalTLSAddress,
127 TargetExternalSymbol,
132 /// TargetIndex - Like a constant pool entry, but with completely
133 /// target-dependent semantics. Holds target flags, a 32-bit index, and a
134 /// 64-bit index. Targets can use this however they like.
137 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...)
138 /// This node represents a target intrinsic function with no side effects.
139 /// The first operand is the ID number of the intrinsic from the
140 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The
141 /// node returns the result of the intrinsic.
144 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...)
145 /// This node represents a target intrinsic function with side effects that
146 /// returns a result. The first operand is a chain pointer. The second is
147 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The
148 /// operands to the intrinsic follow. The node has two results, the result
149 /// of the intrinsic and an output chain.
152 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...)
153 /// This node represents a target intrinsic function with side effects that
154 /// does not return a result. The first operand is a chain pointer. The
155 /// second is the ID number of the intrinsic from the llvm::Intrinsic
156 /// namespace. The operands to the intrinsic follow.
159 /// CopyToReg - This node has three operands: a chain, a register number to
160 /// set to this value, and a value.
163 /// CopyFromReg - This node indicates that the input value is a virtual or
164 /// physical register that is defined outside of the scope of this
165 /// SelectionDAG. The register is available from the RegisterSDNode object.
168 /// UNDEF - An undefined node.
171 /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by
172 /// a Constant, which is required to be operand #1) half of the integer or
173 /// float value specified as operand #0. This is only for use before
174 /// legalization, for values that will be broken into multiple registers.
177 /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
178 /// Given two values of the same integer value type, this produces a value
179 /// twice as big. Like EXTRACT_ELEMENT, this can only be used before
183 /// MERGE_VALUES - This node takes multiple discrete operands and returns
184 /// them all as its individual results. This nodes has exactly the same
185 /// number of inputs and outputs. This node is useful for some pieces of the
186 /// code generator that want to think about a single node with multiple
187 /// results, not multiple nodes.
190 /// Simple integer binary arithmetic operators.
191 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
193 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing
194 /// a signed/unsigned value of type i[2*N], and return the full value as
195 /// two results, each of type iN.
196 SMUL_LOHI, UMUL_LOHI,
198 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
199 /// remainder result.
202 /// CARRY_FALSE - This node is used when folding other nodes,
203 /// like ADDC/SUBC, which indicate the carry result is always false.
206 /// Carry-setting nodes for multiple precision addition and subtraction.
207 /// These nodes take two operands of the same value type, and produce two
208 /// results. The first result is the normal add or sub result, the second
209 /// result is the carry flag result.
212 /// Carry-using nodes for multiple precision addition and subtraction. These
213 /// nodes take three operands: The first two are the normal lhs and rhs to
214 /// the add or sub, and the third is the input carry flag. These nodes
215 /// produce two results; the normal result of the add or sub, and the output
216 /// carry flag. These nodes both read and write a carry flag to allow them
217 /// to them to be chained together for add and sub of arbitrarily large
221 /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
222 /// These nodes take two operands: the normal LHS and RHS to the add. They
223 /// produce two results: the normal result of the add, and a boolean that
224 /// indicates if an overflow occurred (*not* a flag, because it may be store
225 /// to memory, etc.). If the type of the boolean is not i1 then the high
226 /// bits conform to getBooleanContents.
227 /// These nodes are generated from llvm.[su]add.with.overflow intrinsics.
230 /// Same for subtraction.
233 /// Same for multiplication.
236 /// Simple binary floating point operators.
237 FADD, FSUB, FMUL, FDIV, FREM,
239 /// FMA - Perform a * b + c with no intermediate rounding step.
242 /// FMAD - Perform a * b + c, while getting the same result as the
243 /// separately rounded operations.
246 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This
247 /// DAG node does not require that X and Y have the same type, just that
248 /// they are both floating point. X and the result must have the same type.
249 /// FCOPYSIGN(f32, f64) is allowed.
252 /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point
253 /// value as an integer 0/1 value.
256 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the
257 /// specified, possibly variable, elements. The number of elements is
258 /// required to be a power of two. The types of the operands must all be
259 /// the same and must match the vector element type, except that integer
260 /// types are allowed to be larger than the element type, in which case
261 /// the operands are implicitly truncated.
264 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element
265 /// at IDX replaced with VAL. If the type of VAL is larger than the vector
266 /// element type then VAL is truncated before replacement.
269 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR
270 /// identified by the (potentially variable) element number IDX. If the
271 /// return type is an integer type larger than the element type of the
272 /// vector, the result is extended to the width of the return type.
275 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of
276 /// vector type with the same length and element type, this produces a
277 /// concatenated vector result value, with length equal to the sum of the
278 /// lengths of the input vectors.
281 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector
282 /// with VECTOR2 inserted into VECTOR1 at the (potentially
283 /// variable) element number IDX, which must be a multiple of the
284 /// VECTOR2 vector length. The elements of VECTOR1 starting at
285 /// IDX are overwritten with VECTOR2. Elements IDX through
286 /// vector_length(VECTOR2) must be valid VECTOR1 indices.
289 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an
290 /// vector value) starting with the element number IDX, which must be a
291 /// constant multiple of the result vector length.
294 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as
295 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int
296 /// values that indicate which value (or undef) each result element will
297 /// get. These constant ints are accessible through the
298 /// ShuffleVectorSDNode class. This is quite similar to the Altivec
299 /// 'vperm' instruction, except that the indices must be constants and are
300 /// in terms of the element size of VEC1/VEC2, not in terms of bytes.
303 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a
304 /// scalar value into element 0 of the resultant vector type. The top
305 /// elements 1 to N-1 of the N-element vector are undefined. The type
306 /// of the operand must match the vector element type, except when they
307 /// are integer types. In this case the operand is allowed to be wider
308 /// than the vector element type, and is implicitly truncated to it.
311 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN,
312 /// producing an unsigned/signed value of type i[2*N], then return the top
316 /// [US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned
318 SMIN, SMAX, UMIN, UMAX,
320 /// Bitwise operators - logical and, logical or, logical xor.
323 /// Shift and rotation operations. After legalization, the type of the
324 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization
325 /// the shift amount can be any type, but care must be taken to ensure it is
326 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before
327 /// legalization, types like i1024 can occur and i8 doesn't have enough bits
328 /// to represent the shift amount.
329 /// When the 1st operand is a vector, the shift amount must be in the same
330 /// type. (TLI.getShiftAmountTy() will return the same type when the input
331 /// type is a vector.)
332 SHL, SRA, SRL, ROTL, ROTR,
334 /// Byte Swap and Counting operators.
335 BSWAP, CTTZ, CTLZ, CTPOP,
337 /// [SU]ABSDIFF - Signed/Unsigned absolute difference of two input integer
338 /// vector. These nodes are generated from llvm.*absdiff* intrinsics.
341 /// Bit counting operators with an undefined result for zero inputs.
342 CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF,
344 /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not
345 /// i1 then the high bits must conform to getBooleanContents.
348 /// Select with a vector condition (op #0) and two vector operands (ops #1
349 /// and #2), returning a vector result. All vectors have the same length.
350 /// Much like the scalar select and setcc, each bit in the condition selects
351 /// whether the corresponding result element is taken from op #1 or op #2.
352 /// At first, the VSELECT condition is of vXi1 type. Later, targets may
353 /// change the condition type in order to match the VSELECT node using a
354 /// pattern. The condition follows the BooleanContent format of the target.
357 /// Select with condition operator - This selects between a true value and
358 /// a false value (ops #2 and #3) based on the boolean result of comparing
359 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
360 /// condition code in op #4, a CondCodeSDNode.
363 /// SetCC operator - This evaluates to a true value iff the condition is
364 /// true. If the result value type is not i1 then the high bits conform
365 /// to getBooleanContents. The operands to this are the left and right
366 /// operands to compare (ops #0, and #1) and the condition code to compare
367 /// them with (op #2) as a CondCodeSDNode. If the operands are vector types
368 /// then the result type must also be a vector type.
371 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
372 /// integer shift operations, just like ADD/SUB_PARTS. The operation
374 /// [Lo,Hi] = op [LoLHS,HiLHS], Amt
375 SHL_PARTS, SRA_PARTS, SRL_PARTS,
377 /// Conversion operators. These are all single input single output
378 /// operations. For all of these, the result type must be strictly
379 /// wider or narrower (depending on the operation) than the source
382 /// SIGN_EXTEND - Used for integer types, replicating the sign bit
386 /// ZERO_EXTEND - Used for integer types, zeroing the new bits.
389 /// ANY_EXTEND - Used for integer types. The high bits are undefined.
392 /// TRUNCATE - Completely drop the high bits.
395 /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign
396 /// depends on the first letter) to floating point.
400 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
401 /// sign extend a small value in a large integer register (e.g. sign
402 /// extending the low 8 bits of a 32-bit register to fill the top 24 bits
403 /// with the 7th bit). The size of the smaller type is indicated by the 1th
404 /// operand, a ValueType node.
407 /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an
408 /// in-register any-extension of the low lanes of an integer vector. The
409 /// result type must have fewer elements than the operand type, and those
410 /// elements must be larger integer types such that the total size of the
411 /// operand type and the result type match. Each of the low operand
412 /// elements is any-extended into the corresponding, wider result
413 /// elements with the high bits becoming undef.
414 ANY_EXTEND_VECTOR_INREG,
416 /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an
417 /// in-register sign-extension of the low lanes of an integer vector. The
418 /// result type must have fewer elements than the operand type, and those
419 /// elements must be larger integer types such that the total size of the
420 /// operand type and the result type match. Each of the low operand
421 /// elements is sign-extended into the corresponding, wider result
423 // FIXME: The SIGN_EXTEND_INREG node isn't specifically limited to
424 // scalars, but it also doesn't handle vectors well. Either it should be
425 // restricted to scalars or this node (and its handling) should be merged
427 SIGN_EXTEND_VECTOR_INREG,
429 /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an
430 /// in-register zero-extension of the low lanes of an integer vector. The
431 /// result type must have fewer elements than the operand type, and those
432 /// elements must be larger integer types such that the total size of the
433 /// operand type and the result type match. Each of the low operand
434 /// elements is zero-extended into the corresponding, wider result
436 ZERO_EXTEND_VECTOR_INREG,
438 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
443 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type
444 /// down to the precision of the destination VT. TRUNC is a flag, which is
445 /// always an integer that is zero or one. If TRUNC is 0, this is a
446 /// normal rounding, if it is 1, this FP_ROUND is known to not change the
449 /// The TRUNC = 1 case is used in cases where we know that the value will
450 /// not be modified by the node, because Y is not using any of the extra
451 /// precision of source type. This allows certain transformations like
452 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
453 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
456 /// FLT_ROUNDS_ - Returns current rounding mode:
459 /// 1 Round to nearest
464 /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and
465 /// rounds it to a floating point value. It then promotes it and returns it
466 /// in a register of the same size. This operation effectively just
467 /// discards excess precision. The type to round down to is specified by
468 /// the VT operand, a VTSDNode.
471 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
474 /// BITCAST - This operator converts between integer, vector and FP
475 /// values, as if the value was stored to memory with one type and loaded
476 /// from the same address with the other type (or equivalently for vector
477 /// format conversions, etc). The source and result are required to have
478 /// the same bit size (e.g. f32 <-> i32). This can also be used for
479 /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by
483 /// ADDRSPACECAST - This operator converts between pointers of different
487 /// CONVERT_RNDSAT - This operator is used to support various conversions
488 /// between various types (float, signed, unsigned and vectors of those
489 /// types) with rounding and saturation. NOTE: Avoid using this operator as
490 /// most target don't support it and the operator might be removed in the
491 /// future. It takes the following arguments:
493 /// 1) dest type (type to convert to)
494 /// 2) src type (type to convert from)
496 /// 4) saturation imm
497 /// 5) ISD::CvtCode indicating the type of conversion to do
500 /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions
501 /// and truncation for half-precision (16 bit) floating numbers. These nodes
502 /// form a semi-softened interface for dealing with f16 (as an i16), which
503 /// is often a storage-only type but has native conversions.
504 FP16_TO_FP, FP_TO_FP16,
506 /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
507 /// FLOG, FLOG2, FLOG10, FEXP, FEXP2,
508 /// FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary
509 /// floating point operations. These are inspired by libm.
510 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
511 FLOG, FLOG2, FLOG10, FEXP, FEXP2,
512 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR,
515 /// FSINCOS - Compute both fsin and fcos as a single operation.
518 /// LOAD and STORE have token chains as their first operand, then the same
519 /// operands as an LLVM load/store instruction, then an offset node that
520 /// is added / subtracted from the base pointer to form the address (for
521 /// indexed memory ops).
524 /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned
525 /// to a specified boundary. This node always has two return values: a new
526 /// stack pointer value and a chain. The first operand is the token chain,
527 /// the second is the number of bytes to allocate, and the third is the
528 /// alignment boundary. The size is guaranteed to be a multiple of the
529 /// stack alignment, and the alignment is guaranteed to be bigger than the
530 /// stack alignment (if required) or 0 to get standard stack alignment.
533 /// Control flow instructions. These all have token chains.
535 /// BR - Unconditional branch. The first operand is the chain
536 /// operand, the second is the MBB to branch to.
539 /// BRIND - Indirect branch. The first operand is the chain, the second
540 /// is the value to branch to, which must be of the same type as the
541 /// target's pointer type.
544 /// BR_JT - Jumptable branch. The first operand is the chain, the second
545 /// is the jumptable index, the last one is the jumptable entry index.
548 /// BRCOND - Conditional branch. The first operand is the chain, the
549 /// second is the condition, the third is the block to branch to if the
550 /// condition is true. If the type of the condition is not i1, then the
551 /// high bits must conform to getBooleanContents.
554 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
555 /// that the condition is represented as condition code, and two nodes to
556 /// compare, rather than as a combined SetCC node. The operands in order
557 /// are chain, cc, lhs, rhs, block to branch to if condition is true.
560 /// INLINEASM - Represents an inline asm block. This node always has two
561 /// return values: a chain and a flag result. The inputs are as follows:
562 /// Operand #0 : Input chain.
563 /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string.
564 /// Operand #2 : a MDNodeSDNode with the !srcloc metadata.
565 /// Operand #3 : HasSideEffect, IsAlignStack bits.
566 /// After this, it is followed by a list of operands with this format:
567 /// ConstantSDNode: Flags that encode whether it is a mem or not, the
568 /// of operands that follow, etc. See InlineAsm.h.
569 /// ... however many operands ...
570 /// Operand #last: Optional, an incoming flag.
572 /// The variable width operands are required to represent target addressing
573 /// modes as a single "operand", even though they may have multiple
577 /// EH_LABEL - Represents a label in mid basic block used to track
578 /// locations needed for debug and exception handling tables. These nodes
579 /// take a chain as input and return a chain.
582 /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a
583 /// value, the same type as the pointer type for the system, and an output
587 /// STACKRESTORE has two operands, an input chain and a pointer to restore
588 /// to it returns an output chain.
591 /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end
592 /// of a call sequence, and carry arbitrary information that target might
593 /// want to know. The first operand is a chain, the rest are specified by
594 /// the target and not touched by the DAG optimizers.
595 /// CALLSEQ_START..CALLSEQ_END pairs may not be nested.
596 CALLSEQ_START, // Beginning of a call sequence
597 CALLSEQ_END, // End of a call sequence
599 /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE,
600 /// and the alignment. It returns a pair of values: the vaarg value and a
604 /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer,
605 /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the
609 /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain,
610 /// pointer, and a SRCVALUE.
613 /// SRCVALUE - This is a node type that holds a Value* that is used to
614 /// make reference to a value in the LLVM IR.
617 /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to
618 /// reference metadata in the IR.
621 /// PCMARKER - This corresponds to the pcmarker intrinsic.
624 /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
625 /// The only operand is a chain and a value and a chain are produced. The
626 /// value is the contents of the architecture specific cycle counter like
627 /// register (or other high accuracy low latency clock source)
630 /// HANDLENODE node - Used as a handle for various purposes.
633 /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It
634 /// takes as input a token chain, the pointer to the trampoline, the pointer
635 /// to the nested function, the pointer to pass for the 'nest' parameter, a
636 /// SRCVALUE for the trampoline and another for the nested function
637 /// (allowing targets to access the original Function*).
638 /// It produces a token chain as output.
641 /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
642 /// It takes a pointer to the trampoline and produces a (possibly) new
643 /// pointer to the same trampoline with platform-specific adjustments
644 /// applied. The pointer it returns points to an executable block of code.
647 /// TRAP - Trapping instruction
650 /// DEBUGTRAP - Trap intended to get the attention of a debugger.
653 /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand
654 /// is the chain. The other operands are the address to prefetch,
655 /// read / write specifier, locality specifier and instruction / data cache
659 /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope)
660 /// This corresponds to the fence instruction. It takes an input chain, and
661 /// two integer constants: an AtomicOrdering and a SynchronizationScope.
664 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr)
665 /// This corresponds to "load atomic" instruction.
668 /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val)
669 /// This corresponds to "store atomic" instruction.
672 /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
673 /// For double-word atomic operations:
674 /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi,
676 /// This corresponds to the cmpxchg instruction.
679 /// Val, Success, OUTCHAIN
680 /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap)
681 /// N.b. this is still a strong cmpxchg operation, so
682 /// Success == "Val == cmp".
683 ATOMIC_CMP_SWAP_WITH_SUCCESS,
685 /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt)
686 /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt)
687 /// For double-word atomic operations:
688 /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi)
689 /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi)
690 /// These correspond to the atomicrmw instruction.
703 // Masked load and store - consecutive vector load and store operations
704 // with additional mask operand that prevents memory accesses to the
708 // Masked gather and scatter - load and store operations for a vector of
709 // random addresses with additional mask operand that prevents memory
710 // accesses to the masked-off lanes.
713 /// This corresponds to the llvm.lifetime.* intrinsics. The first operand
714 /// is the chain and the second operand is the alloca pointer.
715 LIFETIME_START, LIFETIME_END,
717 /// GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the
718 /// beginning and end of GC transition sequence, and carry arbitrary
719 /// information that target might need for lowering. The first operand is
720 /// a chain, the rest are specified by the target and not touched by the DAG
721 /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be
726 /// BUILTIN_OP_END - This must be the last enum value in this list.
727 /// The target-specific pre-isel opcode values start here.
731 /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations
732 /// which do not reference a specific memory location should be less than
733 /// this value. Those that do must not be less than this value, and can
734 /// be used with SelectionDAG::getMemIntrinsicNode.
735 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+300;
737 //===--------------------------------------------------------------------===//
738 /// MemIndexedMode enum - This enum defines the load / store indexed
739 /// addressing modes.
741 /// UNINDEXED "Normal" load / store. The effective address is already
742 /// computed and is available in the base pointer. The offset
743 /// operand is always undefined. In addition to producing a
744 /// chain, an unindexed load produces one value (result of the
745 /// load); an unindexed store does not produce a value.
747 /// PRE_INC Similar to the unindexed mode where the effective address is
748 /// PRE_DEC the value of the base pointer add / subtract the offset.
749 /// It considers the computation as being folded into the load /
750 /// store operation (i.e. the load / store does the address
751 /// computation as well as performing the memory transaction).
752 /// The base operand is always undefined. In addition to
753 /// producing a chain, pre-indexed load produces two values
754 /// (result of the load and the result of the address
755 /// computation); a pre-indexed store produces one value (result
756 /// of the address computation).
758 /// POST_INC The effective address is the value of the base pointer. The
759 /// POST_DEC value of the offset operand is then added to / subtracted
760 /// from the base after memory transaction. In addition to
761 /// producing a chain, post-indexed load produces two values
762 /// (the result of the load and the result of the base +/- offset
763 /// computation); a post-indexed store produces one value (the
764 /// the result of the base +/- offset computation).
765 enum MemIndexedMode {
774 //===--------------------------------------------------------------------===//
775 /// LoadExtType enum - This enum defines the three variants of LOADEXT
776 /// (load with extension).
778 /// SEXTLOAD loads the integer operand and sign extends it to a larger
779 /// integer result type.
780 /// ZEXTLOAD loads the integer operand and zero extends it to a larger
781 /// integer result type.
782 /// EXTLOAD is used for two things: floating point extending loads and
783 /// integer extending loads [the top bits are undefined].
792 NodeType getExtForLoadExtType(bool IsFP, LoadExtType);
794 //===--------------------------------------------------------------------===//
795 /// ISD::CondCode enum - These are ordered carefully to make the bitfields
796 /// below work out, when considering SETFALSE (something that never exists
797 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered
798 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal
799 /// to. If the "N" column is 1, the result of the comparison is undefined if
800 /// the input is a NAN.
802 /// All of these (except for the 'always folded ops') should be handled for
803 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT,
804 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
806 /// Note that these are laid out in a specific order to allow bit-twiddling
807 /// to transform conditions.
809 // Opcode N U L G E Intuitive operation
810 SETFALSE, // 0 0 0 0 Always false (always folded)
811 SETOEQ, // 0 0 0 1 True if ordered and equal
812 SETOGT, // 0 0 1 0 True if ordered and greater than
813 SETOGE, // 0 0 1 1 True if ordered and greater than or equal
814 SETOLT, // 0 1 0 0 True if ordered and less than
815 SETOLE, // 0 1 0 1 True if ordered and less than or equal
816 SETONE, // 0 1 1 0 True if ordered and operands are unequal
817 SETO, // 0 1 1 1 True if ordered (no nans)
818 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
819 SETUEQ, // 1 0 0 1 True if unordered or equal
820 SETUGT, // 1 0 1 0 True if unordered or greater than
821 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal
822 SETULT, // 1 1 0 0 True if unordered or less than
823 SETULE, // 1 1 0 1 True if unordered, less than, or equal
824 SETUNE, // 1 1 1 0 True if unordered or not equal
825 SETTRUE, // 1 1 1 1 Always true (always folded)
826 // Don't care operations: undefined if the input is a nan.
827 SETFALSE2, // 1 X 0 0 0 Always false (always folded)
828 SETEQ, // 1 X 0 0 1 True if equal
829 SETGT, // 1 X 0 1 0 True if greater than
830 SETGE, // 1 X 0 1 1 True if greater than or equal
831 SETLT, // 1 X 1 0 0 True if less than
832 SETLE, // 1 X 1 0 1 True if less than or equal
833 SETNE, // 1 X 1 1 0 True if not equal
834 SETTRUE2, // 1 X 1 1 1 Always true (always folded)
836 SETCC_INVALID // Marker value.
839 /// isSignedIntSetCC - Return true if this is a setcc instruction that
840 /// performs a signed comparison when used with integer operands.
841 inline bool isSignedIntSetCC(CondCode Code) {
842 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE;
845 /// isUnsignedIntSetCC - Return true if this is a setcc instruction that
846 /// performs an unsigned comparison when used with integer operands.
847 inline bool isUnsignedIntSetCC(CondCode Code) {
848 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE;
851 /// isTrueWhenEqual - Return true if the specified condition returns true if
852 /// the two operands to the condition are equal. Note that if one of the two
853 /// operands is a NaN, this value is meaningless.
854 inline bool isTrueWhenEqual(CondCode Cond) {
855 return ((int)Cond & 1) != 0;
858 /// getUnorderedFlavor - This function returns 0 if the condition is always
859 /// false if an operand is a NaN, 1 if the condition is always true if the
860 /// operand is a NaN, and 2 if the condition is undefined if the operand is a
862 inline unsigned getUnorderedFlavor(CondCode Cond) {
863 return ((int)Cond >> 3) & 3;
866 /// getSetCCInverse - Return the operation corresponding to !(X op Y), where
867 /// 'op' is a valid SetCC operation.
868 CondCode getSetCCInverse(CondCode Operation, bool isInteger);
870 /// getSetCCSwappedOperands - Return the operation corresponding to (Y op X)
871 /// when given the operation for (X op Y).
872 CondCode getSetCCSwappedOperands(CondCode Operation);
874 /// getSetCCOrOperation - Return the result of a logical OR between different
875 /// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This
876 /// function returns SETCC_INVALID if it is not possible to represent the
877 /// resultant comparison.
878 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
880 /// getSetCCAndOperation - Return the result of a logical AND between
881 /// different comparisons of identical values: ((X op1 Y) & (X op2 Y)). This
882 /// function returns SETCC_INVALID if it is not possible to represent the
883 /// resultant comparison.
884 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
886 //===--------------------------------------------------------------------===//
887 /// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT
890 CVT_FF, /// Float from Float
891 CVT_FS, /// Float from Signed
892 CVT_FU, /// Float from Unsigned
893 CVT_SF, /// Signed from Float
894 CVT_UF, /// Unsigned from Float
895 CVT_SS, /// Signed from Signed
896 CVT_SU, /// Signed from Unsigned
897 CVT_US, /// Unsigned from Signed
898 CVT_UU, /// Unsigned from Unsigned
899 CVT_INVALID /// Marker - Invalid opcode
902 } // end llvm::ISD namespace
904 } // end llvm namespace