1 //===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares codegen opcodes and related utilities.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_ISDOPCODES_H
15 #define LLVM_CODEGEN_ISDOPCODES_H
19 /// ISD namespace - This namespace contains an enum which represents all of the
20 /// SelectionDAG node types and value types.
24 //===--------------------------------------------------------------------===//
25 /// ISD::NodeType enum - This enum defines the target-independent operators
26 /// for a SelectionDAG.
28 /// Targets may also define target-dependent operator codes for SDNodes. For
29 /// example, on x86, these are the enum values in the X86ISD namespace.
30 /// Targets should aim to use target-independent operators to model their
31 /// instruction sets as much as possible, and only use target-dependent
32 /// operators when they have special requirements.
34 /// Finally, during and after selection proper, SNodes may use special
35 /// operator codes that correspond directly with MachineInstr opcodes. These
36 /// are used to represent selected instructions. See the isMachineOpcode()
37 /// and getMachineOpcode() member functions of SDNode.
40 /// DELETED_NODE - This is an illegal value that is used to catch
41 /// errors. This opcode is not a legal opcode for any node.
44 /// EntryToken - This is the marker used to indicate the start of a region.
47 /// TokenFactor - This node takes multiple tokens as input and produces a
48 /// single token result. This is used to represent the fact that the operand
49 /// operators are independent of each other.
52 /// AssertSext, AssertZext - These nodes record if a register contains a
53 /// value that has already been zero or sign extended from a narrower type.
54 /// These nodes take two operands. The first is the node that has already
55 /// been extended, and the second is a value type node indicating the width
57 AssertSext, AssertZext,
59 /// Various leaf nodes.
60 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask,
62 GlobalAddress, GlobalTLSAddress, FrameIndex,
63 JumpTable, ConstantPool, ExternalSymbol, BlockAddress,
65 /// The address of the GOT
68 /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and
69 /// llvm.returnaddress on the DAG. These nodes take one operand, the index
70 /// of the frame or return address to return. An index of zero corresponds
71 /// to the current function's frame or return address, an index of one to
72 /// the parent's frame or return address, and so on.
73 FRAMEADDR, RETURNADDR,
75 /// LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
76 /// Materializes the offset from the local object pointer of another
77 /// function to a particular local object passed to llvm.localescape. The
78 /// operand is the MCSymbol label used to represent this offset, since
79 /// typically the offset is not known until after code generation of the
83 /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on
84 /// the DAG, which implements the named register global variables extension.
88 /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to
89 /// first (possible) on-stack argument. This is needed for correct stack
90 /// adjustment during unwind.
93 /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents
94 /// 'eh_return' gcc dwarf builtin, which is used to return from
95 /// exception. The general meaning is: adjust stack by OFFSET and pass
96 /// execution to HANDLER. Many platform-related details also :)
99 /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer)
100 /// This corresponds to the eh.sjlj.setjmp intrinsic.
101 /// It takes an input chain and a pointer to the jump buffer as inputs
102 /// and returns an outchain.
105 /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer)
106 /// This corresponds to the eh.sjlj.longjmp intrinsic.
107 /// It takes an input chain and a pointer to the jump buffer as inputs
108 /// and returns an outchain.
111 /// OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN)
112 /// The target initializes the dispatch table here.
113 EH_SJLJ_SETUP_DISPATCH,
115 /// TargetConstant* - Like Constant*, but the DAG does not do any folding,
116 /// simplification, or lowering of the constant. They are used for constants
117 /// which are known to fit in the immediate fields of their users, or for
118 /// carrying magic numbers which are not values which need to be
119 /// materialized in registers.
123 /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or
124 /// anything else with this node, and this is valid in the target-specific
125 /// dag, turning into a GlobalAddress operand.
127 TargetGlobalTLSAddress,
131 TargetExternalSymbol,
136 /// TargetIndex - Like a constant pool entry, but with completely
137 /// target-dependent semantics. Holds target flags, a 32-bit index, and a
138 /// 64-bit index. Targets can use this however they like.
141 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...)
142 /// This node represents a target intrinsic function with no side effects.
143 /// The first operand is the ID number of the intrinsic from the
144 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The
145 /// node returns the result of the intrinsic.
148 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...)
149 /// This node represents a target intrinsic function with side effects that
150 /// returns a result. The first operand is a chain pointer. The second is
151 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The
152 /// operands to the intrinsic follow. The node has two results, the result
153 /// of the intrinsic and an output chain.
156 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...)
157 /// This node represents a target intrinsic function with side effects that
158 /// does not return a result. The first operand is a chain pointer. The
159 /// second is the ID number of the intrinsic from the llvm::Intrinsic
160 /// namespace. The operands to the intrinsic follow.
163 /// CopyToReg - This node has three operands: a chain, a register number to
164 /// set to this value, and a value.
167 /// CopyFromReg - This node indicates that the input value is a virtual or
168 /// physical register that is defined outside of the scope of this
169 /// SelectionDAG. The register is available from the RegisterSDNode object.
172 /// UNDEF - An undefined node.
175 /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by
176 /// a Constant, which is required to be operand #1) half of the integer or
177 /// float value specified as operand #0. This is only for use before
178 /// legalization, for values that will be broken into multiple registers.
181 /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
182 /// Given two values of the same integer value type, this produces a value
183 /// twice as big. Like EXTRACT_ELEMENT, this can only be used before
187 /// MERGE_VALUES - This node takes multiple discrete operands and returns
188 /// them all as its individual results. This nodes has exactly the same
189 /// number of inputs and outputs. This node is useful for some pieces of the
190 /// code generator that want to think about a single node with multiple
191 /// results, not multiple nodes.
194 /// Simple integer binary arithmetic operators.
195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM,
197 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing
198 /// a signed/unsigned value of type i[2*N], and return the full value as
199 /// two results, each of type iN.
200 SMUL_LOHI, UMUL_LOHI,
202 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and
203 /// remainder result.
206 /// CARRY_FALSE - This node is used when folding other nodes,
207 /// like ADDC/SUBC, which indicate the carry result is always false.
210 /// Carry-setting nodes for multiple precision addition and subtraction.
211 /// These nodes take two operands of the same value type, and produce two
212 /// results. The first result is the normal add or sub result, the second
213 /// result is the carry flag result.
216 /// Carry-using nodes for multiple precision addition and subtraction. These
217 /// nodes take three operands: The first two are the normal lhs and rhs to
218 /// the add or sub, and the third is the input carry flag. These nodes
219 /// produce two results; the normal result of the add or sub, and the output
220 /// carry flag. These nodes both read and write a carry flag to allow them
221 /// to them to be chained together for add and sub of arbitrarily large
225 /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
226 /// These nodes take two operands: the normal LHS and RHS to the add. They
227 /// produce two results: the normal result of the add, and a boolean that
228 /// indicates if an overflow occurred (*not* a flag, because it may be store
229 /// to memory, etc.). If the type of the boolean is not i1 then the high
230 /// bits conform to getBooleanContents.
231 /// These nodes are generated from llvm.[su]add.with.overflow intrinsics.
234 /// Same for subtraction.
237 /// Same for multiplication.
240 /// Simple binary floating point operators.
241 FADD, FSUB, FMUL, FDIV, FREM,
243 /// FMA - Perform a * b + c with no intermediate rounding step.
246 /// FMAD - Perform a * b + c, while getting the same result as the
247 /// separately rounded operations.
250 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This
251 /// DAG node does not require that X and Y have the same type, just that
252 /// they are both floating point. X and the result must have the same type.
253 /// FCOPYSIGN(f32, f64) is allowed.
256 /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point
257 /// value as an integer 0/1 value.
260 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the
261 /// specified, possibly variable, elements. The number of elements is
262 /// required to be a power of two. The types of the operands must all be
263 /// the same and must match the vector element type, except that integer
264 /// types are allowed to be larger than the element type, in which case
265 /// the operands are implicitly truncated.
268 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element
269 /// at IDX replaced with VAL. If the type of VAL is larger than the vector
270 /// element type then VAL is truncated before replacement.
273 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR
274 /// identified by the (potentially variable) element number IDX. If the
275 /// return type is an integer type larger than the element type of the
276 /// vector, the result is extended to the width of the return type.
279 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of
280 /// vector type with the same length and element type, this produces a
281 /// concatenated vector result value, with length equal to the sum of the
282 /// lengths of the input vectors.
285 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector
286 /// with VECTOR2 inserted into VECTOR1 at the (potentially
287 /// variable) element number IDX, which must be a multiple of the
288 /// VECTOR2 vector length. The elements of VECTOR1 starting at
289 /// IDX are overwritten with VECTOR2. Elements IDX through
290 /// vector_length(VECTOR2) must be valid VECTOR1 indices.
293 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an
294 /// vector value) starting with the element number IDX, which must be a
295 /// constant multiple of the result vector length.
298 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as
299 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int
300 /// values that indicate which value (or undef) each result element will
301 /// get. These constant ints are accessible through the
302 /// ShuffleVectorSDNode class. This is quite similar to the Altivec
303 /// 'vperm' instruction, except that the indices must be constants and are
304 /// in terms of the element size of VEC1/VEC2, not in terms of bytes.
307 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a
308 /// scalar value into element 0 of the resultant vector type. The top
309 /// elements 1 to N-1 of the N-element vector are undefined. The type
310 /// of the operand must match the vector element type, except when they
311 /// are integer types. In this case the operand is allowed to be wider
312 /// than the vector element type, and is implicitly truncated to it.
315 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN,
316 /// producing an unsigned/signed value of type i[2*N], then return the top
320 /// [US]{MIN/MAX} - Binary minimum or maximum or signed or unsigned
322 SMIN, SMAX, UMIN, UMAX,
324 /// Bitwise operators - logical and, logical or, logical xor.
327 /// Shift and rotation operations. After legalization, the type of the
328 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization
329 /// the shift amount can be any type, but care must be taken to ensure it is
330 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before
331 /// legalization, types like i1024 can occur and i8 doesn't have enough bits
332 /// to represent the shift amount.
333 /// When the 1st operand is a vector, the shift amount must be in the same
334 /// type. (TLI.getShiftAmountTy() will return the same type when the input
335 /// type is a vector.)
336 SHL, SRA, SRL, ROTL, ROTR,
338 /// Byte Swap and Counting operators.
339 BSWAP, CTTZ, CTLZ, CTPOP, BITREVERSE,
341 /// [SU]ABSDIFF - Signed/Unsigned absolute difference of two input integer
342 /// vector. These nodes are generated from llvm.*absdiff* intrinsics.
345 /// Bit counting operators with an undefined result for zero inputs.
346 CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF,
348 /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not
349 /// i1 then the high bits must conform to getBooleanContents.
352 /// Select with a vector condition (op #0) and two vector operands (ops #1
353 /// and #2), returning a vector result. All vectors have the same length.
354 /// Much like the scalar select and setcc, each bit in the condition selects
355 /// whether the corresponding result element is taken from op #1 or op #2.
356 /// At first, the VSELECT condition is of vXi1 type. Later, targets may
357 /// change the condition type in order to match the VSELECT node using a
358 /// pattern. The condition follows the BooleanContent format of the target.
361 /// Select with condition operator - This selects between a true value and
362 /// a false value (ops #2 and #3) based on the boolean result of comparing
363 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
364 /// condition code in op #4, a CondCodeSDNode.
367 /// SetCC operator - This evaluates to a true value iff the condition is
368 /// true. If the result value type is not i1 then the high bits conform
369 /// to getBooleanContents. The operands to this are the left and right
370 /// operands to compare (ops #0, and #1) and the condition code to compare
371 /// them with (op #2) as a CondCodeSDNode. If the operands are vector types
372 /// then the result type must also be a vector type.
375 /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but
376 /// op #2 is a *carry value*. This operator checks the result of
377 /// "LHS - RHS - Carry", and can be used to compare two wide integers:
378 /// (setcce lhshi rhshi (subc lhslo rhslo) cc). Only valid for integers.
381 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
382 /// integer shift operations. The operation ordering is:
383 /// [Lo,Hi] = op [LoLHS,HiLHS], Amt
384 SHL_PARTS, SRA_PARTS, SRL_PARTS,
386 /// Conversion operators. These are all single input single output
387 /// operations. For all of these, the result type must be strictly
388 /// wider or narrower (depending on the operation) than the source
391 /// SIGN_EXTEND - Used for integer types, replicating the sign bit
395 /// ZERO_EXTEND - Used for integer types, zeroing the new bits.
398 /// ANY_EXTEND - Used for integer types. The high bits are undefined.
401 /// TRUNCATE - Completely drop the high bits.
404 /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign
405 /// depends on the first letter) to floating point.
409 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to
410 /// sign extend a small value in a large integer register (e.g. sign
411 /// extending the low 8 bits of a 32-bit register to fill the top 24 bits
412 /// with the 7th bit). The size of the smaller type is indicated by the 1th
413 /// operand, a ValueType node.
416 /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an
417 /// in-register any-extension of the low lanes of an integer vector. The
418 /// result type must have fewer elements than the operand type, and those
419 /// elements must be larger integer types such that the total size of the
420 /// operand type and the result type match. Each of the low operand
421 /// elements is any-extended into the corresponding, wider result
422 /// elements with the high bits becoming undef.
423 ANY_EXTEND_VECTOR_INREG,
425 /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an
426 /// in-register sign-extension of the low lanes of an integer vector. The
427 /// result type must have fewer elements than the operand type, and those
428 /// elements must be larger integer types such that the total size of the
429 /// operand type and the result type match. Each of the low operand
430 /// elements is sign-extended into the corresponding, wider result
432 // FIXME: The SIGN_EXTEND_INREG node isn't specifically limited to
433 // scalars, but it also doesn't handle vectors well. Either it should be
434 // restricted to scalars or this node (and its handling) should be merged
436 SIGN_EXTEND_VECTOR_INREG,
438 /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an
439 /// in-register zero-extension of the low lanes of an integer vector. The
440 /// result type must have fewer elements than the operand type, and those
441 /// elements must be larger integer types such that the total size of the
442 /// operand type and the result type match. Each of the low operand
443 /// elements is zero-extended into the corresponding, wider result
445 ZERO_EXTEND_VECTOR_INREG,
447 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned
452 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type
453 /// down to the precision of the destination VT. TRUNC is a flag, which is
454 /// always an integer that is zero or one. If TRUNC is 0, this is a
455 /// normal rounding, if it is 1, this FP_ROUND is known to not change the
458 /// The TRUNC = 1 case is used in cases where we know that the value will
459 /// not be modified by the node, because Y is not using any of the extra
460 /// precision of source type. This allows certain transformations like
461 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for
462 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed.
465 /// FLT_ROUNDS_ - Returns current rounding mode:
468 /// 1 Round to nearest
473 /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and
474 /// rounds it to a floating point value. It then promotes it and returns it
475 /// in a register of the same size. This operation effectively just
476 /// discards excess precision. The type to round down to is specified by
477 /// the VT operand, a VTSDNode.
480 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
483 /// BITCAST - This operator converts between integer, vector and FP
484 /// values, as if the value was stored to memory with one type and loaded
485 /// from the same address with the other type (or equivalently for vector
486 /// format conversions, etc). The source and result are required to have
487 /// the same bit size (e.g. f32 <-> i32). This can also be used for
488 /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by
492 /// ADDRSPACECAST - This operator converts between pointers of different
496 /// CONVERT_RNDSAT - This operator is used to support various conversions
497 /// between various types (float, signed, unsigned and vectors of those
498 /// types) with rounding and saturation. NOTE: Avoid using this operator as
499 /// most target don't support it and the operator might be removed in the
500 /// future. It takes the following arguments:
502 /// 1) dest type (type to convert to)
503 /// 2) src type (type to convert from)
505 /// 4) saturation imm
506 /// 5) ISD::CvtCode indicating the type of conversion to do
509 /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions
510 /// and truncation for half-precision (16 bit) floating numbers. These nodes
511 /// form a semi-softened interface for dealing with f16 (as an i16), which
512 /// is often a storage-only type but has native conversions.
513 FP16_TO_FP, FP_TO_FP16,
515 /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
516 /// FLOG, FLOG2, FLOG10, FEXP, FEXP2,
517 /// FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary
518 /// floating point operations. These are inspired by libm.
519 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW,
520 FLOG, FLOG2, FLOG10, FEXP, FEXP2,
521 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR,
522 /// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
524 /// In the case where a single input is NaN, the non-NaN input is returned.
526 /// The return value of (FMINNUM 0.0, -0.0) could be either 0.0 or -0.0.
528 /// FMINNAN/FMAXNAN - Behave identically to FMINNUM/FMAXNUM, except that
529 /// when a single input is NaN, NaN is returned.
532 /// FSINCOS - Compute both fsin and fcos as a single operation.
535 /// LOAD and STORE have token chains as their first operand, then the same
536 /// operands as an LLVM load/store instruction, then an offset node that
537 /// is added / subtracted from the base pointer to form the address (for
538 /// indexed memory ops).
541 /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned
542 /// to a specified boundary. This node always has two return values: a new
543 /// stack pointer value and a chain. The first operand is the token chain,
544 /// the second is the number of bytes to allocate, and the third is the
545 /// alignment boundary. The size is guaranteed to be a multiple of the
546 /// stack alignment, and the alignment is guaranteed to be bigger than the
547 /// stack alignment (if required) or 0 to get standard stack alignment.
550 /// Control flow instructions. These all have token chains.
552 /// BR - Unconditional branch. The first operand is the chain
553 /// operand, the second is the MBB to branch to.
556 /// BRIND - Indirect branch. The first operand is the chain, the second
557 /// is the value to branch to, which must be of the same type as the
558 /// target's pointer type.
561 /// BR_JT - Jumptable branch. The first operand is the chain, the second
562 /// is the jumptable index, the last one is the jumptable entry index.
565 /// BRCOND - Conditional branch. The first operand is the chain, the
566 /// second is the condition, the third is the block to branch to if the
567 /// condition is true. If the type of the condition is not i1, then the
568 /// high bits must conform to getBooleanContents.
571 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in
572 /// that the condition is represented as condition code, and two nodes to
573 /// compare, rather than as a combined SetCC node. The operands in order
574 /// are chain, cc, lhs, rhs, block to branch to if condition is true.
577 /// INLINEASM - Represents an inline asm block. This node always has two
578 /// return values: a chain and a flag result. The inputs are as follows:
579 /// Operand #0 : Input chain.
580 /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string.
581 /// Operand #2 : a MDNodeSDNode with the !srcloc metadata.
582 /// Operand #3 : HasSideEffect, IsAlignStack bits.
583 /// After this, it is followed by a list of operands with this format:
584 /// ConstantSDNode: Flags that encode whether it is a mem or not, the
585 /// of operands that follow, etc. See InlineAsm.h.
586 /// ... however many operands ...
587 /// Operand #last: Optional, an incoming flag.
589 /// The variable width operands are required to represent target addressing
590 /// modes as a single "operand", even though they may have multiple
594 /// EH_LABEL - Represents a label in mid basic block used to track
595 /// locations needed for debug and exception handling tables. These nodes
596 /// take a chain as input and return a chain.
599 /// CATCHPAD - Represents a catchpad instruction.
602 /// CATCHRET - Represents a return from a catch block funclet. Used for
603 /// MSVC compatible exception handling. Takes a chain operand and a
604 /// destination basic block operand.
607 /// CLEANUPRET - Represents a return from a cleanup block funclet. Used for
608 /// MSVC compatible exception handling. Takes only a chain operand.
611 /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a
612 /// value, the same type as the pointer type for the system, and an output
616 /// STACKRESTORE has two operands, an input chain and a pointer to restore
617 /// to it returns an output chain.
620 /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end
621 /// of a call sequence, and carry arbitrary information that target might
622 /// want to know. The first operand is a chain, the rest are specified by
623 /// the target and not touched by the DAG optimizers.
624 /// CALLSEQ_START..CALLSEQ_END pairs may not be nested.
625 CALLSEQ_START, // Beginning of a call sequence
626 CALLSEQ_END, // End of a call sequence
628 /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE,
629 /// and the alignment. It returns a pair of values: the vaarg value and a
633 /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer,
634 /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the
638 /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain,
639 /// pointer, and a SRCVALUE.
642 /// SRCVALUE - This is a node type that holds a Value* that is used to
643 /// make reference to a value in the LLVM IR.
646 /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to
647 /// reference metadata in the IR.
650 /// PCMARKER - This corresponds to the pcmarker intrinsic.
653 /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
654 /// It produces a chain and one i64 value. The only operand is a chain.
655 /// If i64 is not legal, the result will be expanded into smaller values.
656 /// Still, it returns an i64, so targets should set legality for i64.
657 /// The result is the content of the architecture-specific cycle
658 /// counter-like register (or other high accuracy low latency clock source).
661 /// HANDLENODE node - Used as a handle for various purposes.
664 /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It
665 /// takes as input a token chain, the pointer to the trampoline, the pointer
666 /// to the nested function, the pointer to pass for the 'nest' parameter, a
667 /// SRCVALUE for the trampoline and another for the nested function
668 /// (allowing targets to access the original Function*).
669 /// It produces a token chain as output.
672 /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
673 /// It takes a pointer to the trampoline and produces a (possibly) new
674 /// pointer to the same trampoline with platform-specific adjustments
675 /// applied. The pointer it returns points to an executable block of code.
678 /// TRAP - Trapping instruction
681 /// DEBUGTRAP - Trap intended to get the attention of a debugger.
684 /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand
685 /// is the chain. The other operands are the address to prefetch,
686 /// read / write specifier, locality specifier and instruction / data cache
690 /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope)
691 /// This corresponds to the fence instruction. It takes an input chain, and
692 /// two integer constants: an AtomicOrdering and a SynchronizationScope.
695 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr)
696 /// This corresponds to "load atomic" instruction.
699 /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val)
700 /// This corresponds to "store atomic" instruction.
703 /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
704 /// For double-word atomic operations:
705 /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi,
707 /// This corresponds to the cmpxchg instruction.
710 /// Val, Success, OUTCHAIN
711 /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap)
712 /// N.b. this is still a strong cmpxchg operation, so
713 /// Success == "Val == cmp".
714 ATOMIC_CMP_SWAP_WITH_SUCCESS,
716 /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt)
717 /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt)
718 /// For double-word atomic operations:
719 /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi)
720 /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi)
721 /// These correspond to the atomicrmw instruction.
734 // Masked load and store - consecutive vector load and store operations
735 // with additional mask operand that prevents memory accesses to the
739 // Masked gather and scatter - load and store operations for a vector of
740 // random addresses with additional mask operand that prevents memory
741 // accesses to the masked-off lanes.
744 /// This corresponds to the llvm.lifetime.* intrinsics. The first operand
745 /// is the chain and the second operand is the alloca pointer.
746 LIFETIME_START, LIFETIME_END,
748 /// GC_TRANSITION_START/GC_TRANSITION_END - These operators mark the
749 /// beginning and end of GC transition sequence, and carry arbitrary
750 /// information that target might need for lowering. The first operand is
751 /// a chain, the rest are specified by the target and not touched by the DAG
752 /// optimizers. GC_TRANSITION_START..GC_TRANSITION_END pairs may not be
757 /// BUILTIN_OP_END - This must be the last enum value in this list.
758 /// The target-specific pre-isel opcode values start here.
762 /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations
763 /// which do not reference a specific memory location should be less than
764 /// this value. Those that do must not be less than this value, and can
765 /// be used with SelectionDAG::getMemIntrinsicNode.
766 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+300;
768 //===--------------------------------------------------------------------===//
769 /// MemIndexedMode enum - This enum defines the load / store indexed
770 /// addressing modes.
772 /// UNINDEXED "Normal" load / store. The effective address is already
773 /// computed and is available in the base pointer. The offset
774 /// operand is always undefined. In addition to producing a
775 /// chain, an unindexed load produces one value (result of the
776 /// load); an unindexed store does not produce a value.
778 /// PRE_INC Similar to the unindexed mode where the effective address is
779 /// PRE_DEC the value of the base pointer add / subtract the offset.
780 /// It considers the computation as being folded into the load /
781 /// store operation (i.e. the load / store does the address
782 /// computation as well as performing the memory transaction).
783 /// The base operand is always undefined. In addition to
784 /// producing a chain, pre-indexed load produces two values
785 /// (result of the load and the result of the address
786 /// computation); a pre-indexed store produces one value (result
787 /// of the address computation).
789 /// POST_INC The effective address is the value of the base pointer. The
790 /// POST_DEC value of the offset operand is then added to / subtracted
791 /// from the base after memory transaction. In addition to
792 /// producing a chain, post-indexed load produces two values
793 /// (the result of the load and the result of the base +/- offset
794 /// computation); a post-indexed store produces one value (the
795 /// the result of the base +/- offset computation).
796 enum MemIndexedMode {
805 //===--------------------------------------------------------------------===//
806 /// LoadExtType enum - This enum defines the three variants of LOADEXT
807 /// (load with extension).
809 /// SEXTLOAD loads the integer operand and sign extends it to a larger
810 /// integer result type.
811 /// ZEXTLOAD loads the integer operand and zero extends it to a larger
812 /// integer result type.
813 /// EXTLOAD is used for two things: floating point extending loads and
814 /// integer extending loads [the top bits are undefined].
823 NodeType getExtForLoadExtType(bool IsFP, LoadExtType);
825 //===--------------------------------------------------------------------===//
826 /// ISD::CondCode enum - These are ordered carefully to make the bitfields
827 /// below work out, when considering SETFALSE (something that never exists
828 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered
829 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal
830 /// to. If the "N" column is 1, the result of the comparison is undefined if
831 /// the input is a NAN.
833 /// All of these (except for the 'always folded ops') should be handled for
834 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT,
835 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used.
837 /// Note that these are laid out in a specific order to allow bit-twiddling
838 /// to transform conditions.
840 // Opcode N U L G E Intuitive operation
841 SETFALSE, // 0 0 0 0 Always false (always folded)
842 SETOEQ, // 0 0 0 1 True if ordered and equal
843 SETOGT, // 0 0 1 0 True if ordered and greater than
844 SETOGE, // 0 0 1 1 True if ordered and greater than or equal
845 SETOLT, // 0 1 0 0 True if ordered and less than
846 SETOLE, // 0 1 0 1 True if ordered and less than or equal
847 SETONE, // 0 1 1 0 True if ordered and operands are unequal
848 SETO, // 0 1 1 1 True if ordered (no nans)
849 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y)
850 SETUEQ, // 1 0 0 1 True if unordered or equal
851 SETUGT, // 1 0 1 0 True if unordered or greater than
852 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal
853 SETULT, // 1 1 0 0 True if unordered or less than
854 SETULE, // 1 1 0 1 True if unordered, less than, or equal
855 SETUNE, // 1 1 1 0 True if unordered or not equal
856 SETTRUE, // 1 1 1 1 Always true (always folded)
857 // Don't care operations: undefined if the input is a nan.
858 SETFALSE2, // 1 X 0 0 0 Always false (always folded)
859 SETEQ, // 1 X 0 0 1 True if equal
860 SETGT, // 1 X 0 1 0 True if greater than
861 SETGE, // 1 X 0 1 1 True if greater than or equal
862 SETLT, // 1 X 1 0 0 True if less than
863 SETLE, // 1 X 1 0 1 True if less than or equal
864 SETNE, // 1 X 1 1 0 True if not equal
865 SETTRUE2, // 1 X 1 1 1 Always true (always folded)
867 SETCC_INVALID // Marker value.
870 /// isSignedIntSetCC - Return true if this is a setcc instruction that
871 /// performs a signed comparison when used with integer operands.
872 inline bool isSignedIntSetCC(CondCode Code) {
873 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE;
876 /// isUnsignedIntSetCC - Return true if this is a setcc instruction that
877 /// performs an unsigned comparison when used with integer operands.
878 inline bool isUnsignedIntSetCC(CondCode Code) {
879 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE;
882 /// isTrueWhenEqual - Return true if the specified condition returns true if
883 /// the two operands to the condition are equal. Note that if one of the two
884 /// operands is a NaN, this value is meaningless.
885 inline bool isTrueWhenEqual(CondCode Cond) {
886 return ((int)Cond & 1) != 0;
889 /// getUnorderedFlavor - This function returns 0 if the condition is always
890 /// false if an operand is a NaN, 1 if the condition is always true if the
891 /// operand is a NaN, and 2 if the condition is undefined if the operand is a
893 inline unsigned getUnorderedFlavor(CondCode Cond) {
894 return ((int)Cond >> 3) & 3;
897 /// getSetCCInverse - Return the operation corresponding to !(X op Y), where
898 /// 'op' is a valid SetCC operation.
899 CondCode getSetCCInverse(CondCode Operation, bool isInteger);
901 /// getSetCCSwappedOperands - Return the operation corresponding to (Y op X)
902 /// when given the operation for (X op Y).
903 CondCode getSetCCSwappedOperands(CondCode Operation);
905 /// getSetCCOrOperation - Return the result of a logical OR between different
906 /// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This
907 /// function returns SETCC_INVALID if it is not possible to represent the
908 /// resultant comparison.
909 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
911 /// getSetCCAndOperation - Return the result of a logical AND between
912 /// different comparisons of identical values: ((X op1 Y) & (X op2 Y)). This
913 /// function returns SETCC_INVALID if it is not possible to represent the
914 /// resultant comparison.
915 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
917 //===--------------------------------------------------------------------===//
918 /// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT
921 CVT_FF, /// Float from Float
922 CVT_FS, /// Float from Signed
923 CVT_FU, /// Float from Unsigned
924 CVT_SF, /// Signed from Float
925 CVT_UF, /// Unsigned from Float
926 CVT_SS, /// Signed from Signed
927 CVT_SU, /// Signed from Unsigned
928 CVT_US, /// Unsigned from Signed
929 CVT_UU, /// Unsigned from Unsigned
930 CVT_INVALID /// Marker - Invalid opcode
933 } // end llvm::ISD namespace
935 } // end llvm namespace