1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/BasicBlock.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/SelectionDAGNodes.h"
23 class MachineBasicBlock;
24 class MachineFunction;
25 class TargetInstrInfo;
26 class TargetRegisterClass;
28 /// FastISel - This is a fast-path instruction selection class that
29 /// generates poor code and doesn't support illegal types or non-trivial
30 /// lowering, but runs quickly.
32 MachineBasicBlock *MBB;
34 const TargetInstrInfo *TII;
37 /// SelectInstructions - Do "fast" instruction selection over the
38 /// LLVM IR instructions in the range [Begin, N) where N is either
39 /// End or the first unsupported instruction. Return N.
40 /// ValueMap is filled in with a mapping of LLVM IR Values to
43 SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
44 DenseMap<const Value*, unsigned> &ValueMap);
49 FastISel(MachineBasicBlock *mbb, MachineFunction *mf,
50 const TargetInstrInfo *tii)
51 : MBB(mbb), MF(mf), TII(tii) {}
53 /// FastEmit_r - This method is called by target-independent code
54 /// to request that an instruction with the given type and opcode
56 virtual unsigned FastEmit_(MVT::SimpleValueType VT,
57 ISD::NodeType Opcode);
59 /// FastEmit_r - This method is called by target-independent code
60 /// to request that an instruction with the given type, opcode, and
61 /// register operand be emitted.
63 virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
64 ISD::NodeType Opcode, unsigned Op0);
66 /// FastEmit_rr - This method is called by target-independent code
67 /// to request that an instruction with the given type, opcode, and
68 /// register operands be emitted.
70 virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
72 unsigned Op0, unsigned Op1);
74 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
75 /// result register in the given register class.
77 unsigned FastEmitInst_(unsigned MachineInstOpcode,
78 const TargetRegisterClass *RC);
80 /// FastEmitInst_ - Emit a MachineInstr with one register operand
81 /// and a result register in the given register class.
83 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
84 const TargetRegisterClass *RC,
87 /// FastEmitInst_ - Emit a MachineInstr with two register operands
88 /// and a result register in the given register class.
90 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
91 const TargetRegisterClass *RC,
92 unsigned Op0, unsigned Op1);
95 bool SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
96 DenseMap<const Value*, unsigned> &ValueMap);
98 bool SelectGetElementPtr(Instruction *I,
99 DenseMap<const Value*, unsigned> &ValueMap);