1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/BasicBlock.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/SelectionDAGNodes.h"
23 class MachineBasicBlock;
24 class MachineFunction;
25 class MachineRegisterInfo;
27 class TargetInstrInfo;
30 class TargetRegisterClass;
32 /// FastISel - This is a fast-path instruction selection class that
33 /// generates poor code and doesn't support illegal types or non-trivial
34 /// lowering, but runs quickly.
37 MachineBasicBlock *MBB;
39 MachineRegisterInfo &MRI;
40 const TargetMachine &TM;
42 const TargetInstrInfo &TII;
43 const TargetLowering &TLI;
46 /// SelectInstructions - Do "fast" instruction selection over the
47 /// LLVM IR instructions in the range [Begin, N) where N is either
48 /// End or the first unsupported instruction. Return N.
49 /// ValueMap is filled in with a mapping of LLVM IR Values to
50 /// virtual register numbers. MBB is a block to which to append
51 /// the generated MachineInstrs.
53 SelectInstructions(BasicBlock::iterator Begin, BasicBlock::iterator End,
54 DenseMap<const Value*, unsigned> &ValueMap,
55 MachineBasicBlock *MBB);
60 explicit FastISel(MachineFunction &mf);
62 /// FastEmit_r - This method is called by target-independent code
63 /// to request that an instruction with the given type and opcode
65 virtual unsigned FastEmit_(MVT::SimpleValueType VT,
66 ISD::NodeType Opcode);
68 /// FastEmit_r - This method is called by target-independent code
69 /// to request that an instruction with the given type, opcode, and
70 /// register operand be emitted.
72 virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
73 ISD::NodeType Opcode, unsigned Op0);
75 /// FastEmit_rr - This method is called by target-independent code
76 /// to request that an instruction with the given type, opcode, and
77 /// register operands be emitted.
79 virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
81 unsigned Op0, unsigned Op1);
83 /// FastEmit_i - This method is called by target-independent code
84 /// to request that an instruction with the given type which materialize
85 /// the specified immediate value.
86 virtual unsigned FastEmit_i(MVT::SimpleValueType VT, uint64_t Imm);
88 /// FastEmit_ri - This method is called by target-independent code
89 /// to request that an instruction with the given type, opcode, and
90 /// register and immediate operands be emitted.
92 virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
94 unsigned Op0, uint64_t Imm);
96 /// FastEmit_rri - This method is called by target-independent code
97 /// to request that an instruction with the given type, opcode, and
98 /// register and immediate operands be emitted.
100 virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
101 ISD::NodeType Opcode,
102 unsigned Op0, unsigned Op1, uint64_t Imm);
104 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
105 /// to emit an instruction with an immediate operand using FastEmit_ri.
106 /// If that fails, it materializes the immediate into a register and try
107 /// FastEmit_rr instead.
108 unsigned FastEmit_ri_(MVT::SimpleValueType VT,
109 ISD::NodeType Opcode,
110 unsigned Op0, uint64_t Imm,
111 MVT::SimpleValueType ImmType);
113 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
114 /// result register in the given register class.
116 unsigned FastEmitInst_(unsigned MachineInstOpcode,
117 const TargetRegisterClass *RC);
119 /// FastEmitInst_r - Emit a MachineInstr with one register operand
120 /// and a result register in the given register class.
122 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
123 const TargetRegisterClass *RC,
126 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
127 /// and a result register in the given register class.
129 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
130 const TargetRegisterClass *RC,
131 unsigned Op0, unsigned Op1);
133 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
134 /// and a result register in the given register class.
136 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
137 const TargetRegisterClass *RC,
138 unsigned Op0, uint64_t Imm);
140 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
141 /// an immediate, and a result register in the given register class.
143 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
144 const TargetRegisterClass *RC,
145 unsigned Op0, unsigned Op1, uint64_t Imm);
148 unsigned createResultReg(const TargetRegisterClass *RC);
150 bool SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
151 DenseMap<const Value*, unsigned> &ValueMap);
153 bool SelectGetElementPtr(Instruction *I,
154 DenseMap<const Value*, unsigned> &ValueMap);