1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/CodeGen/ValueTypes.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
25 class FunctionLoweringInfo;
27 class MachineBasicBlock;
28 class MachineConstantPool;
29 class MachineFunction;
31 class MachineFrameInfo;
32 class MachineRegisterInfo;
34 class TargetInstrInfo;
37 class TargetRegisterClass;
38 class TargetRegisterInfo;
41 /// FastISel - This is a fast-path instruction selection class that
42 /// generates poor code and doesn't support illegal types or non-trivial
43 /// lowering, but runs quickly.
46 DenseMap<const Value *, unsigned> LocalValueMap;
47 FunctionLoweringInfo &FuncInfo;
48 MachineRegisterInfo &MRI;
49 MachineFrameInfo &MFI;
50 MachineConstantPool &MCP;
52 const TargetMachine &TM;
54 const TargetInstrInfo &TII;
55 const TargetLowering &TLI;
56 const TargetRegisterInfo &TRI;
57 MachineInstr *LastLocalValue;
60 /// getLastLocalValue - Return the position of the last instruction
61 /// emitted for materializing constants for use in the current block.
62 MachineInstr *getLastLocalValue() { return LastLocalValue; }
64 /// setLastLocalValue - Update the position of the last instruction
65 /// emitted for materializing constants for use in the current block.
66 void setLastLocalValue(MachineInstr *I) { LastLocalValue = I; }
68 /// startNewBlock - Set the current block to which generated machine
69 /// instructions will be appended, and clear the local CSE map.
73 /// getCurDebugLoc() - Return current debug location information.
74 DebugLoc getCurDebugLoc() const { return DL; }
76 /// SelectInstruction - Do "fast" instruction selection for the given
77 /// LLVM IR instruction, and append generated machine instructions to
78 /// the current block. Return true if selection was successful.
80 bool SelectInstruction(const Instruction *I);
82 /// SelectOperator - Do "fast" instruction selection for the given
83 /// LLVM IR operator (Instruction or ConstantExpr), and append
84 /// generated machine instructions to the current block. Return true
85 /// if selection was successful.
87 bool SelectOperator(const User *I, unsigned Opcode);
89 /// getRegForValue - Create a virtual register and arrange for it to
90 /// be assigned the value for the given LLVM value.
91 unsigned getRegForValue(const Value *V);
93 /// lookUpRegForValue - Look up the value to see if its value is already
94 /// cached in a register. It may be defined by instructions across blocks or
96 unsigned lookUpRegForValue(const Value *V);
98 /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
99 /// takes care of truncating or sign-extending the given getelementptr
101 std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
103 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that
104 /// vreg is being provided by the specified load instruction. If possible,
105 /// try to fold the load as an operand to the instruction, returning true if
107 virtual bool TryToFoldLoad(MachineInstr * /*MI*/, unsigned /*OpNo*/,
108 const LoadInst * /*LI*/) {
112 /// recomputeInsertPt - Reset InsertPt to prepare for inserting instructions
113 /// into the current block.
114 void recomputeInsertPt();
117 MachineBasicBlock::iterator InsertPt;
121 /// enterLocalValueArea - Prepare InsertPt to begin inserting instructions
122 /// into the local value area and return the old insert position.
123 SavePoint enterLocalValueArea();
125 /// leaveLocalValueArea - Reset InsertPt to the given old insert position.
126 void leaveLocalValueArea(SavePoint Old);
131 explicit FastISel(FunctionLoweringInfo &funcInfo);
133 /// TargetSelectInstruction - This method is called by target-independent
134 /// code when the normal FastISel process fails to select an instruction.
135 /// This gives targets a chance to emit code for anything that doesn't
136 /// fit into FastISel's framework. It returns true if it was successful.
139 TargetSelectInstruction(const Instruction *I) = 0;
141 /// FastEmit_r - This method is called by target-independent code
142 /// to request that an instruction with the given type and opcode
144 virtual unsigned FastEmit_(MVT VT,
148 /// FastEmit_r - This method is called by target-independent code
149 /// to request that an instruction with the given type, opcode, and
150 /// register operand be emitted.
152 virtual unsigned FastEmit_r(MVT VT,
155 unsigned Op0, bool Op0IsKill);
157 /// FastEmit_rr - This method is called by target-independent code
158 /// to request that an instruction with the given type, opcode, and
159 /// register operands be emitted.
161 virtual unsigned FastEmit_rr(MVT VT,
164 unsigned Op0, bool Op0IsKill,
165 unsigned Op1, bool Op1IsKill);
167 /// FastEmit_ri - This method is called by target-independent code
168 /// to request that an instruction with the given type, opcode, and
169 /// register and immediate operands be emitted.
171 virtual unsigned FastEmit_ri(MVT VT,
174 unsigned Op0, bool Op0IsKill,
177 /// FastEmit_rf - This method is called by target-independent code
178 /// to request that an instruction with the given type, opcode, and
179 /// register and floating-point immediate operands be emitted.
181 virtual unsigned FastEmit_rf(MVT VT,
184 unsigned Op0, bool Op0IsKill,
185 const ConstantFP *FPImm);
187 /// FastEmit_rri - This method is called by target-independent code
188 /// to request that an instruction with the given type, opcode, and
189 /// register and immediate operands be emitted.
191 virtual unsigned FastEmit_rri(MVT VT,
194 unsigned Op0, bool Op0IsKill,
195 unsigned Op1, bool Op1IsKill,
198 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
199 /// to emit an instruction with an immediate operand using FastEmit_ri.
200 /// If that fails, it materializes the immediate into a register and try
201 /// FastEmit_rr instead.
202 unsigned FastEmit_ri_(MVT VT,
204 unsigned Op0, bool Op0IsKill,
205 uint64_t Imm, MVT ImmType);
207 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
208 /// to emit an instruction with an immediate operand using FastEmit_rf.
209 /// If that fails, it materializes the immediate into a register and try
210 /// FastEmit_rr instead.
211 unsigned FastEmit_rf_(MVT VT,
213 unsigned Op0, bool Op0IsKill,
214 const ConstantFP *FPImm, MVT ImmType);
216 /// FastEmit_i - This method is called by target-independent code
217 /// to request that an instruction with the given type, opcode, and
218 /// immediate operand be emitted.
219 virtual unsigned FastEmit_i(MVT VT,
224 /// FastEmit_f - This method is called by target-independent code
225 /// to request that an instruction with the given type, opcode, and
226 /// floating-point immediate operand be emitted.
227 virtual unsigned FastEmit_f(MVT VT,
230 const ConstantFP *FPImm);
232 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
233 /// result register in the given register class.
235 unsigned FastEmitInst_(unsigned MachineInstOpcode,
236 const TargetRegisterClass *RC);
238 /// FastEmitInst_r - Emit a MachineInstr with one register operand
239 /// and a result register in the given register class.
241 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
242 const TargetRegisterClass *RC,
243 unsigned Op0, bool Op0IsKill);
245 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
246 /// and a result register in the given register class.
248 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
249 const TargetRegisterClass *RC,
250 unsigned Op0, bool Op0IsKill,
251 unsigned Op1, bool Op1IsKill);
253 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
254 /// and a result register in the given register class.
256 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
257 const TargetRegisterClass *RC,
258 unsigned Op0, bool Op0IsKill,
261 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
262 /// and a result register in the given register class.
264 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
265 const TargetRegisterClass *RC,
266 unsigned Op0, bool Op0IsKill,
267 const ConstantFP *FPImm);
269 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
270 /// an immediate, and a result register in the given register class.
272 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
273 const TargetRegisterClass *RC,
274 unsigned Op0, bool Op0IsKill,
275 unsigned Op1, bool Op1IsKill,
278 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
279 /// operand, and a result register in the given register class.
280 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
281 const TargetRegisterClass *RC,
284 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
285 /// from a specified index of a superregister to a specified type.
286 unsigned FastEmitInst_extractsubreg(MVT RetVT,
287 unsigned Op0, bool Op0IsKill,
290 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
291 /// with all but the least significant bit set to zero.
292 unsigned FastEmitZExtFromI1(MVT VT,
293 unsigned Op0, bool Op0IsKill);
295 /// FastEmitBranch - Emit an unconditional branch to the given block,
296 /// unless it is the immediate (fall-through) successor, and update
298 void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
300 unsigned UpdateValueMap(const Value* I, unsigned Reg);
302 unsigned createResultReg(const TargetRegisterClass *RC);
304 /// TargetMaterializeConstant - Emit a constant in a register using
305 /// target-specific logic, such as constant pool loads.
306 virtual unsigned TargetMaterializeConstant(const Constant* C) {
310 /// TargetMaterializeAlloca - Emit an alloca address in a register using
311 /// target-specific logic.
312 virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) {
317 bool SelectBinaryOp(const User *I, unsigned ISDOpcode);
319 bool SelectFNeg(const User *I);
321 bool SelectGetElementPtr(const User *I);
323 bool SelectCall(const User *I);
325 bool SelectBitCast(const User *I);
327 bool SelectCast(const User *I, unsigned Opcode);
329 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
330 /// Emit code to ensure constants are copied into registers when needed.
331 /// Remember the virtual registers that need to be added to the Machine PHI
332 /// nodes as input. We cannot just directly add them, because expansion
333 /// might result in multiple MBB's for one BB. As such, the start of the
334 /// BB might correspond to a different MBB than the end.
335 bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
337 /// materializeRegForValue - Helper for getRegForVale. This function is
338 /// called when the value isn't already available in a register and must
339 /// be materialized with new instructions.
340 unsigned materializeRegForValue(const Value *V, MVT VT);
342 /// hasTrivialKill - Test whether the given value has exactly one use.
343 bool hasTrivialKill(const Value *V) const;