1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
27 class MachineBasicBlock;
28 class MachineConstantPool;
29 class MachineFunction;
30 class MachineFrameInfo;
31 class MachineRegisterInfo;
33 class TargetInstrInfo;
36 class TargetRegisterClass;
38 /// FastISel - This is a fast-path instruction selection class that
39 /// generates poor code and doesn't support illegal types or non-trivial
40 /// lowering, but runs quickly.
43 MachineBasicBlock *MBB;
44 DenseMap<const Value *, unsigned> LocalValueMap;
45 DenseMap<const Value *, unsigned> &ValueMap;
46 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
47 DenseMap<const AllocaInst *, int> &StaticAllocaMap;
49 SmallSet<Instruction*, 8> &CatchInfoLost;
52 MachineRegisterInfo &MRI;
53 MachineFrameInfo &MFI;
54 MachineConstantPool &MCP;
56 const TargetMachine &TM;
58 const TargetInstrInfo &TII;
59 const TargetLowering &TLI;
62 /// startNewBlock - Set the current block to which generated machine
63 /// instructions will be appended, and clear the local CSE map.
65 void startNewBlock(MachineBasicBlock *mbb) {
67 LocalValueMap.clear();
70 /// setCurrentBlock - Set the current block to which generated machine
71 /// instructions will be appended.
73 void setCurrentBlock(MachineBasicBlock *mbb) {
77 /// setCurDebugLoc - Set the current debug location information, which is used
78 /// when creating a machine instruction.
80 void setCurDebugLoc(DebugLoc dl) { DL = dl; }
82 /// getCurDebugLoc() - Return current debug location information.
83 DebugLoc getCurDebugLoc() const { return DL; }
85 /// SelectInstruction - Do "fast" instruction selection for the given
86 /// LLVM IR instruction, and append generated machine instructions to
87 /// the current block. Return true if selection was successful.
89 bool SelectInstruction(Instruction *I);
91 /// SelectOperator - Do "fast" instruction selection for the given
92 /// LLVM IR operator (Instruction or ConstantExpr), and append
93 /// generated machine instructions to the current block. Return true
94 /// if selection was successful.
96 bool SelectOperator(User *I, unsigned Opcode);
98 /// getRegForValue - Create a virtual register and arrange for it to
99 /// be assigned the value for the given LLVM value.
100 unsigned getRegForValue(Value *V);
102 /// lookUpRegForValue - Look up the value to see if its value is already
103 /// cached in a register. It may be defined by instructions across blocks or
105 unsigned lookUpRegForValue(Value *V);
107 /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
108 /// takes care of truncating or sign-extending the given getelementptr
110 unsigned getRegForGEPIndex(Value *V);
115 FastISel(MachineFunction &mf,
116 DenseMap<const Value *, unsigned> &vm,
117 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
118 DenseMap<const AllocaInst *, int> &am
120 , SmallSet<Instruction*, 8> &cil
124 /// TargetSelectInstruction - This method is called by target-independent
125 /// code when the normal FastISel process fails to select an instruction.
126 /// This gives targets a chance to emit code for anything that doesn't
127 /// fit into FastISel's framework. It returns true if it was successful.
130 TargetSelectInstruction(Instruction *I) = 0;
132 /// FastEmit_r - This method is called by target-independent code
133 /// to request that an instruction with the given type and opcode
135 virtual unsigned FastEmit_(MVT VT,
139 /// FastEmit_r - This method is called by target-independent code
140 /// to request that an instruction with the given type, opcode, and
141 /// register operand be emitted.
143 virtual unsigned FastEmit_r(MVT VT,
145 unsigned Opcode, unsigned Op0);
147 /// FastEmit_rr - This method is called by target-independent code
148 /// to request that an instruction with the given type, opcode, and
149 /// register operands be emitted.
151 virtual unsigned FastEmit_rr(MVT VT,
154 unsigned Op0, unsigned Op1);
156 /// FastEmit_ri - This method is called by target-independent code
157 /// to request that an instruction with the given type, opcode, and
158 /// register and immediate operands be emitted.
160 virtual unsigned FastEmit_ri(MVT VT,
163 unsigned Op0, uint64_t Imm);
165 /// FastEmit_rf - This method is called by target-independent code
166 /// to request that an instruction with the given type, opcode, and
167 /// register and floating-point immediate operands be emitted.
169 virtual unsigned FastEmit_rf(MVT VT,
172 unsigned Op0, ConstantFP *FPImm);
174 /// FastEmit_rri - This method is called by target-independent code
175 /// to request that an instruction with the given type, opcode, and
176 /// register and immediate operands be emitted.
178 virtual unsigned FastEmit_rri(MVT VT,
181 unsigned Op0, unsigned Op1, uint64_t Imm);
183 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
184 /// to emit an instruction with an immediate operand using FastEmit_ri.
185 /// If that fails, it materializes the immediate into a register and try
186 /// FastEmit_rr instead.
187 unsigned FastEmit_ri_(MVT VT,
189 unsigned Op0, uint64_t Imm,
192 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
193 /// to emit an instruction with an immediate operand using FastEmit_rf.
194 /// If that fails, it materializes the immediate into a register and try
195 /// FastEmit_rr instead.
196 unsigned FastEmit_rf_(MVT VT,
198 unsigned Op0, ConstantFP *FPImm,
201 /// FastEmit_i - This method is called by target-independent code
202 /// to request that an instruction with the given type, opcode, and
203 /// immediate operand be emitted.
204 virtual unsigned FastEmit_i(MVT VT,
209 /// FastEmit_f - This method is called by target-independent code
210 /// to request that an instruction with the given type, opcode, and
211 /// floating-point immediate operand be emitted.
212 virtual unsigned FastEmit_f(MVT VT,
217 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
218 /// result register in the given register class.
220 unsigned FastEmitInst_(unsigned MachineInstOpcode,
221 const TargetRegisterClass *RC);
223 /// FastEmitInst_r - Emit a MachineInstr with one register operand
224 /// and a result register in the given register class.
226 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
227 const TargetRegisterClass *RC,
230 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
231 /// and a result register in the given register class.
233 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
234 const TargetRegisterClass *RC,
235 unsigned Op0, unsigned Op1);
237 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
238 /// and a result register in the given register class.
240 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
241 const TargetRegisterClass *RC,
242 unsigned Op0, uint64_t Imm);
244 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
245 /// and a result register in the given register class.
247 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
248 const TargetRegisterClass *RC,
249 unsigned Op0, ConstantFP *FPImm);
251 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
252 /// an immediate, and a result register in the given register class.
254 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
255 const TargetRegisterClass *RC,
256 unsigned Op0, unsigned Op1, uint64_t Imm);
258 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
259 /// operand, and a result register in the given register class.
260 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
261 const TargetRegisterClass *RC,
264 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
265 /// from a specified index of a superregister to a specified type.
266 unsigned FastEmitInst_extractsubreg(MVT RetVT,
267 unsigned Op0, uint32_t Idx);
269 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
270 /// with all but the least significant bit set to zero.
271 unsigned FastEmitZExtFromI1(MVT VT,
274 /// FastEmitBranch - Emit an unconditional branch to the given block,
275 /// unless it is the immediate (fall-through) successor, and update
277 void FastEmitBranch(MachineBasicBlock *MBB);
279 unsigned UpdateValueMap(Value* I, unsigned Reg);
281 unsigned createResultReg(const TargetRegisterClass *RC);
283 /// TargetMaterializeConstant - Emit a constant in a register using
284 /// target-specific logic, such as constant pool loads.
285 virtual unsigned TargetMaterializeConstant(Constant* C) {
289 /// TargetMaterializeAlloca - Emit an alloca address in a register using
290 /// target-specific logic.
291 virtual unsigned TargetMaterializeAlloca(AllocaInst* C) {
296 bool SelectBinaryOp(User *I, unsigned ISDOpcode);
298 bool SelectFNeg(User *I);
300 bool SelectGetElementPtr(User *I);
302 bool SelectCall(User *I);
304 bool SelectBitCast(User *I);
306 bool SelectCast(User *I, unsigned Opcode);